CC1150中文资料

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Chipcon
SmartRF ? CC1100
CC1100 Single Chip Low Cost Low Power RF-Transceiver
Applications
? Ultra low power UHF wireless transceivers ? 315/433/868 and 915MHz ISM/SRD band systems ? AMR – Automatic Meter Reading ? Consumer Electronics ? RKE – Two-way Remote Keyless Entry ? ? ? ? ? Low power telemetry Home and building automation Wireless alarm and security systems Industrial monitoring and control Wireless sensor networks
Product Description
The CC1100 is a low cost true single chip UHF transceiver designed for very low power wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915MHz, but can easily be programmed for operation at other frequencies in the 300348MHz, 400-464MHz and 800-928MHz bands. The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 500kbps. Performance can be increased by enabling a Forward Error Correction option, which is integrated in the modem. microcontroller and a few additional passive components.
CC1100 is based on Chipcon’s SmartRF?04
technology in 0.18μm CMOS.
CC1100 provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication and wake on radio.
The main operating parameters and the 64byte transmit/receive FIFOs of CC1100 can be controlled via an SPI interface. In a typical system, the CC1100 will be used together with a
Key Features
? ? ? ? ? ? ? ? Small size (QLP 4x4mm package, 20 pins) True single chip UHF RF transceiver Frequency bands: 300-348MHz, 400464MHz and 800-928MHz High sensitivity (–110dBm at 1.2kbps, 1% packet error rate) Programmable data rate up to 500kbps Low current consumption (15.6mA in RX, 2.4kbps, 433MHz) Programmable output power up to +10dBm for all supported frequencies Excellent receiver selectivity and blocking performance ? ? ? ? ? ? ? ? Very few external components: Totally onchip frequency synthesizer, no external filters or RF switch needed Programmable baseband modem Ideal for multi-channel operation Configurable packet handling hardware Suitable for frequency hopping systems due to a fast settling frequency synthesizer Optional Forward Error Correction with interleaving Separate 64-byte RX and TX data FIFOs Efficient SPI interface: All registers can be programmed with one “burst” transfer
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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Features (continued from front page)
? ? ? ? ? ? ? Digital RSSI output Suited for systems compliant with EN 300 220 (Europe) and FCC CFR Part 15 (US) Wake-on-radio functionality for automatic low-power RX polling Many powerful digital features allow a high-performance RF system to be made using an inexpensive microcontroller Integrated analog temperature sensor Lead-free “green“ package Flexible support for packet oriented systems: On chip support for sync word detection, address check, flexible packet length and automatic CRC handling. Programmable channel filter bandwidth OOK and flexible ASK shaping supported 2-FSK, GFSK and MSK supported. Automatic Frequency Compensation can be used to align the frequency synthesizer to the received centre frequency
SmartRF ? CC1100
? ? Optional automatic whitening and dewhitening of data Support for asynchronous transparent receive/transmit mode for backwards compatibility with existing radio communication protocols Programmable Carrier Sense indicator Programmable Preamble Quality Indicator for detecting preambles and improved protection against sync word detection in random noise Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) Support for per-package Link Quality Indication
? ?
? ?
? ? ? ?
Abbreviations
Abbreviations used in this data sheet are described below.
2-FSK ADC AFC AGC AMR ASK BER CCA CRC CS DC EIRP ESR FEC FIFO FSK GFSK IF LBT LNA LO LQI MCU Binary Frequency Shift Keying Analog to Digital Converter Automatic Frequency Offset Compensation Automatic Gain Control Automatic Meter Reading Amplitude Shift Keying Bit Error Rate Clear Channel Assessment Cyclic Redundancy Check Carrier Sense Direct Current Equivalent Isotropic Radiated Power Equivalent Series Resistance Forward Error Correction First-In-First-Out Frequency Shift Keying Gaussian shaped Frequency Shift Keying Intermediate Frequency Listen Before Transmit Low Noise Amplifier Local Oscillator Link Quality Indicator Microcontroller Unit MSK PA PCB PD PER PLL PQI PQT RCOSC RF RSSI RX SAW SNR SPI TBD TX VCO WOR XOSC XTAL Minimum Shift Keying Power Amplifier Printed Circuit Board Power Down Packet Error Rate Phase Locked Loop Preamble Quality Indicator Preamble Quality Threshold RC Oscillator Radio Frequency Received Signal Strength Indicator Receive, Receive Mode Surface Aqustic Wave Signal to Noise Ratio Serial Peripheral Interface To Be Defined Transmit, Transmit Mode Voltage Controlled Oscillator Wake on Radio, Low power polling Crystal Oscillator Crystal
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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Table Of Contents
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 19.1 19.2 19.3 20 21 22 22.1 22.2 22.3 23 23.1 23.2 23.3 23.4 23.5 24 24.1 24.2 24.3 25 25.1 25.2 25.3 25.4 25.5 26 26.1 26.2 27 27.1
SmartRF ? CC1100
ABSOLUTE MAXIMUM RATINGS ...........................................................................................................5 OPERATING CONDITIONS ......................................................................................................................5 ELECTRICAL SPECIFICATIONS ...............................................................................................................6 GENERAL CHARACTERISTICS ...............................................................................................................7 RF RECEIVE SECTION...........................................................................................................................8 RF TRANSMIT SECTION ........................................................................................................................9 CRYSTAL OSCILLATOR .........................................................................................................................9 LOW POWER RC OSCILLATOR............................................................................................................10 FREQUENCY SYNTHESIZER CHARACTERISTICS ...................................................................................10 ANALOG TEMPERATURE SENSOR ........................................................................................................11 DC CHARACTERISTICS .......................................................................................................................11 POWER ON RESET...............................................................................................................................12 PIN CONFIGURATION ..........................................................................................................................12 CIRCUIT DESCRIPTION ........................................................................................................................14 APPLICATION CIRCUIT ........................................................................................................................14 CONFIGURATION OVERVIEW ..............................................................................................................16 CONFIGURATION SOFTWARE ..............................................................................................................17 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE ...................................................................18 CHIP STATUS BYTE ............................................................................................................................18 REGISTER ACCESS ..............................................................................................................................19 COMMAND STROBES ..........................................................................................................................19 FIFO ACCESS .....................................................................................................................................19 PATABLE ACCESS ............................................................................................................................19 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ...............................................................21 CONFIGURATION INTERFACE ..............................................................................................................21 GENERAL CONTROL AND STATUS PINS ..............................................................................................21 OPTIONAL RADIO CONTROL FEATURE .................................................................................................22 DATA RATE PROGRAMMING ...............................................................................................................22 RECEIVER CHANNEL FILTER BANDWIDTH..........................................................................................22 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION ......................................................23 FREQUENCY OFFSET COMPENSATION.................................................................................................23 BIT SYNCHRONIZATION ......................................................................................................................23 BYTE SYNCHRONIZATION ...................................................................................................................23 PACKET HANDLING HARDWARE SUPPORT .........................................................................................24 DATA WHITENING ...............................................................................................................................24 PACKET FORMAT ................................................................................................................................24 PACKET FILTERING IN RECEIVE MODE ...............................................................................................26 PACKET HANDLING IN TRANSMIT MODE ............................................................................................26 PACKET HANDLING IN RECEIVE MODE ..............................................................................................26 MODULATION FORMATS.....................................................................................................................27 FREQUENCY SHIFT KEYING ................................................................................................................27 MINIMUM SHIFT KEYING....................................................................................................................27 AMPLITUDE MODULATION .................................................................................................................27 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ...................................................27 PREAMBLE QUALITY THRESHOLD (PQT) ...........................................................................................27 RSSI...................................................................................................................................................28 CARRIER SENSE (CS)..........................................................................................................................28 CLEAR CHANNEL ASSESSMENT (CCA) ..............................................................................................28 LINK QUALITY INDICATOR (LQI) .......................................................................................................28 FORWARD ERROR CORRECTION WITH INTERLEAVING ........................................................................29 FORWARD ERROR CORRECTION (FEC)...............................................................................................29 INTERLEAVING ...................................................................................................................................29 RADIO CONTROL ................................................................................................................................30 POWER ON START-UP SEQUENCE.........................................................................................................31
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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27.2 27.3 27.4 27.5 27.6 27.7 28 29 30 30.1 31 32 33 34 35 36 36.1 36.2 37 37.1 37.2 37.3 38 38.1 38.2 38.3 38.4 38.5 39 40 40.1 40.2 40.3 40.4 40.5 41
SmartRF ? CC1100
CRYSTAL CONTROL ............................................................................................................................31 VOLTAGE REGULATOR CONTROL.......................................................................................................31 ACTIVE MODES ..................................................................................................................................31 WAKE ON RADIO (WOR) ...................................................................................................................32 TIMING ...............................................................................................................................................33 RX TERMINATION TIMER ...................................................................................................................33 DATA FIFO ........................................................................................................................................34 FREQUENCY PROGRAMMING ..............................................................................................................35 VCO...................................................................................................................................................35 VCO AND PLL SELF-CALIBRATION ...................................................................................................35 VOLTAGE REGULATORS .....................................................................................................................35 OUTPUT POWER PROGRAMMING ........................................................................................................36 CRYSTAL OSCILLATOR .......................................................................................................................37 ANTENNA INTERFACE.........................................................................................................................38 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS ...........................................................................38 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION ................................................................40 ASYNCHRONOUS OPERATION..............................................................................................................40 SYNCHRONOUS SERIAL OPERATION ....................................................................................................40 CONFIGURATION REGISTERS ..............................................................................................................40 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ..........45 CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOOSE PROGRAMMING IN SLEEP STATE ......59 STATUS REGISTER DETAILS .................................................................................................................60 PACKAGE DESCRIPTION (QLP 20)......................................................................................................63 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 20).....................................................................64 PACKAGE THERMAL PROPERTIES ........................................................................................................64 SOLDERING INFORMATION..................................................................................................................64 TRAY SPECIFICATION ..........................................................................................................................65 CARRIER TAPE AND REEL SPECIFICATION ...........................................................................................65 ORDERING INFORMATION ...................................................................................................................65 GENERAL INFORMATION ....................................................................................................................66 DOCUMENT HISTORY .........................................................................................................................66 PRODUCT STATUS DEFINITIONS .........................................................................................................66 DISCLAIMER .......................................................................................................................................66 TRADEMARKS .....................................................................................................................................66 LIFE SUPPORT POLICY ........................................................................................................................66 ADDRESS INFORMATION .....................................................................................................................68
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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1 Absolute Maximum Ratings
SmartRF ? CC1100
Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Parameter Supply voltage Voltage on any digital pin Voltage on the pins RF_P, RF_N and DCOUPL Input RF level Storage temperature range Solder reflow temperature –50 Min –0.3 –0.3 –0.3 Max 3.6 VDD+0.3, max 3.6 2.0 10 150 265 Units V V V dBm °C °C According to IPC/JEDEC J-STD-020C Condition All supply pins must have the same voltage
Table 1: Absolute Maximum Ratings
2
Operating Conditions
Min -40 1.8 Max 85 3.6 Unit °C V All supply pins must have the same voltage Condition
The operating conditions for CC1100 are listed Table 2 in below.
Parameter Operating temperature Operating supply voltage
Table 2: Operating Conditions
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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3 Electrical Specifications
Min Typ 900 400 90 160 Current consumption 15 Max
SmartRF ? CC1100
Tc = 25°C, VDD = 3.0V if nothing else stated. Measured on Chipcon’s CC1100EM reference design. Parameter Current consumption in power down modes Unit Condition nA nA μA μA μA Voltage regulator to digital part off, register values retained, lowpower RC oscillator running (SLEEP state with WOR enabled) Voltage regulator to digital part off, register values retained (SLEEP state) Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set) Voltage regulator to digital part on, all other modules in power down (XOFF state) Automatic RX polling once each second, using low-power RC oscillator, with 460kHz filter bandwidth and 250kbps data rate, th PLL calibration every 4 wakeup. Average current with signal in channel below carrier sense level. Same as above, but with signal in channel above carrier sense level, 1.9ms RX timeout, and no preamble/sync word found. Automatic RX polling every 15 second, using low-power RC oscillator, with 460kHz filter bandwidth and 250kbps data rate, th PLL calibration every 4 wakeup. Average current with signal in channel below carrier sense level. Same as above, but with signal in channel above carrier sense level, 14ms RX timeout, and no preamble/sync word found. Only voltage regulator to digital part and crystal oscillator running (IDLE state) Only the frequency synthesizer running (after going from IDLE until reaching RX or TX states, and frequency calibration states) Transmit mode, +10dBm output power Transmit mode, 5dBm output power Transmit mode, 0dBm output power Transmit mode, –10dBm output power Receive mode, 2.4kbps, input at sensitivity limit Receive mode, 2.4kbps, input 30dB above sensitivity limit Receive mode, 250kbps, input at sensitivity limit Receive mode, 250kbps, input 30dB above sensitivity limit mA Transmit mode, +10dBm output power Transmit mode, 5dBm output power Transmit mode, 0dBm output power Transmit mode, –10dBm output power Receive mode, 2.4kbps, input at sensitivity limit Receive mode, 2.4kbps, input 30dB above sensitivity limit Receive mode, 250kbps, input at sensitivity limit Receive mode, 250kbps, input 30dB above sensitivity limit
th
34 1.8
μA μA
15 1.9 8.7 Current consumption, 315MHz 26.9 18.3 15.1 13.4 15.1 14.0 16.2 15.1 Current consumption, 433MHz 28.8 19.3 16.1 14.3 15.6 14.5 16.5 15.5
μA mA mA mA
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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Parameter Current consumption, 868/915MHz Min Typ 30.3 19.7 16.6 14.0 15.4 14.2 16.2 15.2 Max mA
SmartRF ? CC1100
Unit Condition Transmit mode, +10dBm output power Transmit mode, 5dBm output power Transmit mode, 0dBm output power Transmit mode, –10dBm output power Receive mode, 2.4kbps, input at sensitivity limit Receive mode, 2.4kbps, input 30dB above sensitivity limit Receive mode, 250kbps, input at sensitivity limit Receive mode, 250kbps, input 30dB above sensitivity limit
Table 3: Electrical Specifications
4
General Characteristics
Min 300 400 800 Typ Max 348 464 928 500 Unit MHz MHz MHz kbps Modulation formats supported: (Shaped) MSK (also known as differential offset QPSK) up to 500kbps 2-FSK up to 500kbps GFSK and OOK/ASK (up to 250kbps) Optional Manchester encoding (halves the data rate). Condition/Note
Parameter Frequency range
Data rate
1.2
Table 4: General Characteristics
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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5 RF Receive Section
Min Typ TBD –110 –100 -88 Max Unit ? dBm dBm dBm
SmartRF ? CC1100
Tc = 25°C, VDD = 3.0V if nothing else stated. Measured on Chipcon’s CC1100EM reference design. Parameter Differential input impedance Receiver sensitivity 315/433/868/915MHz Condition/Note Follow CC1100EM reference design 2-FSK, 1.2kbps, 5.2kHz deviation, 1% packet error rate, 62 bytes packet length, 58kHz digital channel filter bandwidth 2-FSK, 38.4kbps, 20kHz deviation, 1% packet error rate, 62 bytes packet length, 100kHz digital channel filter bandwidth 2-FSK, 250kbps, 127kHz deviation, 1% packet error rate, 62 bytes packet length, 540kHz digital channel filter bandwidth OOK, 250kbps OOK, 1% packet error rate, 62 bytes packet length, 540kHz digital channel filter bandwidth
-88 Saturation Digital channel filter bandwidth Adjacent channel rejection, 868MHz 58 –15 650
dBm dBm kHz
User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0MHz crystal). 2-FSK, 38.4kbps, 20kHz deviation, 1% packet error rate, 62 bytes packet length, 100kHz digital channel filter, 150kHz channel spacing Desired channel 3dB above the sensitivity limit.
23
dB
Alternate channel rejection, 868MHz
33
dB
2-FSK, 38.4kbps, 20kHz deviation, 1% packet error rate, 62 bytes packet length, 100kHz digital channel filter, 150kHz channel spacing Desired channel 3dB above the sensitivity limit.
Image channel rejection, 868MHz
29
dB
2-FSK, 38.4kbps, 20kHz deviation, 1% packet error rate, 62 bytes packet length, 100kHz digital channel filter, 150kHz channel spacing, IF frequency 305kHz Desired channel 3dB above the sensitivity limit.
Blocking at 1MHz offset, 868MHz Blocking at 2MHz offset, 868MHz Blocking at 5MHz offset, 868MHz Blocking at 10MHz offset, 868MHz Spurious emissions
52 54 61 64 –57 –47
dB dB dB dB dBm dBm
Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement. Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement. Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement. Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement. 25MHz – 1GHz Above 1GHz
Table 5: RF Receive Section
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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6 RF Transmit Section
SmartRF ? CC1100
Tc = 25°C, VDD = 3.0V, +10dBm if nothing else stated. Measured on Chipcon’s CC1100EM reference design. Parameter Differential load impedance Output power, highest setting Min Typ TBD 10 Max Unit ? dBm Condition/Note Follow CC1100EM reference design Output power is programmable, and full range is available in all frequency bands. Delivered to a 50? single-ended load via Chipcon reference RF matching network. Output power, lowest setting –30 dBm Output power is programmable, and full range is available in all frequency bands. Delivered to a 50? single-ended load via Chipcon reference RF matching network. Spurious emissions and harmonics, 433/868MHz –36 –54 –47 dBm dBm dBm 25MHz – 1GHz 47-74, 87.5-118, 174-230, 470-862MHz 1800MHz-1900MHz (restricted band in Europe), when the nd operating frequency is below 900MHz (2 harmonic can not fall within this band when used in Europe) Otherwise above 1GHz <200μV/m at 3m below 960MHz. <500μV/m at 3m above 960MHz. 2 , 3 and 4 harmonic when the output power is maximum 6mV/m at 3m. (-19.6dBm EIRP) 5 harmonic 2 harmonic 3 , 4 and 5 harmonic
rd th th nd th nd rd th
–30 Spurious emissions, 315/915MHz -49.2 -41.2 Harmonics 315MHz -20
dBm dBm EIRP dBm EIRP dBc
-41.2 Harmonics 915MHz -20 -41.2
dBm dBc dBm
Table 6: RF Transmit Parameters
7
Crystal Oscillator
Tc = 25°C @ VDD = 3.0 V if nothing else is stated. Parameter Crystal frequency Tolerance Min 26 Typ 26 ±40 Max 27 Unit MHz ppm This is the total tolerance including a) initial tolerance, b) aging and c) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. ESR Start-up time 300 100 ? μs Measured on Chipcon’s CC1100EM reference design. This parameter is to a large degree crystal dependent. Condition/Note
Table 7: Crystal Oscillator Parameters
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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8 Low Power RC Oscillator
SmartRF ? CC1100
Typical performance is for Tc = 25°C @ VDD = 3.0 V if nothing else is stated. The values in the table are simulated results and will be updated in later versions of the data sheet. Parameter Calibrated frequency Frequency accuracy after calibration Temperature coefficient Supply voltage coefficient Initial calibration time +0.4 +3 2 Min 34.6 Typ 34.7 Max 36 ±0.2 Unit kHz % % / °C %/V ms Frequency drift when temperature changes after calibration Frequency drift when supply voltage changes after calibration When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. Programmable, dependent on XTAL frequency Condition/Note Calibrated RC Oscillator frequency is XTAL frequency divided by 750
Wake-up period
58e-6
59650
Seconds
Table 8: RC Oscillator parameters
9
Frequency Synthesizer Characteristics
Tc = 25°C @ VDD = 3.0 V if nothing else is stated. Measured on Chipcon’s CC1100EM reference design. Parameter Programmed frequency resolution Synthesizer frequency tolerance PLL turn-on / hop time Min 397 Typ FXOSC/ 16 2 ±40 Max 412 Unit Hz Condition/Note 26MHz-27MHz crystal. The resolution (in Hz) is equal for all frequency bands. ppm Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running. Settling time for the 1xIF frequency step from RX to TX, and vice versa. Calibration can be initiated manually, or automatically before entering or after leaving RX/TX. Min/typ/max time is for 27/26/26MHz crystal frequency.
80
μs
PLL RX/TX and TX/RX settling time PLL calibration time 0.69 18739 0.72
10
μs XOSC cycles
0.72
ms
Table 9: Frequency Synthesizer Parameters
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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10 Analog temperature sensor
SmartRF ? CC1100
The characteristics of the analog temperature sensor are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.
The values in the table are simulated results and will be updated in later versions of the data sheet. Minimum / maximum values are valid over entire supply voltage range. Typical values are for 3.0V supply voltage. Parameter Output voltage at –40°C Output voltage at 0°C Output voltage at +40°C Output voltage at +80°C Temperature coefficient Absolute error in calculated temperature Error in calculated temperature, calibrated Settling time after enabling Current consumption increase when enabled Min 0.638 0.733 0.828 0.924 2.35 –14 –2 TBD 0.3 Typ 0.648 0.743 0.840 0.939 2.45 –8 Max 0.706 0.793 0.891 0.992 2.46 +14 +2 Unit V V V V mV/°C °C °C μs mA Fitted from –20°C to +80°C From –20°C to +80°C when assuming best fit for absolute accuracy: 0.763V at 0°C and 2.44mV / °C From –20°C to +80°C when using 2.44mV / °C, after 1-point calibration at room temperature Condition/Note
Table 10: Analog Temperature Sensor Parameters
11 DC Characteristics
The DC Characteristics of CC1100 are listed in Table 11 below.
Tc = 25°C if nothing else stated. Digital Inputs/Outputs Logic "0" input voltage Logic "1" input voltage Logic "0" output voltage Logic "1" output voltage Logic "0" input current Logic "1" input current Min 0 VDD-0.7 0 VDD-0.3 N/A N/A Max 0.7 VDD 0.5 VDD –1 1 Unit V V V V μA μA For up to 4mA output current For up to 4mA output current Input equals 0V Input equals VDD Condition
Table 11: DC Characteristics
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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12 Power On Reset
SmartRF ? CC1100
When the power supply complies with the requirements in Table 12 below, proper Power-OnReset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. It is recommended to transmit an SRES strobe after turning power on in any case. See section 27.1 on page 31 for a description of the recommended start up sequence after turning power on.
Parameter Power-up ramp-up time. Power off time 1 Min Typ Max 5 Unit ms ms Condition/Note From 0V until reaching 1.8V Minimum time between power-on and power-off.
Table 12: Power-on Reset Requirements
13 Pin Configuration
DGUARD
RBIAS
GND
20 19 18 17 16 SCLK 1 SO (GDO1) 2 GDO2 3 DVDD 4 DCOUPL 5 6 GDO0 (ATEST) 7 CSn 8 XOSC_Q1 9 10 AVDD XOSC_Q2 15 AVDD 14 AVDD 13 RF_N 12 RF_P 11 AVDD GND Exposed die attach pad
Figure 1: Pinout top view Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
GND
SI
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Pin # 1 2 Pin name Pin type Digital Input Digital Output
SmartRF ? CC1100
Description Serial configuration interface, clock input Serial configuration interface, data output. Optional general output pin when CSn is high
SCLK SO (GDO1) GDO2
3
Digital Output
Digital output pin for general use: ? Test signals ? FIFO status signals ? Clear Channel Indicator ? Clock output, down-divided from XOSC ? Serial output RX data
4 5
DVDD DCOUPL
Power (Digital) Power (Digital)
1.8V-3.6V digital power supply for digital I/O’s and for the digital core voltage regulator 1.6V-2.0V digital power supply output for decoupling. NOTE: This pin is intended for use with the CC1100 only. It can not be used to provide supply voltage to other devices.
6
GDO0 (ATEST)
Digital I/O
Digital output pin for general use: ? Test signals ? FIFO status signals ? Clear Channel Indicator ? Clock output, down-divided from XOSC ? Serial output RX data ? Serial input TX data Also used as analog test I/O for prototype/production testing
7 8 9 10 11 12
CSn XOSC_Q1 AVDD XOSC_Q2 AVDD RF_P RF_N AVDD AVDD GND RBIAS DGUARD GND SI
Digital Input Analog I/O Power (Analog) Analog I/O Power (Analog) RF I/O
Serial configuration interface, chip select Crystal oscillator pin 1, or external clock input 1.8V-3.6V analog power supply connection Crystal oscillator pin 2 1.8V-3.6V analog power supply connection Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode
13
RF I/O
Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode
14 15 16 17 18 19 20
Power (Analog) Power (Analog) Ground (Analog) Analog I/O Power (Digital) Ground (Digital) Digital Input
1.8V-3.6V analog power supply connection 1.8V-3.6V analog power supply connection Analog ground connection External bias resistor for reference current Power supply connection for digital noise isolation Ground connection for digital noise isolation Serial configuration interface, data input
Table 13: Pinout overview
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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14 Circuit Description
SmartRF ? CC1100
RADIO CONTROL DEMODULATOR
RXFIFO
ADC
LNA
ADC
RF_P RF_N
DIGITAL INTERFACE TO MCU
FEC / INTERLEAVER
PACKET HANDLER
SCLK SO (GDO1) SI CSn GDO0 (ATEST) GDO2
0 90
FREQ SYNTH
RC OSC
BIAS
XOSC
RBIAS
XOSC_Q1
XOSC_Q2
Figure 2: CC1100 Simplified Block Diagram A simplified block diagram of CC1100 is shown in Figure 2. frequency synthesizer includes a completely on-chip LC VCO and a 90 degree phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode. A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband includes support for channel configuration, packet handling and data buffering.
CC1100 features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization is performed digitally.
The transmitter part of CC1100 is based on direct synthesis of the RF frequency. The
15 Application Circuit
Only a few external components are required for using the CC1100. The recommended application circuit is shown in Figure 3. The external components are described in Table 14, and typical values are given in Table 15. Bias resistor The bias resistor R171 is used to set an accurate bias current. Balun and RF matching C131, C121, L121 and L131 form a balun that converts the differential RF port on CC1100 to a single-ended RF signal (C124 is also needed for DC blocking). Together with an appropriate LC network, the balun components also transform the impedance to match a 50? antenna (or cable). Component values for the RF balun and LC network are easily found using the SmartRF? Studio software. Suggested values for 315MHz, 433MHz and 868/915MHz are listed in Table 15.
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
TXFIFO
PA
MODULATOR
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Crystal The crystal oscillator uses an external crystal with two loading capacitors (C81 and C101). See section 33 on page 37 for details. Additional filtering Additional external components (e.g. an RF SAW filter) may be used in order to improve the performance in specific applications.
SmartRF ? CC1100
Power supply decoupling The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. Chipcon provides a reference design that should be followed closely.
Component C51 C81/C101 C121/C131 C122/C123 C124 C125 L121/L131 L122/L123 R171 XTAL
Description 100nF decoupling capacitor for on-chip voltage regulator to digital part Crystal loading capacitors, see section 33 on page 37 for details RF balun/matching capacitors RF LC filter/matching capacitors RF balun DC blocking capacitor RF LC filter DC blocking capacitor (only needed if there is a DC path in the antenna) RF balun/matching inductors (inexpensive multi-layer type) RF LC filter/matching filter inductor (inexpensive multi-layer type) 56k? resistor for internal bias current reference 26MHz-27MHz crystal, see section 33 on page 37 for details
Table 14: Overview of external components (excluding supply decoupling capacitors)
1.8V-3.6V power supply
SI
SI 20 RBIAS 17 GND 19 DGUARD 18 GND 16
R171
SCLK
1 SCLK 2 SO (GDO1) 3 GDO2 4 DVDD
AVDD 15 AVDD 14 RF_N 13 RF_P 12 10 XOSC_Q2
Antenna (50 Ohm) C131 L131 C121 L121 C124 L122 L123 C122 C125
Digital Inteface
SO (GDO1) GDO2 (optional)
CC1100
DIE ATTACH PAD: 8 XOSC_Q1 6 GDO0 9 AVDD 7 CSn
5 DCOUPL
AVDD 11
C123
C51
GDO0 (optional) CSn
XTAL C81 C101
Figure 3: Typical application and evaluation circuit (excluding supply decoupling capacitors)
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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Component Value at 315MHz
SmartRF ? CC1100
Value at 433MHz Value at 868/915MHz 100nF±10%, 0402 X5R 27pF±5%, 0402 NP0 27pF±5%, 0402 NP0
C51 C81 C101 C121 C122 C123 C124 C125 or C126 C131 L121 L122 L123 L131 R171 XTAL 6.8pF±0.5pF, 0402 NP0 12pF±5%, 0402 NP0 6.8pF±0.5pF, 0402 NP0 220pF±5%, 0402 NP0 220pF±5%, 0402 NP0 6.8pF±0.5pF, 0402 NP0 33nH±5%, 0402 monolithic 18nH±5%, 0402 monolithic 33nH±5%, 0402 monolithic 33nH±5%, 0402 monolithic
3.9pF±0.25pF, 0402 NP0 8.2pF±0.5pF, 0402 NP0 5.6pF±0.5pF, 0402 NP0 220pF±5%, 0402 NP0 220pF±5%, 0402 NP0 3.9pF±0.25pF, 0402 NP0 27nH±5%, 0402 monolithic 22nH±5%, 0402 monolithic 27nH±5%, 0402 monolithic 27nH±5%, 0402 monolithic 56k?±1%, 0402 26.0MHz surface mount crystal
2.2pF±0.25pF, 0402 NP0 3.9pF±0.25pF, 0402 NP0 3.3pF±0.25pF, 0402 NP0 100pF±5%, 0402 NP0 100pF±5%, 0402 NP0 2.2pF±0.25pF, 0402 NP0 12nH±5%, 0402 monolithic 5.6nH±0.3nH, 0402 monolithic 12nH±5%, 0402 monolithic 12nH±5%, 0402 monolithic
Table 15: Bill Of Materials for the application circuit (subject to changes)
16 Configuration Overview
CC1100 can be configured to achieve optimum
performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed: ? ? ? ? ? ? ? ? ? Power-down / power up mode Crystal oscillator power-up / power-down Receive / transmit mode RF channel selection Data rate Modulation format RX channel filter bandwidth RF output power Data buffering with separate 64-byte receive and transmit FIFOs ? ? ? ? Packet radio hardware support Forward Error Correction with interleaving Data Whitening Wake-On-Radio (WOR)
Details of each configuration register can be found in section 37, starting on page 40. Figure 4 shows a simplified state diagram that explains the main CC1100 states, together with typical usage and current consumption. For detailed information on controlling the CC1100 state machine, and a complete state diagram, see section 27, starting on page 30.
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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SmartRF ? CC1100
Sleep
SIDLE SPWD or wake-on-radio (WOR)
Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.9mA.
Lowest power mode. Most register values are retained. Current consumption typ 400nA, or typ 900nA when wake-on-radio (WOR) is enabled.
CSn=0
IDLE
SXOFF
SCAL Used for calibrating frequency synthesizer upfront (entering CSn=0 Manual freq. receive or transmit mode can synth. calibration SRX or STX or SFSTXON or wake-on-radio (WOR) then be done quicker). Transitional state. Typ. current consumption: 8.7mA.
Crystal oscillator off
All register values are retained. Typ. current consumption; 0.16mA.
Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe.Typ. current consumption: 8.7mA.
SFSTXON
Frequency synthesizer startup, optional calibration, settling
Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional state. Typ. current consumption: 8.7mA.
Frequency synthesizer on
STX SRX or wake-on-radio (WOR) STX TXOFF_MODE=01 SFSTXON or RXOFF_MODE=01
Typ. current consumption: 14mA at -10dBm output, 16mA at 0dBm output, 19mA at +5dBm output, 29mA at +10dBm output.
Transmit mode
STX or RXOFF_MODE=10
Receive mode
SRX or TXOFF_MODE=11
Typ. current consumption: from 14.2mA (strong input signal) to 15.4mA (weak input signal) at 2.4kbps.
TXOFF_MODE=00
RXOFF_MODE=00
In FIFO-based modes, transmission is turned off and this state entered if the TX FIFO becomes empty in the middle of a packet. Typ. current consumption: 1.9mA.
Optional transitional state. Typ. current consumption: 8.7mA. TX FIFO underflow Optional freq. synth. calibration RX FIFO overflow
In FIFO-based modes, reception is turned off and this state entered if the RX FIFO overflows. Typ. current consumption: 1.9mA.
SFTX
SFRX
IDLE
Figure 4: Simplified state diagram, with typical usage and current consumption
17 Configuration Software
CC1100 can be configured using the SmartRF?
Studio software, available for download from https://www.wendangku.net/doc/08807879.html,. The SmartRF? Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF? Studio user interface for CC1100 is shown in Figure 5.
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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SmartRF ? CC1100
Figure 5: SmartRF? Studio user interface
18 4-wire Serial Configuration and Data Interface
CC1100 is configured via a simple 4-wire SPIcompatible interface (SI, SO, SCLK and CSn) where CC1100 is the slave. This interface is also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first. All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address. During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes high during the access, the transfer will be cancelled. When CSn goes low, the MCU must wait until the CC1100 SO pin goes low before starting to transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low. 18.1 Chip Status Byte When the header byte is sent on the SPI interface, the chip status byte is sent by the CC1100 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable. Bit 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. When idle the XOSC and power to the digital core is on, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The RX state will be active when the chip is in receive mode. Likewise, TX is active when the chip is transmitting.
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations, the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations, the FIFO_BYTES_AVAILABLE field contains the number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are available/free. 18.2 Register Access The configuration registers on the CC1100 are located on SPI addresses from 0x00 to 0x2F. Table 29 on page 42 lists all configuration registers. The detailed description of each register is found in Section 37.1, starting on page 45. All configuration registers can be both written to and read. The read/write bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a data byte to be written is transmitted on the SI pin. Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high. For register addresses in the range 0x300x3D, the “burst” bit is used to select between status registers and command strobes (see below). The status registers can only be read. Burst read is not available for status registers, so they must be read one at a time. 18.3 Command Strobes Command Strobes may be viewed as single byte instructions to CC1100. By addressing a Command Strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 14 command strobes are listed in Table 28 on page 41. The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to 0) and the six address bits (in the range 0x30
SmartRF ? CC1100
through 0x3D) are written. A command strobe may be followed by any other SPI access without pulling CSn high. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high. 18.4 FIFO Access The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F addresses. When the read/write bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the read/write bit is one. The TX FIFO is write-only, while the RX FIFO is read-only. The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte. After the data byte a new address is expected; hence, CSn can remain low. The burst access method expects one address byte and then consecutive data bytes until terminating the access by setting CSn high. The following header bytes access the FIFOs: ? ? ? ? 0x3F: Single byte access to TX FIFO 0x7F: Burst access to TX FIFO 0xBF: Single byte access to RX FIFO 0xFF: Burst access to RX FIFO
When writing to the TX FIFO, the status byte (see Section 18.1) is output for each new data byte on SO, as shown in Figure 6. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received concurrently on the SO pin will indicate that one byte is free in the TX FIFO. The transmit FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the receive FIFO. Both FIFOs are cleared when going to the SLEEP state. 18.5 PATABLE Access The 0x3E address is used to access the PATABLE, which is used for selecting PA
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SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for reduced bandwidth. See section 32 on page 36 for output power programming details. The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power values (selected by the 3-bit value FREND0.PA_POWER). The table is written to and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CSn is high. When the
SmartRF ? CC1100
highest value is reached the counter restarts at zero. The access to the PATABLE is either single byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write bit controls whether the access is a write access (R/W=0) or a read access (R/W=1). If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before the read access in order to set the index counter back to zero. Note that the content of the PATABLE is lost when entering the SLEEP state, except for the first byte (index 0).
tsp
tch
tcl
tsd
thd
tns
SCLK: CSn: Write to register: SI SO
X Hi-Z
0
S7
A6 S6
A5 S5
A4 S4
A3 S3
A2 S2
A1 S1
A0 S0
X
D 7
W
D 6
W
D 5
W
D 4
W
D 3
W
D 2
W
D 1
W
D 0
W
X S7 Hi-Z
S7
S6
S5
S4
S3
S2
S1
S0
Read from register: SI
X
1
S7
A6 S6
A5 S5
A4 S4
A3 S3
A2 S2
A1 S1
A0 S0 D 7
R
X D 6
R
SO Hi-Z
D 5
R
D 4
R
D 3
R
D 2
R
D 1
R
D 0
R
Hi-Z
Figure 6: Configuration registers write and read operations
Parameter FSCLK tsp,pd tsp tch tcl trise tfall tsd thd tns Description SCLK frequency Min 0 TBDμs TBDns 50ns 50ns TBDns TBDns TBDns Max 10MHz TBDns TBDns -
CSn low to positive edge on SCLK, in power-down mode CSn low to positive edge on SCLK, in active mode
Clock high Clock low Clock rise time Clock rise time Setup data to positive edge on SCLK Hold data after positive edge on SCLK Negative edge on SCLK to CSn high.
Table 16: SPI interface timing requirements
Chipcon AS
SmartRF? CC1100 Preliminary Data Sheet (rev. 1.0) 2005-04-25
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