SIHFB20N50K中文资料
Power MOSFET
IRFB20N50K, SiHFB20N50K
Vishay Siliconix
FEATURES
?Low G ate Charge Q g Results in Simple Drive Requirement
?Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
?Fully Characterized Capacitance and Avalanche Voltage and Current ?Low
R Notes
a.Repetitive rating; pulse width limited by maximum junction temperature.
b.Starting T J = 25 °C, L = 1.6 mH, R G = 25 Ω, I AS = 20 A.
c.I SD ≤ 20 A, dI/dt ≤ 350 A/μs, V DD ≤ V DS , T J ≤ 150 °C.
d. 1.6 mm from cas
e.
PRODUCT SUMMARY
V DS (V)500
R DS(on) (Ω)V GS = 10 V
0.21
Q g (Max.) (nC)110Q gs (nC)33Q gd (nC)54Configuration
Single
G
D
S
ABSOLUTE MAXIMUM RATINGS T C = 25 °C, unless otherwise noted
ARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS
500V
Gate-Source Voltage V GS ± 30 Continuous Drain Current V GS at 10 V
T C = 25 °C I D
20A T C = 100 °C
12Pulsed Drain Current a I DM 80
Linear Derating Factor
2.2W/°C Single Pulse Avalanche Energy b E AS 330mJ Repetitive Avalanche Current a I AR 20 A Repetitive Avalanche Energy a E AR 28mJ Maximum Power Dissipation T C = 25 °C
P D 280W
Peak Diode Recovery dV/dt c
dV/dt 6.9
V/ns Operating Junction and Storage Temperature Range T J , T stg
- 55 to + 150
°C Soldering Recommendations (Peak Temperature)for 10 s 300d Mounting Torque
6-32 or M3 screw
10
N * Pb containing terminations are not RoHS compliant, exemptions may apply
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IRFB20N50K, SiHFB20N50K
Vishay Siliconix
Notes
a.Repetitive rating; pulse width limited by maximum junction temperature.
b.Pulse width ≤ 400 μs; duty cycle ≤ 2 %.
THERMAL RESISTANCE RATINGS
ARAMETER SYMBOL TY
.MAX.UNIT Maximum Junction-to-Ambient R thJA -58°C/W
Case-to-Sink, Flat, Greased Surface R thCS 0.50-Maximum Junction-to-Case (Drain)
R thJC
-
0.45
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IRFB20N50K, SiHFB20N50K
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 2 - Typical Output Characteristics
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IRFB20N50K, SiHFB20N50K Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area
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IRFB20N50K, SiHFB20N50K
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
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IRFB20N50K, SiHFB20N50K
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
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IRFB20N50K, SiHFB20N50K
Vishay Siliconix
Fig. 14 - For N-Channel
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