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DTC34LM85A

DTC34LM85A ( Rev. 0.3)

REVISED JAN. 2003

+3.3V LVDS 24Bit Flat Panel Display (FPD) Transmitter - 85MHz

General Description

The DTC34LM85A transmitter converts 28 bits of CMOS/TTL data into four LVDS(Low Voltage Differential Signaling) data streams. A CLKIN signal is phase-locked and transmitted in

parallel with the data streams over a fifth LVDS link. 24bits of graphic data and 3 bits of timing and 1 control data are transmitted at a rate of 595 Mbps per LVDS data channel at a transmit clock frequency of 85MHz. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. The R_FB pin

selects either rising or falling edge trigger of CLKIN. A

Rising/Falling edge strobe transmitter will interoperate with a Rising/Falling edge strobe receiver (DTC34LF/R86) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Features

Wide frequency range : 20 to 85 MHz shift clock support Narrow bus (10 lines) reduces cable size and cost Single 3.3V supply Power-Down Mode

Supports VGA, SVGA, XGA and SXGA Supports Spread Spectrum Clock Generator On Chip Input Jitter Filtering

Up to 297.5 Megabytes/sec bandwidth Reduced Swing LVDS Support for low EMI ( 200mV or 350mV Swing LVDS Selectable) PLL requires no external components Low profile 56-lead TSSOP package Compatible with TIA/EIA-644 LVDS standard

Compatible with National DS90C385

Thine THC63LVDM83R

LVDS Product

PIN OUT PACKAGE

56 Lead Molded Thin Shrink Small Outline Package, JEDEC

Unit : millimeters

Vcc=3.0 ~ 3.6V, Ta=-10 ~ +70°C

CMOS/TTL DC SPECIFICATIONS

Symbol Parameter Conditions Min Typ Max Units

V IH High Level Input Voltage 2.0 Vcc V V IL

Low Level Input Voltage

GND 0.8 V I IN Input Current 0V ≤ V IN ≤ Vcc ±10 uA I PD

Pull Down Current

R_FB pin, VIH=Vcc

Electrical Characteristics RS TX5TX6TX7

GND TX8TX9TX10VCC TX11TX12TX13GND TX14TX15TX16R_FB TX17TX18TX19GND TX20TX21TX22TX23VCC TX24TX25TX4TX3TX2GND TX1TX0TX27

LVDS GND TXOUT0-TXOUT0+TXOUT1-TXOUT1+LVDS VCC LVDS GND TXOUT2-TXOUT2+TCLK-TCLK+

TXOUT3-TXOUT3+LVDS GND PLL GND PLL VCC PLL GND /PDN CLKIN TX26GND

LVDS TRANSMITTER DC SPECIFICATIONS

Symbol Parameter Conditions

Min

Typ

Max

Units

V OD Differential Output Voltage,

Normal RS=VCC

(Small RS=GND)

250

(100)

350

(200)

450

(300)

?V OD Change in V OD between

Complimentary Output States

V OC Common

Mode

Voltage 1.125 1.25 1.375 V

?V OC Change in V OC between

Complimentary Output States

RL=100?

I OZ Output TRI-STATE Current

/PDN=0V,

Vout=0 to Vcc

±10

TRANSMITTER SUPPLY CURRENT

Symbol Parameter Conditions Typ

Max

Units

ICC TG Transmitter Supply Current

(16 Grayscale)

RL=100?, CL = 10pF, f = 85MHz

RS=VCC ( RS=GND)

(31)

ICC TW Transmitter Supply Current

(Worst Case)

RL=100?, CL = 10pF, f = 85MHz

RS=VCC ( RS=GND)

(34)

ICC TP Transmitter Supply Current

(Power Down)

/PDN

0V 10

* All typical values are Vcc = 3.3V, Ta = 25°C

Absolute Maximum Ratings (Note1)

Supply Voltage (Vcc) -0.3 to +4.0V

CMOS/TTL Input Voltage -0.3V to (Vcc + 0.3V)

CMOS/TTL Output Voltage -0.3V to (Vcc + 0.3V) LVDS Driver Output Voltage -0.3V to (Vcc + 0.3V) Output Short Circuit Duration Continuous

Junction Temperature +150°C Storage Temperature Range -65°C to 150°C Lead Temperature (Soldering, 4 sec.) +260°C Maximum Power Dissipation @25°C 1.4W (Note 1)

"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation

Transmitter Switching Characteristics

Vcc=3.0 ~ 3.6V, Ta=-10 ~ +70°C, T=1/f

Symbol Parameter Min

Typ

Max

Units

t TCIT CLKIN Transition Time 5.0

t TCP CLKIN

Period 11.76 T 50 nS t TCH CLKIN High Time 0.35T 0.5T 0.65T nS

t TCL CLKIN

Low

Time 0.35T 0.5T 0.65T

nS t TCD CLKIN to TCLK+/- Delay 2T/7 + 2.3 nS

t TS TTL Data Setup to CLKIN 2.5 nS

t TH TTL Data Hold from CLKIN 2.5 nS

t LVT LVDS

Transition

Time 0.6 1.5 nS t TDP1Transmitter Output Data Position 0 (85MHz)-0.2 0 0. 2 nS

t TDP0Transmitter Output Data Position 1 (85MHz)T/7-0. 2 T/7 T/7+0. 2 nS

t TDP6Transmitter Output Data Position 2 (85MHz)2T/7-0. 2 2T/7 2T/7+0. 2 nS

t TDP5Transmitter Output Data Position 3 (85MHz)3T/7-0. 2 3T/7 3T/7+0. 2 nS

t TDP4Transmitter Output Data Position 4 (85MHz)4T/7-0. 2 4T/7 4T/7+0. 2 nS

t TDP3Transmitter Output Data Position 5 (85MHz)5T/7-0. 2 5T/7 5T/7+0. 2 nS

t TDP2Transmitter Output Data Position 6 (85MHz)6T/7-0. 2 6T/7 6T/7+0. 2 nS

t TPLLS Transmitter Phase Lock Loop Set - - 10 mS

AC Timing Diagrams

FIGURE 1. Test Pattern “Worst Case Pattern”

CLKIN

ODD TX

EVEN TX

AC Timing Diagrams(Continued)

FIGURE 2. Test Pattern “16 Grayscale Test Pattern”

FIGURE 3. TTL Input

FIGURE 4. LVDS Output

Vdiff= (TXOUT+) – (TXOUT– )

Vdiff

100ohm

LVDS OUTPUT LOAD

AC Timing Diagrams(Continued)

FIGURE 5. Phase Lock Loop Set Time

/PDN

3.6V

VCC

FIGURE 6. Transmitter Device Operation

Note : 1)Vdiff = (TXOUT+) - (TXOUT-), .... (TCLK+) – (TCLK-)

FIGURE 7. Parallel TTL Data Inputs Mapped to LVDS Outputs – DTC34LM85A

FIGURE 8. Setup/Hold and High/Low Times

Note : 1) CLKIN : for DTC34LM85A(R_FB=GND), denoted as solid line

for DTC34LM85A(R_FB=VCC), denoted as dotted line

Note : 1) Vdiff = (TXOUT+) - (TXOUT-), .... (TCLK+) - (TCLK-)

CLKIN

TCLK+/-TXOUT0(Single Ended)

TCLK (Differential)TXOUT1(Single Ended)TXOUT2(Single Ended)TXOUT3(Single Ended)

FIGURE 10. Package Pin Description

IMPORTANT NOTICE :

-The contents of this data sheet are subject to change without prior notice.

DOESTEK Co., Ltd. ( www.doestek.co.kr )

7F TechnoComplex Korea Univ., Anam-Dong5-Ga, Songbuk-Gu, SEOUL,KOREA Tel) 82-2-926-9464