EDI9F81025C100BPC中文资料
EDI9F81025C
2x512Kx8 SRAM Module
Features
2x512Kx8 bit CMOS Static Random Access Memory
?Access Times: 70, 85, and 100ns ?Common Address and Data Pins
?Data Retention Function (EDI9F81025LP)?TTL Compatible Inputs and Outputs ?Fully Static, No Clocks 36 Lead SOIC Module, No. 198Single +5V (±10%) Supply Operation
2x512Kx8 Static RAM CMOS, Module
The EDI9F81025C is an 8 megabit CMOS Static RAM based on two 512Kx8 Static RAMs mounted on a multi-layered epoxy laminate (FR4) substrate.
The EDI9F81025C is organized as two separate banks of 512Kx8Random Access Memory, with common address and data pins to minimize module size. It is offered with access times of 70, 85, and 100ns.
It is also available as EDI9F81025LP, which features Low Power and Battery Back-up Data Retention.
All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous, the EDI9F81025C requires no clocks or refreshing for operation.
Pin Configurations and Block Diagram
A?-A18Address Inputs E?-E1Chip Enable W Write Enable G
Output Enable
DQ?-DQ7Common Data Input/Output VCC Power (+5V ±10%)VSS Ground
NC
No Connection
Pin Names
NC NC A18A16A14A12A7A6A5A4A3A2A1A?DQ?DQ1DQ2VSS
3635343332 31 30 2928 27 26 25 24 23 22 21 2019
1 2 345 678 910 1112 13 14 15 161718
VCC NC A15A17W A13A8A9A11G A10E1E?DQ7DQ6DQ5DQ4DQ3
A?-A18
W G E?
E1
DQ?-DQ7
512Kx8
512Kx8
Electronic Designs Incorporated
? One Research Drive ? Westborough, MA 01581USA ? 508-366-5151 ? FAX 508-836-4850 ?Electronic Designs Europe Ltd. ? Shelley House, The Avenue ? Lightwater, Surrey GU18 5RF
United Kingdom ? 01276 472637 ? FAX: 01276 473748
EDI9F81025C
Voltage on any pin relative to VSS -0.5V to 7.0V Operating Temperature TA (Ambient)
Commercial 0°C to +70°C Industrial
-40°C to +85°C Storage Temperature -65°C to +150°C
Power Dissipation 2 Watts Output Current.
20 mA
Parameter
Sym Conditions
Min Typ*Max Units Operating Power ICC1W, II/O = 0mA, E? or E1= VIL, Min Cycle --6085mA Supply Current
(Operating Current per Bank of 512K bits)
Standby (TTL) Power ICC2 E ≥ VIH, VIN ≤ VIL
--
1
2mA Supply Current VIN ≥ VIH Full Standby Power ICC3 E ≥ VCC-0.2V C 1mA Supply Current (CMOS)VIN ≥ VCC-0.2V or LP 10
100μA VIN ≤ 0.2V Input Leakage Current ILI VIN = 0V to VCC -1010μA Output Leakage Current ILO V I/O = 0V to VCC -1010μA Output High Voltage VOH IOH =-1.0mA 2.4----V Output Low Voltage
VOL IOL = 2.1mA
--
--
0.4
V
(f=1.0MHz, VIN=VCC or VSS)
Parameter Sym Max Unit Address Lines CI 30pF Data Lines
CD/Q 30pF Chip Enable Line CC 20pF Write and
Output Enable Lines
CW
30
pF
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Sym Min Typ Max Units Supply Voltage VCC 4.5 5.0 5.5V Supply Voltage VSS 000V Input High Voltage VIH 2.2-- 6.0V Input Low Voltage VIL
-0.3
--0.8V
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns Input and Output Timing Levels 1.5V
Output Load
1TTL, CL =100pF
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
*Typical: TA = 25°C, VCC = 5.0V
These parameters are sampled, not 100% tested.
EDI9F81025C
2x512Kx8 SRAM Module
Symbol 70ns 85ns 100ns Parameter
JEDEC Alt.Min Max Min
Max Min
Max Units E
G
Q
A
A
Q
Read Cycle Time TAVAV TRC 70
85
100
ns Address Access Time TAVQV TAA 7085100ns Chip Enable Access Time
TELQV TACS 7085100ns Chip Enable to Output in Low Z (1)TELQX TCLZ 5
5
5
ns Chip Disable to Output in High Z (1)TEHQZ TCHZ 303540ns Output Hold from Address Change TAVQX TOH 5
5
5
ns Output Enable to Output Valid
TGLQV TOE 404550ns Output Enable to Output in Low Z (1)TGLQX TOLZ 5
5
5
ns Output Disable to Output in High Z(1)
TGHQZ
TOHZ
30
35
40
ns
Note 1: Parameter guaranteed, but not tested.
EDI9F81025C
Note 1: Parameter guaranteed, but not tested.
Symbol 70ns 85ns 100ns Parameter JEDEC Alt.Min Max Min Max Min Max Units Write Cycle Time
TAVAV TWC 7085100ns Chip Enable to End of Write TELWH TCW 657080ns TELEH TCW 657080ns Address Setup Time TAVWL TAS 000ns TAVEL TAS 000ns Address Valid to End of Write TAVWH TAW 657080ns TAVEH TAW 657080ns Write Pulse Width TWLWH TWP 657080ns TWLEH TWP 657080ns Write Recovery Time TWHAX TWR 555ns TEHAX TWR 555ns Data Hold Time
TWHDX TDH 000ns TEHDX TDH 000ns Write to Output in High Z (1)TWLQZ TWHZ 030035040ns Data to Write Time
TDVWH TDW 303540ns TDVEH TDW 30
35
40
ns
Output Active from End of Write (1)
TWHQX TWLZ
A E
W
D
Q
EDI9F81025C
2x512Kx8 SRAM Module
A
E
D Q
E VCC
Characteristic Sym Test Conditions VDD
Min Typ Max Unit 70°C
85°C Data Retention Voltage VDD VDD= 0.2V 2-- ---- V Data Retention Quiescent Current
ICCDR
E ≥ VDD -0.2V 2V --10 60100 μA VIN ≥VDD -0.2V 3V --20
90150 μA Chip Disable to Data Retention Time(1)TCDR or VIN ≤0.2V
0 ---- ns Operation Recovery Time (1)TR
TAVAV*
---- ns
*Read Cycle Time
Note 1: Parameter guaranteed, but not tested.
LP Version Only
Standard Power Low Power Speed Package with Data Retention
(ns)No.EDI9F81025C70BPC EDI9F81025LP70BPC 70198EDI9F81025C85BPC EDI9F81025LP85BPC 85198EDI9F81025C100BPC
EDI9F81025LP100BPC
100
198
Package No. 198
36 Lead SOIC Package
Electronic Designs Incorporated
Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I,eg. EDI8F9F81025C70BPC becomes EDI9F81025C70BPI.