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XC2C256-6CP132C_IcpdfCom_945778

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Features

Optimized for 1.8V systems

-As fast as 5.7 ns pin-to-pin delays -As low as 13 μA quiescent current ?

Industry’s best 0.18 micron CMOS CPLD

-Optimized architecture for effective logic synthesis.

Refer to the CoolRunner?-II family data sheet for architecture description.

-Multi-voltage I/O operation — 1.5V to 3.3V ?

Available in multiple package options -100-pin VQFP with 80 user I/O -144-pin TQFP with 118 user I/O

-132-ball CP (0.5mm) BGA with 106 user I/O -208-pin PQFP with 173 user I/O

-256-ball FT (1.0mm) BGA with 184 user I/O -Pb-free available for all packages ?

Advanced system features

-Fastest in system programming

· 1.8V ISP using IEEE 1532 (JTAG) interface -IEEE1149.1 JTAG Boundary Scan Test -Optional Schmitt-trigger input (per pin)-Unsurpassed low power management

·DataGATE enable (DGE) signal control -Two separate I/O banks

-RealDigital 100% CMOS product term generation -Flexible clocking modes

·Optional DualEDGE triggered registers ·Clock divider (divide by 2,4,6,8,10,12,14,16)·CoolCLOCK

-Global signal options with macrocell control

·Multiple global clocks with phase selection per

macrocell ·Multiple global output enables ·Global set/reset

-Advanced design security -PLA architecture

·Superior pinout retention ·100% product term routability across function

block

-Open-drain output option for Wired-OR and LED

drive

-Optional bus-hold, 3-state or weak pull-up on

selected I/O pins

-Optional configurable grounds on unused I/Os -Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and

3.3V logic levels ·SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility -Hot pluggable

Description

The CoolRunner?-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reli-ability is improved

This device consists of sixteen Function Blocks inter-con-nected by a low power Advanced Interconnect Matrix (AIM).The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up,open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to stor-ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins.

Clocking is available on a global or Function Block basis.Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.A global set/reset control line is also available to asynchro-nously set or reset selected registers during operation.Additional local clock, synchronous clock-enable, asynchro-nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.

A DualEDGE flip-flop feature is also available on a per mac-rocell basis. This feature allows high performance synchro-nous operation based on lower frequency clocking to help reduce the total power consumption of the device.

Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections.This yields divide by even and odd clock frequencies.The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.

XC2C256 CoolRunner-II CPLD

DS094 (v2.7) March 7, 2005Preliminary Product Specification

DS094 (v2.7) March 7, 2005

By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.Another feature that eases voltage translation is I/O bank-ing. Two I/O banks are available on the CoolRunner-II 256macrocell device that permit easy interfacing to 3.3V, 2.5V,1.8V, and 1.5V devices.

The CoolRunner-II 256 macrocell CPLD is I/O compatible with various I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.

RealDigital Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology.RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance and low power operation.

Supported I/O Standards

The CoolRunner-II 256 macrocell features LVCMOS,LVTTL, SSTL and HSTL I/O implementations. See Table 1

for I/O standard voltages. The LVTTL I/O standard is a gen-eral purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.Both HSTL and SSTL I/O standards make use of a V REF pin for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs Table 1: I/O Standards for XC2C256(1)IOSTANDARD Attribute Output V CCIO Input V CCIO Input V REF Board

Termination Voltage V TT LVTTL 3.3 3.3N/A N/A LVCMOS33 3.3 3.3N/A N/A LVCMOS25 2.5 2.5N/A N/A LVCMOS18 1.8 1.8N/A N/A LVCMOS15 (2) 1.5 1.5N/A N/A HSTL_1 1.5 1.50.750.75SSTL2_1 2.5 2.5 1.25 1.25SSTL3_1

3.3

1.5

(1)For information on Vref, see XAPP399.

(2) LVCMOS15 requires Schmitt-trigger inputs.

CC Table 2: I CC vs Frequency (LVCMOS 1.8V T A = 25°C)(1)

Frequency (MHz)

305070100120150170190220240Typical I CC (mA)

0.021

11.68

19.40

27.01

38.18

45.54

56.32

63.37

70.40

80.90

88.03

Notes:

1.16-bit up/down, resettable binary counter (one counter per function block).

Recommended Operating Conditions

DC Electrical Characteristics (Over Recommended Operating Conditions)

Absolute Maximum Ratings

Symbol Description

Value Units V CC Supply voltage relative to ground –0.5 to 2.0V V CCIO Supply voltage for output drivers –0.5 to 4.0V V JTAG (2)JTAG input voltage limits –0.5 to 4.0V V AUX JTAG input supply voltage –0.5 to 4.0V V IN (1)Input voltage relative to ground –0.5 to 4.0V V TS (1)Voltage applied to 3-state output –0.5 to 4.0V T STG (3)Storage Temperature (ambient)–65 to +150

°C T J

Junction Temperature

+150

°C

Notes:

1.Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,

the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10ns and with the forcing current being limited to 200 mA.2.Valid over commercial temperature range.

3.For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free

packages, see XAPP427.

Symbol Parameter

Min Max Units V CC Supply voltage for internal logic and input buffers

Commercial T A = 0°C to +70°C 1.7 1.9V Industrial T A = –40°C to +85°C

1.7 1.9V V CCIO

Supply voltage for output drivers @ 3.3V operation 3.0 3.6V Supply voltage for output drivers @ 2.5V operation 2.3 2.7V Supply voltage for output drivers @ 1.8V operation 1.7 1.9V Supply voltage for output drivers @ 1.5V operation

1.4 1.6V V AUX

JTAG programming

1.7

3.6

Symbol Parameter

Test Conditions Typical Max.Units I CCSB Standby current Commercial V CC = 1.9V, V CCIO = 3.6V 33150μA I CCSB Standby current Industrial V CC = 1.9V, V CCIO = 3.6V

54300μA I CC Dynamic current f = 1 MHz -410μA f = 50 MHz -27mA C JTAG JTAG input capacitance f = 1 MHz -10pF C CLK Global clock input capacitance f = 1 MHz -12pF C IO I/O capacitance f = 1 MHz

-10pF I IL (2)Input leakage current V IN = 0V or V CCIO to 3.9V -+/–1μA I IH (2)

I/O High-Z leakage

V IN = 0V or V CCIO to 3.9V

-+/–1

μA

Notes:

1.16-bit up/down, resettable binary counter (one counter per function block) tested at V CC = V CCIO = 1.9V

2.See Quality and Reliability section of the CoolRunner-II family data sheet

DS094 (v2.7) March 7, 2005

LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications

LVCMOS 2.5V DC Voltage Specifications

LVCMOS 1.8V DC Voltage Specifications

LVCMOS 1.5V DC Voltage Specifications (1)

Symbol Parameter

Test Conditions

Min.Max.Units V CCIO Input source voltage - 3.0 3.6V V IH High level input voltage -2 3.9V V IL Low level input voltage -–0.30.8V V OH High level output voltage I OH = –8 mA, V CCIO = 3V V CCIO – 0.4V -V I OH = –0.1 mA, V CCIO = 3V V CCIO – 0.2V

-V V OL

Low level output voltage

I OL = 8 mA, V CCIO = 3V -0.4V I OL = 0.1 mA, V CCIO = 3V

-0.2

Symbol Parameter

Test Conditions

Min.Max.Units V CCIO Input source voltage - 2.3 2.7V V IH High level input voltage - 1.7 3.9V V IL Low level input voltage -–0.30.7V V OH High level output voltage I OH = –8 mA, V CCIO = 2.3V V CCIO – 0.4V -V I OH = –0.1 mA, V CCIO = 2.3V V CCIO – 0.2V

-V V OL

Low level output voltage

I OL = 8 mA, V CCIO = 2.3V -0.4V I OL = 0.1 mA, V CCIO = 2.3V

-0.2

Symbol Parameter

Test Conditions

Min.Max.Units V CCIO Input source voltage - 1.7 1.9V V IH High level input voltage -0.65 x V CCIO

3.9V V IL Low level input voltage -–0.30.35 x V CCIO

V V OH High level output voltage I OH = –8 mA, V CCIO = 1.7V V CCIO – 0.45-V I OH = –0.1 mA, V CCIO = 1.7V V CCIO – 0.2

-V V OL

Low level output voltage

I OL = 8 mA, V CCIO = 1.7V -0.45V I OL = 0.1 mA, V CCIO = 1.7V

-0.2

Symbol Parameter

Test Conditions

Min.Max.Units V CCIO Input source voltage

- 1.4 1.6V V T+Input hysteresis threshold voltage -0.5 x V CCIO 0.8 x V CCIO

V V T- -0.2 x V CCIO 0.5 x V CCIO V

V OH

High level output voltage

I OH = –8 mA, V CCIO = 1.4V V CCIO – 0.45-V I OH = –0.1 mA, V CCIO = 1.4V

V CCIO – 0.2

-V

Schmitt Trigger Input DC Voltage Specifications

SSTL2-1 DC Voltage Specifications

V OL

Low level output voltage

I OL = 8 mA, V CCIO = 1.4V -0.4V I OL = 0.1 mA, V CCIO = 1.4V

0.2

Notes:

1.Hysteresis used on 1.5V inputs.

Symbol Parameter

Test Conditions

Min.Max.Units V CCIO Input source voltage

- 1.4 3.9V V T+

Input hysteresis threshold voltage

-0.5 x V CCIO

0.8 x V CCIO

V T- -0.2 x V CCIO 0.5 x V CCIO V

Symbol Parameter

Test Conditions

Min.Typ Max.Units V CCIO Input source voltage - 2.3 2.5 2.7V V REF (1)Input reference voltage - 1.15 1.25 1.35V V TT (2)Termination voltage -V REF – 0.04 1.25V REF + 0.04

V V IH High level input voltage -V REF + 0.18

- 3.9V V IL Low level input voltage -–0.3-V REF – 0.18

V V OH High level output voltage I OH = –8 mA, V CCIO = 2.3V V CCIO – 0.62

--V V OL

Low level output voltage

I OL = 8 mA, V CCIO = 2.3V

--0.54

Notes:

1.V REF should track the variations in V CCIO , also peak to peak AC noise on V REF may not exceed ± 2% V REF

2.V TT of transmitting device must track V REF of receiving devices

Symbol Parameter

Test Conditions Min.Max.Units

SSTL3-1 DC Voltage Specifications

Symbol Parameter Test Conditions Min.Typ Max.Units V CCIO Input source voltage- 3.0 3.3 3.6V

V REF(1)Input reference voltage- 1.3 1.5 1.7V

V TT(2)Termination voltage-V REF – 0.05 1.5V REF + 0.05V

V IH High level input voltage-V REF + 0.2-V CCIO + 0.3V

V IL Low level input voltage-–0.3-V REF – 0.2V

V OH High level output voltage I OH = –8 mA, V CCIO = 3V V CCIO – 1.1--V

V OL Low level output voltage I OL = 8 mA, V CCIO = 3V--0.7V Notes:

1.V REF should track the variations in V CCIO, also peak to peak AC noise on V REF may not exceed ± 2% V REF

2.V TT of transmitting device must track V REF of receiving devices

HSTL1 DC Voltage Specifications

Symbol Parameter Test Conditions Min.Typ Max.Units V CCIO Input source voltage- 1.4 1.5 1.6V

V REF(1)Input reference voltage-0.680.750.90V

V TT(2)Termination voltage--V CCIO x0.5-V

V IH High level input voltage-V REF + 0.1- 1.9V

V IL Low level input voltage-–0.3-V REF – 0.1V

V OH High level output voltage I OH = –8 mA, V CCIO = 1.7V V CCIO – 0.4--V

V OL Low level output voltage I OL = 8 mA, V CCIO = 1.7V--0.4V Notes:

1.V REF should track the variations in V CCIO, also peak-to-peak AC noise on V REF may not exceed ± 2% V REF

2.V TT of transmitting device must track V REF of receiving devices

DS094 (v2.7) March 7, 2005

AC Electrical Characteristics Over Recommended Operating Conditions

Symbol Parameter

-6

-7Units Min.Max.Min.Max.T PD1Propagation delay single p-term - 5.7- 6.7ns T PD2Propagation delay OR array - 6.0-7.5ns T SUD Direct input register clock setup time 2.6- 3.0-ns T SU1Setup time (single p-term) 2.4- 2.8-ns T SU2Setup time (OR array) 2.7- 3.3-ns T HD Direct input register hold time 0-0-ns T H P-term hold time 0-0-ns T CO Clock to output - 4.5- 6.0ns F TOGGLE (1)Internal toggle rate

-450-300MHz F SYSTEM1(2)Maximum system frequency -256-152MHz F SYSTEM2(2)Maximum system frequency -238-141MHz F EXT1(3)Maximum external frequency -145-114MHz F EXT2(3)Maximum external frequency

-139-108MHz T PSUD Direct input register p-term clock setup time 0.9- 1.7-ns T PSU1P-term clock setup time (single p-term)0.7- 1.5-ns T PSU2P-term clock setup time (OR array) 1.0- 2.0-ns T PHD Direct input register p-term clock hold time 0.9- 1.2-ns T PH P-term clock hold 0.7- 1.0-ns T PCO P-term clock to output

- 6.2-7.3ns T OE /T OD Global OE to output enable/disable - 5.6-7.0ns T POE /T POD P-term OE to output enable/disable

-7.0-8.0ns T MOE /T MOD Macrocell driven OE to output enable/disable -7.4-9.9ns T PAO P-term set/reset to output valid -7.0-8.1ns T AO Global set/reset to output valid - 5.5-7.6ns T SUEC Register clock enable setup time 2.5- 3.1-ns T HEC Register clock enable hold time 0-0-ns T CW Global clock pulse width High or Low 1.4- 2.2-ns T PCW P-term pulse width High or Low

6.0-

7.5-ns T APRPW Asynchronous preset/reset pulse width (High or Low) 6.0-7.5-ns T DGSU Set-up before DataGATE latch assertion 0-0-ns T DGH Hold to DataGATE latch assertion 4.0- 6.0-ns T DGR DataGATE recovery to new data -

8.2-

9.0ns T DGW DataGATE low pulse width

2.5-

3.5-ns T CDRSU

CDRST setup time before falling edge GCLK2

1.3

- 2.0

-ns

DS094 (v2.7) March 7, 2005

T CDRH Hold time CDRST after falling edge GCLK2

0-0-ns T CONFIG (4)

Configuration time

150

-150

-μs

Notes:

1.F TOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more

information).

2.F SYSTEM1 (1/T CYCLE ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per

macrocell while F SYSTEM2 is through the OR array.

3.F EXT1 (1/T SU1+T CO ) is the maximum external frequency using one p-term while F EXT2 is through the OR array.

4.Typical configuration current during T CONFIG is approximately 7.7 m A.

Symbol Parameter

-6

-7Units Min.Max.Min.Max.

Internal Timing Parameters

Symbol Parameter (2)

-6

-7

Units Min.Max.Min.Max.Buffer Delays

T IN Input buffer delay

- 2.4- 2.6ns T DIN Direct data register input delay - 3.1- 3.9ns T GCK Global Clock buffer delay - 1.8- 2.7ns T GSR Global set/reset buffer delay - 2.0- 3.5ns T GTS Global 3-state buffer delay - 2.1- 3.0ns T OUT Output buffer delay

- 2.3- 2.6ns T EN

Output buffer enable/disable delay - 3.5- 4.0ns P-term Delays

T CT Control term delay - 1.1- 1.4ns T LOGI1Single P-term delay adder -0.5- 1.1ns T LOGI2

Multiple P-term delay adder -0.3-0.5ns Macrocell Delay

T PDI Input to output valid -0.5-0.7ns T SUI Setup before clock 1.3- 1.8-ns T HI Hold after clock 0-0-ns T ECSU Enable clock setup time 0.8- 1.8-ns T ECHO Enable clock hold time 0-0-ns T COI Clock to output valid -0.4-0.7ns T AOI Set/reset to output valid - 1.2- 1.5ns T CDBL

Clock doubler delay -0-0ns Feedback Delays

T F Feedback delay

- 1.7- 3.0ns T OEM Macrocell to global OE delay - 1.7- 2.5ns I/O Standard Time Adder Delays 1.5V CMOS

T IN15Standard input adder -0.8- 1.0ns T HYS15Hysteresis input adder - 3.0- 4.0ns T OUT15Output adder

-0.8- 1.0ns T SLEW15Output slew rate adder - 4.0- 5.0ns I/O Standard Time Adder Delays 1.8V CMOS

T HYS18Hysteresis input adder - 2.0- 3.0ns T OUT18Output adder

-0-0ns T SLEW

Output slew rate adder

2.0

- 4.0

DS094 (v2.7) March 7, 2005

Switching Characteristics

AC Test Circuit

I/O Standard Time Adder Delays 2.5V CMOS

T IN25Standard input adder -0.6- 1.0ns T HYS25Hysteresis input adder - 1.5- 3.0ns T OUT25Output adder

-0.8- 2.0ns T SLEW25Output slew rate adder - 3.0- 4.0ns I/O Standard Time Adder Delays 3.3V CMOS/TTL

T IN33Standard input adder -0.5-

2.0ns T HYS33Hysteresis input adder - 1.2-

3.0ns T OUT33Output adder

- 1.2- 3.0ns T SLEW33Output slew rate adder

- 3.0- 4.0ns I/O Standard Time Adder Delays HSTL, SSTL

SSTL2-1Input adder to T IN , T DIN , T GCK , T GSR ,T GTS -0.4- 1.0ns Output adder to T OUT

--0.5-0.0ns SSTL3-1Input adder to T IN , T DIN , T GCK , T GSR ,T GTS -0.4- 1.0ns Output adder to T OUT

--0.5-0.0ns HSTL-1

Input adder to T IN , T DIN , T GCK , T

GSR ,T GTS -0.6- 1.0ns Output adder to T OUT

Notes:

1. 1.5 ns input pin signal rise/fall.

Internal Timing Parameters (Continued)

Symbol Parameter (2)

-6

-7

Units Min.Max.Min.Max.Figure 2: Derating Curve for T PD

Figure 4: Typical I/V Curve for XC2C256

DS094 (v2.7) March 7, 2005

Pin Descriptions

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O Bank

11---2B3212---208B421(GSR)399A3143206C4214--142205A2215---203A321697B4140202A4217------18------19------110------111------11296-139201B5211395-138200A5211494A4137199E82115---198B62116-C5-197C722(GTS2)

11A123D3222---4C322(GTS3)

32B235E3224-B146B222(GTS0)

53C357D4226---8D2227------28------29------210------211------2(GTS1)

124C269E52213-C1710B122146D2912E422157-1014C122

31--136196A6232-B5135195D7233--134194B7234-A5-193E923593-133192A7236C6191D8237------38------39------310------311------31292--189B82313-B6- 188

C8231491A6132187A82315-C7-186E11231690B7131185E102418E31115F22429-1216F324310E21317G4244-E11418G324511F31519F524612F21620G5247------48------49------410------411------412-F11721H2241313G1-22H42414--1823H32415----H124

Pin Descriptions (Continued)

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O

Bank

51-L3-49R1152--3348N4153---47N215(GCK1)

423L23246M3155L13145P115(GCK0)

622K33044M2157------58------59------510------511------512---43L31513---41N11514--2840L41515---39M11516-K1-38L5161-M13450N316 (CDRST)

224M23551P2163---54P416(GCK2)

427N23855P5165---56R2166---57T1167------68------69------610------611------6(DGE)1228P23958T21613-M34060N5161429N34161R41615-P34262M516

Pin Descriptions (Continued)

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O

Bank

71---37K4172---36L2173---35K3174---34L117519J22632K517618J12531K2177------78------79------710------71117H32430J4171216H22329K1171315H12228J3171414G32127J21715-G220-J51716--19-J1181-N44464R6182--4565N6183--4666R3184---67M6185--4869T318632-4970P6187------88------89------810------81133M55071T4181234N55172P7181335P55273T5181436M6-74N7181537N6-75R718

Pin Descriptions (Continued)

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O

Bank

DS094 (v2.7) March 7, 2005

9178C12112160B1329279B12113161B14293---162C1329480A12114163A15295164C1229681C11115165B12297------98------99------910------911---166D13291282B11116167A142913--117168E132914-A11118169A132915--119170C112916-C10-171A12210177A13111159A16210276B13110158B15210374C13107155C14210473C14106154G11210572D12105153B16210671D13104152D152107------108------109------1010------1011151E142101270D14103150C1621013---149F1421014-E12102148F1321015---147E15210

E13

101

146

G13

Pin Descriptions (Continued)

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O

Bank

111-B10--B112112--173D112113-A10-174A112114---175D102115-C9120-B102116--121-E122117------118------119------1110------111185A8124178F122111286B8125179B92111387C8126180C92111489-128182C1021115--129183A921116--130184D92121---145F152122--100144G142123---143E162124---142H122125-F12-140F162126-F13-139H162127------128------129------1210------121168F1498138G1521212-G1297137H132121367G1396136G162121466-95135H142121565-94134H15212

J12

Pin Descriptions (Continued)

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O

Bank

131-N1375107R15113253N1476108T161133-M1277109N14113454--110R161135-M1378111N15113655-79112M151137------138------139------1310------1311------1312-M1480113M131131356-81114P1611314-L1282115N1611315---116L1411316-L13-117M14114152P1474106P151142--71103P14114350P1270102P131144-M1169101R13114549N11-100N131146-P1168-R141147------148------149------1410------1411------1412---99T1511413--6697R121141446P106495N111141544---M11114

N10

Pin Descriptions (Continued)

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O

Bank

151---118L151152-L1483119L131153---120M121154---121M161155---122K141156---123L161157------158------159------1510------151158K1385125K151151259K1486126L121151360J1287127K161151461J1388128J141151563H1391-J151151664H1292131J131161---90P101162---89R101163-M8-88T101164---87R9116543N86086N9116642-5985M81167------168------169------1610------161141P85884T81161240M75783P81161339N75682R811614---80T711615--5478N8116

Notes:

1.GTS = global output enable, GSR = global reset/set, GCK =

global clock, CDRST = clock divide reset, DGE = DataGATE enable.

Pin Descriptions (Continued)

Function Block Macro-cell VQ100CP132TQ144PQ208FT256

I/O

Bank

DS094 (v2.7) March 7, 2005

XC2C256 JTAG, Power/Ground, No Connect Pins and Total User I/O

Pin Type

VQ100CP132TQ144PQ208FT256TCK 48M106798P12TDI 45M96394R11TDO 83B9122176A10TMS

47N106596N12V AUX (JTAG supply voltage)5D3811F4

Power internal (V CC )26, 57P1, K12, A21, 37, 841, 53, 124P3, K13, D12, D5Power Bank 1 I/O (V CCIO1)20, 38, 51J3, P7, G14, P1327, 55, 73, 9333, 59, 79, 92, 105, 132J6, K6, L7, L8, J11, K11, L10, L9Power Bank 2 I/O (V CCIO2)88, 98A14, C4, A7109, 127, 14126, 133, 157, 172, 181, 204 F7, F8, G6, H6, F10,

F9, H11Ground

21, 25, 31, 62, 69, 75, 84, 100

K2, N1, P4, N9, N12, J14, H14, E14, B14, A9, B3

29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144

13, 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190,

207

F11, F6, G10, G7, G8, G9, H10, H7, H8, H9, J10, J7, J8, J9, K10, K7, K8, K9, L11, L6No connects ---

-A1, C2, E6, D1, E1, G2, F1, G1, M4, T9, P9, M9, M10, T11, T12, T13, P11, T14, J16, K12, D16, G12, C15, D14, D6, C6, E7, C5

Total user I/O 80106118173

184

Ordering Information

Part Number Pin/Ball Spacing θJA

(C/Watt)θJC (C/Watt)Package Type Package Body Dimensions I/O Commercia

l (C)

Industrial (I)(1)

XC2C256-6VQ100C 0.5mm 43.110.9Very Thin Quad Flat

Pack 14mm x 14mm 80C XC2C256-7VQ100C 0.5mm 43.110.9Very Thin Quad Flat

Pack 14mm x 14mm 80C XC2C256-6CP132C 0.5mm 65.015.0Chip Scale Package 8mm x 8mm 106C XC2C256-7CP132C 0.5mm 65.015.0Chip Scale Package 8mm x 8mm 106C XC2C256-6TQ144C 0.5mm 37.27.2Thin Quad Flat Pack 20mm x 20mm 118C XC2C256-7TQ144C 0.5mm 37.27.2Thin Quad Flat Pack 20mm x 20mm 118C XC2C256-6PQ208C 0.5mm 36.99.7Plastic Quad Flat

Pack 28mm x 28mm 173C XC2C256-7PQ208C 0.5mm 36.99.7Plastic Quad Flat

Pack 28mm x 28mm 173C XC2C256-6FT256C 1.0mm 34.6 6.1Fine Pitch Thin BGA 17mm x 17mm 184C XC2C256-7FT256C 1.0mm 34.6 6.1Fine Pitch Thin BGA 17mm x 17mm 184C XC2C256-6VQG100C 0.5mm 43.110.9Very Thin Quad Flat Pack; Pb-free 14mm x 14mm 80C XC2C256-7VQG100C 0.5mm 43.110.9Very Thin Quad Flat Pack; Pb-free 14mm x 14mm 80C XC2C256-6CPG132C 0.5mm 65.015.0Chip Scale Package;

Pb-free 8mm x 8mm 106C XC2C256-7CPG132C 0.5mm 65.015.0Chip Scale Package;

Pb-free 8mm x 8mm 106C XC2C256-6TQG144C 0.5mm 37.27.2Thin Quad Flat Pack;

Pb-free 20mm x 20mm 118C XC2C256-7TQG144C 0.5mm 37.27.2Thin Quad Flat Pack;

Pb-free 20mm x 20mm 118C XC2C256-6PQG208C 0.5mm 36.99.7Plastic Quad Flat Pack; Pb-free 28mm x 28mm 173C XC2C256-7PQG208C 0.5mm 36.99.7Plastic Quad Flat Pack; Pb-free 28mm x 28mm 173C XC2C256-6FTG256C 1.0mm 34.6 6.1Fine Pitch Thin BGA;

Pb-free 17mm x 17mm 184C XC2C256-7FTG256C 1.0mm 34.6 6.1Fine Pitch Thin BGA;

Pb-free 17mm x 17mm 184C XC2C256-7VQ100I 0.5mm 43.110.9Very Thin Quad Flat

Pack 14mm x 14mm 80I XC2C256-7CP132I 0.5mm 65.015.0Chip Scale Package 8mm x 8mm 106I XC2C256-7TQ144I 0.5mm 37.27.2Thin Quad Flat Pack 20mm x 20mm 118I XC2C256-7PQ208I 0.5mm 36.99.7Plastic Quad Flat

Pack 28mm x 28mm 173I XC2C256-7FT256I

1.0mm

34.6

6.1

Fine Pitch Thin BGA

17mm x 17mm

184

DS094 (v2.7) March 7, 2005

Device Part Marking

Figure 5: Sample Package with Part Marking

Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale packages by line are:?Line 1 = X (Xilinx logo) then truncated part number ?Line 2 = Not related to device part number ?

Line 3 = Not related to device part number

1.Line 4 = Package code, speed, operating temperature,

three digits not related to device part number. Package codes: C5 = CP132, C6 = CPG132.

XC2C256-7VQG100I 0.5mm 43.110.9Very Thin Quad Flat Pack; Pb-free 14mm x 14mm 80I XC2C256-7CPG132I 0.5mm 65.015.0Chip Scale Package;

Pb-free 8mm x 8mm 106I XC2C256-7TQG144I 0.5mm 37.27.2Thin Quad Flat Pack;

Pb-free 20mm x 20mm 118I XC2C256-7PQG208I 0.5mm 36.99.7Plastic Quad Flat Pack; Pb-free 28mm x 28mm 173I XC2C256-7FTG256I

1.0mm

34.6

6.1

Fine Pitch Thin BGA;

Pb-free

17mm x 17mm

184

Notes:

1. C = Commercial (T A = 0°C to +70°C); I = Industrial (T A = –40°C to +85°C).

Part Number Pin/Ball Spacing θJA

(C/Watt)θJC (C/Watt)Package Type Package Body Dimensions I/O Commercia

l (C)

Industrial (I)

(1)

Figure 6: VQ100 Very Thin Quad Flat Pack

Figure 7: CP132 Chip Scale Package

DS094 (v2.7) March 7, 2005