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ACT-5260PC-133F17T中文资料

Features

BLOCK DIAGRAM

s Full militarized QED RM5260 microprocessor

Dual Issue superscalar QED RISCMark ? - can issue one integer and one floating-point instruction per cycle microprocessor - can issue one integer and one floating-point instruction per cycle

q 100, 133 and 150MHz frequency (200MHz future option) Consult Factory for latest speeds q 260 Dhrystone2.1 MIPS

q SPECInt95 4.8. SPECfp95 5.1

High performance system interface compatible with R4600, R4700 and R5000

q 64-bit multiplexed system address/data bus for optimum price/performance up to 100 MHz operating frequency q High performance write protocols maximize uncached write bandwidth

q Operates at input system clock multipliers of 2 through 8q 5V tolerant I/O's

q IEEE 1149.1 JTAG boundary scan

Integrated on-chip caches - up to 3.2GBps internal data rate q 16KB instruction - 2 way set associative q 16KB data - 2 way set associative q Virtually indexed, physically tagged

q Write-back and write-through on per page basis

q Pipeline restart on first double for data cache misses s

Integrated memory management unit

q Fully associative joint TLB (shared by I and D translations)q 48 dual entries map 96 pages

q Variable page size (4KB to 16MB in 4x increments)

Embedded supply de-coupling capacitors and Pll filter components

High-performance floating point unit - up to 400 MFLOPS q Single cycle repeat rate for common single precision operations and some double precision operations

q Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations q Single cycle repeat rate for single precision combined multiply-add operation s

MIPS IV instruction set

q Floating point multiply-add instruction increases performance in signal processing and graphics applications

q Conditional moves to reduce branch frequency q Index address modes (register + register)s

Embedded application enhancements

q Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction q I and D cache locking by set

q Optional dedicated exception vector for interrupts s

Fully static CMOS design with power down logic

q Standby reduced power mode with WAIT instruction q 5 Watts typical at 3.3V , less than 175 mwatts in Standby s 208-lead CQFP , cavity-up package (F17)

208-lead CQFP , inverted footprint (F24), Intended to duplicate the commercial QED footprin t (Consult Factory)s

179-pin PGA package (Future Product ) (P10)

Store Buffer

Data Set A Data Tag A DTLB Physical Data Tag B

Instruction Set A

Integer Instruction Register

FP Instruction Register

Instruction Set B Address Buffer Instruction Tag A ITLB Physical

Instruction Tag B

Sys AD

Write Buffer Read Buffer Data Set B

DBus

Control

Floating-point Register File Joint TLB

Tag

Aux Tag

IntIBus

Floating-point Coprocessor 0

Unpacker/Packer

MAdd, Add, Sub,Cvt

PC Incrementer Branch Adder DVA

Load Aligner

Integer Register File Integer/Address Adder Data TLB Virtual Shifter/Store Aligner

Logic Unit Integer Multiply, Divide

Integer Control

Instruction TLB Virtual F l o a t i n g p o i n t C o n t r o l

Phase Lock Loop

Instruction Select

FPIBus

ABus

System/Memory

Control

Program Counter

IVA

Div, SqRt

64-Bit Superscaler Microprocessor

ACT5260

DESCRIPTION:

The ACT5260 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 64-bit system interface. The ACT5260 can issue both an integer and a floating point instruction in the same cycle.

The ACT5260 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.

HARDWARE OVERVIEW

The ACT5260 offers a high-level of integration targeted at high-performance embedded applications. Some of the key elements of the ACT5260 are briefly described below. Superscalar Dispatch

The ACT5260 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5260 provides unparalleled price/performance in computationally intensive embedded applications.

CPU Registers

Like all MIPS ISA processors, the ACT5260 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Pipeline

For integer operations, loads, stores, and other non-floating-point operations, the ACT5260 uses the simple 5-stage pipeline also found in the circuits R4600, R4700, and R5000. In addition to this standard pipeline, the ACT5260 uses an extended seven stage pipeline for floating-point operations. Like the R5000, the ACT5260 does virtual to physical translation in parallel with cache access.Integer Unit

Like the R5000, the ACT5260 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5260 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5260 datasheet, these instructions are integer multiply-accumulate and 3-operand integer multiply.

The ACT5260 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/ divide operations, and the program counter(PC). Register File

The ACT5260 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.

ALU

The ACT5260 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle

For additional Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMark? RM5260?, 64-Bit Superscalar Microprocessor see the latest QED datasheet (Revision 1.1 July 1998).

Absolute Maximum Ratings1

Symbol Rating Range Units V TERM T erminal Voltage with respect to GND-0.52 to 4.6V Tc Operating T emperature-55 to +125°C T BIAS Case T emperature under Bias-55 to +125°C T STG Storage T emperature-55 to +125°C

I IN DC Input Current203mA

I OUT DC Output Current50mA Notes:

1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. V IN minimum = -2.0V for pulse width less than 15nS. V IN maximum should not exceed +5.5 Volts.

3. When V IN < 0V or V IN > Vcc.

4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.

Recommended Operating Conditions

Symbol Parameter Minimum Maximum Units V CC Power Supply Voltage+3.135+3.465V V IH Input High Voltage0.7V CC V CC+ 0.5V V IL Input Low Voltage-0.50.2V CC V T C Operating Temperature Case -55+125°C For 133MHz Parts only -40+125°C

DC Characteristics

(V CC = 3.3V ±5%; 133MHz parts: Tc =-40°C to +125°C, All other parts Tc =-55°C to +125°C)

Parameter Sym Conditions 100 / 133 / 150MHz

Units Min Max

Output Low Voltage V OL1I OL = 20 μA-0.1V Output High Voltage V OH1I OL = 20 μA Vcc - 0.1-V Output Low Voltage V OL2I OL = 4 mA-0.4V Output High Voltage V OH2I OL = 4 mA 2.4-V Input High Voltage V IH0.7V CC V CC+ 0.5V Input Low Voltage V IL-0.50.2V CC V Input Current I IN1V IN = 0V-20+20μA Input Current I IN2V IN = V CC-20+20μA Input Current I IN3V IN = 5.5V-250+250μA Input Capacitance C IN-10pF Output Capacitance C OUT-10pF

AC Characteristics

(V CC = 3.3V ±5%; 133MHz parts: Tc =-40°C to +125°C, All other parts Tc =-55°C to +125°C)

Power Consumption

Parameter Symbol Conditions

100MHz, 3.3V 133MHz, 3.3V 150MHz, 3.3V Units Typ 5Max Typ 5Max Typ 5Max Active Operating Supply Current

I CC1C L = 0pF ,

No SysAD activity

8001550800155010001750mA I CC2C L = 50pF , R4000 write

protocol without FPU operation 100017501000175011501950mA I CC3

C L = 50pF , write re-issue or pipelined writes 110020001100200012502250mA Standby Current

I SB1C L = 0pF 7515075150100175mA I SB1

C L = 50pF

150

100

175

Notes:

5. Typical integer instruction mix and cache miss rates.

Capacitive Load Deration

Symbol Parameter

100 / 133 / 150MHz Units Minimum

Maximum

C LD

Load Derate

-2

ns/25pF

Clock Parameters

Parameter Symbol Test Conditions

100/133/150MHz Units Min Max SysClock High t SCHigh T 4-ns SysClock Low t SCLow

T 4-ns SysClock Frequency 63375MHz SysClock Period t SCP -30ns Clock Jitter for SysClock t JitterIn -±250ps SysClock Rise Time t SCRise -5ns SysClock Fall Time t SCFall -5ns ModeClock Period t ModeCKP -256*t SCP ns JTAG Clock Period

t JTAGCKP -4*t SCP

Notes:

6. Operation of the ACT5260 is only guaranteed with the Phase Loop enabled.

System Interface Parameters7

Parameter Symbol Test Conditions

100MHz133MHz150MHz

Units Min Max Min Max Min Max

Data Output8

t DO mode14...13 = 10 (fastest) 1.07.0 1.07.0 1.07.0ns mode14...13 = 11 1.07.5 1.07.5 1.07.5ns mode14...13 = 00 1.08.0 1.08.0 1.08.0ns mode14...13 = 01 (slowest) 1.08.5 1.08.5 1.08.5ns

Data Setup t DS t RISE = 5ns 5.0- 5.0- 5.0-ns Data Hold t DH t FALL= 5ns 2.0- 2.0- 2.0-ns Notes: -

7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal.

8. Capacitive load for all output timing is 50pF.

Boot Time Interface Parameters

Parameter Symbol Test Conditions 100/133/150MHz

Units Min Max

Mode Data Setup t DS4-SysClock cycles Mode Data Hold t DH0-SysClock cycles

1.8401.880

1.700BSC 1.700BSC 1.8401.880

V U T R P N M L K J H G F E D C B A

9101112131415161718

Bottom View

Side View

Future Package – "P10" – PGA 179 Pins (Advanced)

1.131 (28.727) SQ 1.109 (28.169) SQ

1.009 (25.63).9998 (25.37)51 Spaces at .0197(51 Spaces at .50)

.0236 (.51).0158 (.49)

208

156

157

105

10453Pin 1 Chamfer

Detail "A"

0°±5°1.331 (33.807)1.269 (32.233)

.005 (.127).008 (.258)

.055 (1.397)

REF .055 (1.397).045 (1.143)

.115 (2.921)

MAX

.960 (24.384) SQ

REF

.130 (3.302)

MAX

.010R MIN

.010R MIN .009 (.253).007 (.178)

.015 (.381).009 (.229)

.100 (2.540).080 (2.032)

Package Information – "F17" – CQFP 208 Leads

Detail "A"

BSC

.100.221MAX

.018

.050

Note: Pin rotation is opposite of QEDs PQUAD due to cavity-up construction.

.035 (.889).025 (.635)

Units: Inches (Millimeters)

ACT5260 Microprocessor CQFP Pinouts – "F17"

Pin #Function Pin #Function Pin # Function Pin # Function 1Vcc (3.3V)53NC105Vcc (3.3V)157NC

2NC54NC106NMI*158NC

3NC55NC107ExtRqst*159NC

4Vcc (3.3V)56Vcc (3.3V)108Reset*160NC

5Vss57Vss109ColdReset*161Vcc (3.3V) 6SysAD458ModeIn110VccOK162Vss

7SysAD3659RdRdy*111BigEndian163SysAD28 8SysAD560WrRdy*112Vcc (3.3V)164SysAD60 9SysAD3761ValidIn*113Vss165SysAD29 10Vcc (3.3V)62ValidOut*114SysAD16166SysAD61 11Vss63Release*115SysAD48167Vcc (3.3V) 12SysAD664VccP116Vcc (3.3V)168Vss

13SysAD3865VssP117Vss169SysAD30 14Vcc (3.3V)66SysClock118SysAD17170SysAD62 15Vss67Vcc (3.3V)119SysAD49171Vcc (3.3V) 16SysAD768Vss120SysAD18172Vss

17SysAD3969Vcc (3.3V)121SysAD50173SysAD31 18SysAD870Vss122Vcc (3.3V)174SysAD63 19SysAD4071Vcc (3.3V)123Vss175SysADC2 20Vcc (3.3V)72Vss124SysAD19176SysADC6 21Vss73SysCmd0125SysAD51177Vcc (3.3V) 22SysAD974SysCmd1126Vcc (3.3V)178Vss

23SysAD4175SysCmd2127Vss179SysADC3 24Vcc (3.3V)76SysCmd3128SysAD20180SysADC7 25Vss77Vcc (3.3V)129SysAD52181Vcc (3.3V) 26SysAD1078Vss130SysAD21182Vss

27SysAD4279SysCmd4131SysAD53183SysADC0 28SysAD1180SysCmd5132Vcc (3.3V)184SysADC4 29SysAD4381Vcc (3.3V)133Vss185Vcc (3.3V) 30Vcc (3.3V)82Vss134SysAD22186Vss

31Vss83SysCmd6135SysAD54187SysADC1 32SysAD1284SysCmd7136Vcc (3.3V)188SysADC5 33SysAD4485SysCmd8137Vss189SysAD0 34Vcc (3.3V)86SysCmdP138SysAD23190SysAD32 35Vss87Vcc (3.3V)139SysAD55191Vcc (3.3V) 36SysAD1388Vss140SysAD24192Vss

37SysAD4589Vcc (3.3V)141SysAD56193SysAD1 38SysAD1490Vss142Vcc (3.3V)194SysAD33 39SysAD4691Vcc (3.3V)143Vss195Vcc (3.3V) 40Vcc (3.3V)92Vss144SysAD25196Vss

41Vss93Int0*145SysAD57197SysAD2 42SysAD1594Int1*146Vcc (3.3V)198SysAD34 43SysAD4795Int2*147Vss199SysAD3 44Vcc (3.3V)96Int3*148SysAD26200SysAD35 45Vss97Int4*149SysAD58201Vcc (3.3V) 46ModeClock98Int5*150SysAD27202Vss

47JTDO99Vcc (3.3V)151SysAD59203NC

48JTDI100Vss152Vcc (3.3V)204NC

49JTCK101NC153Vss205NC

50JTMS102NC154NC206NC

51Vcc (3.3V)103NC155NC207Vcc (3.3V) 52Vss104NC156Vss208Vss

Ordering Information

Part Number

Screening

Speed (MHz)Package ACT-5260PC-100F17C Commercial Temperature (0°C to +70°C)100 208 Lead CQFP ACT-5260PC-133F17C Commercial Temperature (0°C to +70°C)133 208 Lead CQFP ACT-5260PC-150F17C Commercial Temperature (0°C to +70°C)150 208 Lead CQFP ACT-5260PC-100F17I Industrial Temperature (-40°C to +85°C)100 208 Lead CQFP ACT-5260PC-133F17I Industrial Temperature (-40°C to +85°C)133 208 Lead CQFP ACT-5260PC-150F17I Industrial Temperature (-40°C to +85°C)150 208 Lead CQFP ACT-5260PC-100F17T Military Temperature (-55°C to +125°C)100 208 Lead CQFP ACT-5260PC-133F17T Reduced Military Temperature (-40°C to +125°C)

133 208 Lead CQFP ACT-5260PC-150F17T Military Temperature (-55°C to +125°C)150 208 Lead CQFP ACT-5260PC-100F17M Military Temperature, Screened* (-55°C to +125°C)100 208 Lead CQFP ACT-5260PC-133F17M Reduced Military Temperature, Screened* (-40°C to +125°C)

133 208 Lead CQFP ACT-5260PC-150F17M

Military Temperature, Screened* (-55°C to +125°C)

150

208 Lead CQFP

Aeroflex Circuit Technology 35 South Service Road

Plainview New York 11803 Telephone: (516) 694-6700FAX: (516) 694-6715

Toll Free Inquiries: (800) https://www.wendangku.net/doc/0711050544.html,/act1.htm

E-Mail: sales-act@https://www.wendangku.net/doc/0711050544.html,

Specifications subject to change without notice.

C I R C U I T T E C H N O L O G Y

Part Number Breakdown

ACT–5260PC –100F17M

Aeroflex Circuit Technology

Base Processor Type 100 = 100MHz

133 = 133MHz (Screening: T & M -40°C to +125°C only)150 = 150MHz

200 = 200MHZ (Future option)

Cache Style

Package Type & Size

C = Commercial Temp, 0°C to +70°C I = Industrial T emp, -40°C to +85°C T = Military Temp, -55°C to +125°C

M = Military T emp, -55°C to +125°C, Screened *Q = MIL-PRF-38534 Compliant/SMD if applicable

Screening

* Screened to the individual test methods of MIL-STD-883

PC = Primary Cache Maximum Pipeline Freq.

Surface Mount Package

F17 = 1.120" SQ 208 Lead CQFP

F24 = 1.120" SQ Inverted 208 Lead CQFP (Consult Factory)

Thru-Hole Package

P10 = 1.86"SQ PGA 179 pins with shoulder Future Product