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SN74ALVCH16903DGGR中文资料

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FEATURES

DESCRIPTION

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

SN74ALVCH16903

3.3-V12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL3-STATE OUTPUTS

SCES095D–MARCH1997–REVISED SEPTEMBER2004

?Member of the Texas Instruments Widebus?

Family

?EPIC?(Enhanced-Performance Implanted

CMOS)Submicron Process

?Checks Parity

?Able to Cascade With a Second

SN74ALVCH16903

?ESD Protection Exceeds2000V Per

MIL-STD-883,Method3015;Exceeds200V

Using Machine Model(C=200pF,R=0)

?Latch-Up Performance Exceeds250mA Per

JESD17

?Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

?Package Options Include Plastic300-mil

Shrink Small-Outline(DL),Thin Shrink

Small-Outline(DGG),and Thin Very

Small-Outline(DGV)Packages

This12-bit universal bus driver is designed for2.3-V

to3.6-V V CC operation.

The SN74ALVCH16903has dual outputs and can

operate as a buffer or an edge-triggered register.In

both modes,parity is checked on APAR,which

arrives one cycle after the data to which it applies.

The YERR output,which is produced one cycle after

APAR,is open drain.

MODE selects one of the two data paths.When

MODE is low,the device operates as an

edge-triggered register.On the positive transition of

the clock(CLK)input and when the clock-enable

(CLKEN)input is low,data set up at the A inputs is stored in the internal registers.On the positive transition of CLK and when CLKEN is high,only data set up at the9A–12A inputs is stored in their internal registers.When MODE is high,the device operates as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN serves a dual purpose;it acts as a normal data bit and also enables YERR data to be clocked into the YERR output register.

When used as a single device,parity output enable(PAROE)must be tied high;when parity input/output (PARI/O)is low,even parity is selected and when PARI/O is high,odd parity is selected.When used in pairs and PAROE is low,the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903.When used in pairs and PAROE is high,PARI/O accepts a partial parity sum from the first SN74ALVCH16903.

A buffered output-enable(OE)input can be used to place the24outputs and YERR in either a normal logic state (high or low logic levels)or a high-impedance state.In the high-impedance state,the outputs neither load nor drive the bus lines significantly.The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operation of the device.Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus,EPIC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.Copyright?1997–2004,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

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DESCRIPTION (CONTINUED)

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

To ensure the high-impedance state during power up or power down,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH16903is characterized for operation from 0°C to 70°C.

FUNCTION TABLES

FUNCTION

INPUTS

OUTPUTS

OE MODE CLKEN CLK A 1Yn (1)–8Yn (1)

9Yn (1)–12Yn (1)

L L L ↑H H H L L L ↑L L L L L H ↑H Y 0H L L H ↑L Y 0L L H X X H H H L H X X L L L H X

(1)

n =1or 2

PARITY FUNCTION

INPUTS

OUTPUT ΣOF INPUTS YERR

OE PAROE

(1)

11A/YERREN (2)

PARI/O APAR 1A–10A =H L H L L 0,2,4,6,8,10L H L H L L 1,3,5,7,9L L L H L L 0,2,4,6,8,10H L L H L L 1,3,5,7,9H H L H L H 0,2,4,6,8,10L L L H L H 1,3,5,7,9L H L H L H 0,2,4,6,8,10H H L H L H 1,3,5,7,9

H L H X X X X X H L X

(1)When used as a single device,PAROE must be tied high.

(2)

Valid after appropriate number of clock pulses have set internal register

PARI/O FUNCTION (1)

INPUTS

OUTPUT ΣOF INPUTS PARI/O

PAROE APAR 1A–10A =H L 0,2,4,6,8,10L L L 1,3,5,7,9L H L 0,2,4,6,8,10H H L 1,3,5,7,9

H L H

(1)

This table applies to the first device of a cascaded pair of SN74ALVCH16903devices.

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YERR

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

LOGIC DIAGRAM (POSITIVE LOGIC)

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ABSOLUTE MAXIMUM RATINGS (1)

RECOMMENDED OPERATING CONDITIONS (1)

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT V CC Supply voltage range -0.5 4.6V V I Input voltage range (2)-0.5 4.6V V O Output voltage range (2)(3)-0.5

V CC +0.5

V I IK Input clamp current V I <0-50mA I OK Output clamp current V O <0

-50mA I O

Continuous output current

±50mA Continuous current through each V CC or GND

±100mA

DGG package

81θJA Package thermal impedance (4)DGV package 86°C/W DL package

74T stg Storage temperature range

-65

150

°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3)This value is limited to 4.6V maximum.

(4)

The package thermal impedance is calculated in accordance with JESD 51.

MIN

MAX UNIT V CC Supply voltage 2.3 3.6

V V CC =2.3V to 2.7V 1.7V IH High-level input voltage V V CC =2.7V to 3.6V 2

V CC =2.3V to 2.7V 0.7V IL Low-level input voltage V V CC =2.7V to 3.6V

0.8V I Input voltage 0V CC V V O

Output voltage

0V CC V

V CC =2.3V

-12Y port V CC =2.7V -12I OH

High-level output current

PARI/O -12V CC =3V Y port -24V CC =2.3V 12Y port V CC =2.7V

12I OL

Low-level output current

PARI/O 12mA V CC =3V

Y port 24YERR output

24?t/?v Input transition rise or fall rate 010ns/V T A Operating free-air temperature

°C (1)

All unused control inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.

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ELECTRICAL CHARACTERISTICS

SN74ALVCH16903

3.3-V12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL3-STATE OUTPUTS

SCES095D–MARCH1997–REVISED SEPTEMBER2004

over recommended operating free-air temperature range(unless otherwise noted)

PARAMETER TEST CONDITIONS V CC MIN TYP(1)MAX UNIT

I OH=-100μA 2.3V to3.6V V CC-0.2

I OH=-6mA,V IH=1.7V 2.3V2

V IH=1.7V 2.3V 1.7

Y port

V OH I OH=-12mA 2.7V 2.2V

V IH=2V

3V 2.4

I OH=-24mA,V IH=2V3V2

PARI/O I OH=-12mA,V IH=2V3V2

I OL=100μA 2.3V to3.6V0.2

I OL=6mA,V IL=0.7V 2.3V0.4

Y port V IL=0.7V 2.3V0.7

I OL=12mA

V OL V IL=0.8V 2.7V0.4V

I OL=24mA,V IL=0.8V3V0.55

PARI/O I OL=12mA,V IL=0.8V3V0.55

YERR output I OL=24mA3V0.5

I I V I=V CC or GND 3.6V±5μA

V I=0.7V 2.3V45

V I=1.7V 2.3V-45

I I(hold)V I=0.8V3V75μA

V I=2V3V-75

V I=0to3.6V(2) 3.6V±500

I OH YERR output V O=V CC0to3.6V±10μA

I OZ(3)V O=V CC or GND 3.6V±10μA

I CC V I=V CC or GND,I O=0 3.6V40μA

?I CC One input at V CC-0.6V,Other inputs at V CC or GND3V to3.6V750μA

Control inputs 5.5

C i V I=V CC or GN

D 3.3V pF

Data inputs 5.5

YERR output5

C o V O=V CC or GN

D 3.3V pF

Data outputs6

C io PARI/O V O=V CC or GN

D 3.3V7pF

(1)All typical values are at V CC=3.3V,T A=25°C.

(2)This is the bus-hold maximum dynamic current.It is the minimum overdrive current required to switch the input from one state to

another.

(3)For I/O ports,the parameter I OZ includes the input leakage current.

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TIMING REQUIREMENTS

SWITCHING CHARACTERISTICS

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(see Figure 1and Figure 4)

V CC =2.5V V CC =3.3V V CC =2.7V ±0.2V ±0.3V UNIT

MIN

MAX MIN

MAX f clock Clock frequency 125

125

MHz t w

Pulse duration,CLK ↑

333ns 1A–12A before CLK ↑Register mode 1.7 1.9 1.451A–10A before CLK ↑

Buffer mode 5.9 5.2 4.4Register mode 1.2 1.5 1.3APAR before CLK ↑t su

Setup time

Buffer mode 4.6 3.6 3.1ns

PARI/O before CLK ↑Both modes 2.42 1.711A/YERREN before CLK ↑Buffer mode 2 1.9 1.6CLKEN before CLK ↑Register mode 2.5 2.6 2.21A–12A after CLK ↑Register mode 0.40.250.551A–10A after CLK ↑Buffer mode 0.250.250.25Register mode 0.70.40.7APAR after CLK ↑

Buffer mode 0.250.250.25t h

Hold time

ns Register mode 0.250.250.4PARI/O after CLK ↑Buffer mode 0.250.250.511A/YERREN after CLK ↑Buffer mode 0.250.250.4CLKEN after CLK ↑

0.25

0.50.4

over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1and Figure 4)

V CC =2.5V V CC =3.3V V CC =2.7V FROM TO ±0.2V ±0.3V PARAMETER UNIT

(INPUT)

(OUTPUT)

MIN MAX

f max

125125

125MHz Buffer mode

A Y 1 4.4 4.2 1.1 3.8t pd YERR 1 5.7 4.9 1.4 4.4ns

Both modes CLK PARI/O 1.28.67.9 1.7 6.6t pd (1)Both modes CLK PARI/O 1 6.8 5.2 1.3 4.5ns t pd Both modes MODE Y 1 5.9 5.8 1.3 4.9ns t PLH 1 6.1 5.5 1.2 4.8Register mode CLK Y ns t PHL 1 5.9 4.9 1.2 4.6OE Y 1.1 6.5 6.4 1.4 5.4t en Both modes ns PAROE PARI/O 1 5.661 4.8OE Y 1 6.4 5.2 1.75t dis Both modes ns PAROE PARI/O 1 3.2 3.8 1.2 3.8t PLH 1 3.6 4.2 1.94Both modes

YERR

ns t PHL 1.2

5.1 4.9 1.5

4.2

(1)

See Figure 2and Figure 5for the load specification.

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SIMULTANEOUS SWITCHING CHARACTERISTICS(1) OPERATING CHARACTERISTICS FOR BUFFER MODE OPERATING CHARACTERISTICS FOR REGISTER MODE

SN74ALVCH16903 3.3-V12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL3-STATE OUTPUTS

SCES095D–MARCH1997–REVISED SEPTEMBER2004

(see Figure3and Figure6)

V CC=2.5V V CC=3.3V

V CC=2.7V

FROM TO±0.2V±0.3V PARAMETER UNIT

(INPUT)(OUTPUT)

MIN MAX MIN MAX MIN MAX

t PLH 1.8 6.5 6.1 1.85 Register mode CLK Y ns

t PHL 1.4 5.9 5.1 1.7 4.5

(1)All outputs switching

=25°C

V CC=2.5V V CC=3.3V

±0.2V±0.3V

PARAMETER TEST CONDITIONS UNIT

TYP TYP

Outputs enabled57.565

C pd Power dissipation capacitance C L=0,f=10MHz pF

Outputs disabled1517.5

=25°C

V CC=2.5V V CC=3.3V

±0.2V±0.3V

PARAMETER TEST CONDITIONS UNIT

TYP TYP

Outputs enabled5787.5

C pd Power dissipation capacitance C L=0,f=10MHz pF

Outputs disabled16.534

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PARAMETER MEASUREMENT INFORMATION

V OH

V OL From Output Under Test

C L LOA

D CIRCUIT

Open

Output Control (low-level enabling)

Output Waveform 1S1 at 2 × V CC (see Note B)

Output Waveform 2S1 at GND (see Note B)0 V

0 V

V CC

0 V

V CC

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PULSE DURATION

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

Timing Input

Data Input

Input

t pd t PLZ /t PZL t PHZ /t PZH

Open 2 × V CC GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2 ns, t f ≤ 2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .H.t PHL is measured at V CC /2.

I.t PLH is measured at V OL + 0.15 V.

0 V

V CC

Input

Output

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

× V CC

V CC

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

V CC =2.5V ±0.2V

Figure 1.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION

From Output Under Test

PARI/O

LOAD CIRCUIT

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

NOTES: A.C L includes probe and jig capacitance.

B.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2 ns, t f ≤ 2 ns.

C.t PLH and t PHL are the same as t pd .

PARI/O of Second

ALVCH16903

From Output Under Test

LOAD CIRCUIT

R = 10 ?

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

NOTES: A.C L includes probe and jig capacitance.

B.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2 ns, t f ≤ 2 ns.

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

V CC =2.5V ±0.2V

Figure 2.Load Circuit and Voltage Waveforms

Figure 3.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION

V OH

V OL

From Output Under Test

C L LOA

D CIRCUIT

Open

Output Control (low-level enabling)

Output Waveform 1S1 at 6 V (see Note B)

Output Waveform 2S1 at GND (see Nte B)

0 V

2.7 V

0 V

2.7 V

0 V

2.7 V

3 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS PULSE DURATION

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES

Timing Input

Data Input

Input

t pd t PLZ /t PZL t PHZ /t PZH

Open 6 V GND

TEST S1NOTES: A.C L includes probe and jig capacitance.

B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

D.The outputs are measured one at a time, with one transition per measurement.

E.t PLZ and t PHZ are the same as t dis .

F.t PZL and t PZH are the same as t en .

G.t PLH and t PHL are the same as t pd .

H.t PHL is measured at 1.5 V.

I.t PLH is measured at V OL + 0.3 V.

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

V CC =2.7V AND 3.3V ±0.3V

Figure 4.Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION

From Output Under Test

PARI/O

LOAD CIRCUIT

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

NOTES: A.C L includes probe and jig capacitance.

B.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

C.t PLH and t PHL are the same as t pd .

PARI/O of Second

ALVCH16903

From Output Under Test

LOAD CIRCUIT

R = 10 ?

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

NOTES: A.C L includes probe and jig capacitance.

B.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 ?, t r ≤ 2.5 ns, t f ≤ 2.5 ns.

SN74ALVCH16903

3.3-V 12-BIT UNIVERSAL BUS DRIVER

WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS

SCES095D–MARCH 1997–REVISED SEPTEMBER 2004

V CC =2.7V AND 3.3V ±0.3V

Figure 5.Load Circuit and Voltage Waveforms

Figure 6.Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)

Lead/Ball Finish MSL Peak Temp (3)74ALVCH16903DGGRE4ACTIVE TSSOP DGG 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH16903DGGRG4ACTIVE TSSOP DGG 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH16903DGVRE4ACTIVE TVSOP DGV 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74ALVCH16903DLG4ACTIVE SSOP DL 5620

Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 74ALVCH16903DLRG4ACTIVE SSOP DL 561000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16903DGGR ACTIVE TSSOP DGG 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16903DGVR ACTIVE TVSOP DGV 562000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16903DL ACTIVE SSOP DL 5620

Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16903DLR

ACTIVE

SSOP

1000Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.

(2)

Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check https://www.wendangku.net/doc/0812550184.html,/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based

flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)

MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

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6-Dec-2006

Addendum-Page 1

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Low Power Wireless https://www.wendangku.net/doc/0812550184.html,/lpw Telephony https://www.wendangku.net/doc/0812550184.html,/telephony

Video & Imaging https://www.wendangku.net/doc/0812550184.html,/video

Wireless https://www.wendangku.net/doc/0812550184.html,/wireless

Mailing Address:Texas Instruments

Post Office Box 655303 Dallas, Texas 75265