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ZL50019GAG2中文资料

ZL50019GAG2中文资料
ZL50019GAG2中文资料

1

Features

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2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 and 16.384Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384Mbps ?32 serial TDM input, 32 serial TDM output streams

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Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 4E specifications

?Output clocks have less than 1ns of jitter (except for the 1.544MHz output)

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DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs

?Exceptional input clock cycle to cycle variation tolerance (20ns for all rates)

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Output streams can be configured as bi-directional for connection to backplanes

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Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384Mbps. Input and output data rates can differ ?Per-stream high impedance control outputs (STOHZ) for 16 output streams

?Per-stream input bit delay with flexible sampling point selection

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Per-stream output bit and fractional bit advancement

November 2006

Ordering Information

ZL50019GAC 256 Ball PBGA Trays ZL50019QCC 256 Lead LQFP Trays

ZL50019QCG1256 Lead LQFP*Trays, Bake &

Drypack

ZL50019GAG2256 Ball PBGA**Trays, Bake &

Drypack

*Pb Free Matte Tin

**Pb Free Tin/Silver/Copper

-40°C to +85°C

ZL50019

Enhanced 2K Digital Switch with

Stratum 4E DPLL

Data Sheet

Figure 1 - ZL50019 Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

?Per-channel ITU-T G.711 PCM A-Law/μ-Law Translation

?Four frame pulse and six reference clock outputs

?Three programmable delayed frame pulse outputs

?Input clock: 4.096MHz, 8.192MHz, 16.384MHz

?Input frame pulses: 61ns, 122ns, 244ns

?Per-channel constant or variable throughput delay for frame integrity and low latency applications ?Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151

?Per-channel high impedance output control

?Per-channel message mode

?Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses

?Connection memory block programming

?Supports ST-BUS and GCI-Bus standards for input and output timing

?IEEE-1149.1 (JTAG) test port

? 3.3V I/O with 5V tolerant inputs; 1.8V core voltage

Applications

?PBX and IP-PBX

?Small and medium digital switching platforms

?Remote access servers and concentrators

?Wireless base stations and controllers

?Multi service access platforms

?Digital Loop Carriers

?Computer Telephony Integration

Description

The ZL50019 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64kbps and Nx64kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048, 4.096, 8.192 or 16.384Mbps. The ZL50019 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored.

The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state.

When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external 20.000MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input reference signals (which can be 8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz or 19.44MHz provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter attenuation. The jitter attenuation function exceeds the Stratum 4E specification.

The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors.

The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1 External High Impedance Control, STOHZ0 - 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

5.0 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.0 Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

7.0 Data Input Delay and Data Output Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

7.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

7.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

7.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

7.5 External High Impedance Control Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

8.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

8.1 Variable Delay Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

8.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

9.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

10.0 Connection Memory Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

10.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

11.0 Device Operation in Master Mode and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

11.1 Master Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

11.2 Divided Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11.3 Multiplied Slave Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12.0 Overall Operation of the DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12.1 DPLL Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12.1.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12.1.3 Automatic Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12.1.3.1 Automatic Reference Switching Without Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

12.1.3.2 Automatic Reference Switching With Preference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

12.1.4 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

12.1.5 DPLL Internal Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.0 DPLL Frequency Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.1 Input Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.2 Input Frequencies Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13.3 Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

13.4 Pull-In/Hold-In Range (also called Locking Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

14.0 Jitter Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

14.1 Input Clock Cycle to Cycle Timing Variation Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

14.2 Input Jitter Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

14.3 Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

15.0 DPLL Specific Functions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

15.1 Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

15.2 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

15.3 Phase Alignment Speed (Phase Slope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

15.4 Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

15.5 Single Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

15.6 Multiple Period Reference Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

16.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

17.0 Device Reset and Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

17.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

17.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

17.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

18.0 Pseudo Random Bit Generation and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

19.0 PCM A-law/m-law Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

20.0 Quadrant Frame Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

21.0 JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

21.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

21.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

21.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

21.4 BSDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

22.0 Register Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

23.0 Detailed Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

24.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

24.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

24.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

24.3 Connection Memory High (CM_H) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

25.0 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

25.1 OSCi Master Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

25.1.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

25.1.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

26.0 DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

27.0 AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 1 - ZL50019 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50019 256-Ball 17mm x 17mm PBGA (as viewed through top of package). . . . . . . . . . . . . . . . . . 11 Figure 3 - ZL50019 256-Lead 28mm x 28mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7 - Output Timing for CKo0 and FPo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 8 - Output Timing for CKo1 and FPo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 9 - Output Timing for CKo2 and FPo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=”11” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11 - Output Timing for CKo4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 13 - Input Bit Delay Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 14 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 15 - Input Bit Delay and Factional Sampling Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 18 - Channel Switching External High Impedance Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 19 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 20 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 21 - Automatic Reference Switching State Diagram with No Preferred Reference . . . . . . . . . . . . . . . . . . 39 Figure 22 - Automatic Reference Switching State Diagrams with Preferred Reference . . . . . . . . . . . . . . . . . . . . 41 Figure 23 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 24 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 25 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 26 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 27 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 28 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 29 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 30 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 31 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 32 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 33 - ST-BUS Input Timing Diagram when Operated at 2Mbps, 4Mbps, 8Mbps. . . . . . . . . . . . . . . . . . . 101 Figure 34 - ST-BUS Input Timing Diagram when Operated at 16Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 35 - GCI-Bus Input Timing Diagram when Operated at 2Mbps, 4Mbps, 8Mbps . . . . . . . . . . . . . . . . . . 102 Figure 36 - GCI-Bus Input Timing Diagram when Operated at 16Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 37 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16Mbps . . . . . . . . . . . . . . . . . . . . . . 104 Figure 38 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16Mbps. . . . . . . . . . . . . . . . . . . . . . 105 Figure 39 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 40 - Output Drive Enable (ODE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 41 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 42 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 43 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 44 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 45 - FPo3 and CKo3 (32.768MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 46 - FPo4 and CKo4 Timing Diagram (1.544/2.048MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 47 - CKo5 Timing Diagram (19.44MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 48 - REF0 - 3 Reference Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 49 - Output Timing (ST-BUS Format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 1 - CKi and FPi Configurations for Master and Divided Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 2 - CKi and FPi Configurations for Multiplied Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3 - Output Timing Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6 - Connection Memory High After Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 7 - ZL50019 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 8 - Preferred Reference Selection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 9 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 10 - Generated Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 12 - Multi-Period Hysteresis Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 11 - Values for Single Period Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 13 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 14 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 15 - Quadrant Frame Bit Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 16 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 17 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 18 - Internal Mode Selection Register (IMS) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 19 - Software Reset Register (SRR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 20 - Output Clock and Frame Pulse Control Register (OCFCR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 22 - FPo_OFF[n] Register (FPo_OFF[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 23 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 24 - BER Error Flag Register 0 (BERFR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 25 - BER Error Flag Register 1 (BERFR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 26 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 27 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 28 - DPLL Control Register (DPLLCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 29 - Reference Frequency Register (RFR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 30 - Centre Frequency Register - Lower 16 Bits (CFRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 31 - Centre Frequency Register - Upper 10 Bits (CFRU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 32 - Frequency Offset Register (FOR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 33 - Lock Detector Threshold Register (LDTR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 34 - Lock Detector Interval Register (LDIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 35 - Slew Rate Limit Register (SRLR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 36 - Reference Change Control Register (RCCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 37 - Reference Change Status Register (RCSR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 38 - Interrupt Register (IR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 39 - Interrupt Mask Register (IMR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 40 - Interrupt Clear Register (ICR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 41 - Reference Failure Status Register (RSR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 42 - Reference Mask Register (RMR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 43 - Reference Frequency Status Register (RFSR) Bits - Read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 44 - Output Jitter Control Register (OJCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 45 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 46 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 47 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 48 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 49 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 50 - BER Receiver Control Register [n] (BRCR[n]) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 51 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 52 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 54 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 55 - Connection Memory High (CM_H) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Changes Summary

The following table captures the changes from January 2006 to November 2006.

The following table captures the changes from the October 2004 issue.

Page Item

Change

1

Updated Ordering Information.

Page Item

Change

38, 70, 71

12.1, “DPLL Timing Modes“ on page 38RCCR Register bits “FDM1 - 0” on page 70RCSR Register bits “DPM1 - 0” on page 71

?

The on-chip DPLL’s normal, holdover, automatic, and freerun modes are now collectively referred to as DPLL timing modes instead of operation modes. This change is to avoid confusion with the two main device operating modes; the master and slave modes.

39

12.1.3.1, “Automatic Reference Switching Without Preferences“ on page 39 and 12.1.3.2, “Automatic Reference Switching With Preference“ on page 40?

Section 12.1.3.1 and Section 12.1.3.2 added to clarify the DPLL’s automatic reference switching with and without preference operations in Automatic Timing Mode.67Table 33, Lock Detector Threshold Register (LDTR) Bits

?Clarified threshold calculations.

69

Table 36, “Reference Change Control

Register (RCCR) Bits” Bits “PRS1 - 0“ and Bits “PMS2 - 0“

?

Added description to clarify that only two consecutive references can be used in automatic timing mode with a preferred reference.

1.0 Pinout Diagrams

1.1 BGA Pinout

Figure 2 - ZL50019 256-Ball 17mm x 17mm PBGA (as viewed through top of package)

1

2345678910111213141516

A

V SS STi29STi28STi27STi25STi26STi24NC NC STio22STio23STio21STio20NC NC V SS A

B STi31

STi10STi5STi4CKo2STi0CKo0REF2V DD_ COREA FPi CKi IC_OPEN IC_OPEN OSCi ODE STio19B

C STi30

STi9V SS STi7STi6STi1CKo1REF_FAIL2V SS IC_OPEN IC_OPEN OSCo IC_GND V SS STio15STio18C

D STi17

STi11V DD_IO STi3STi2CKo4REF3REF1REF_FAIL0V SS FPo_OFF1OSC_EN STio13V DD_IO STio14STio16D

E

STi16STi14STi8V DD_IO V SS V DD_

CORE

REF_FAIL3REF_FAIL1REF0NC V DD_

CORE

V SS V DD_IO STio12FPo2STio17

E

F

STi19

STi15STi12STi13V DD_IO V DD_ CORE V DD_ CORE V SS V SS V DD_ CORE V DD_ CORE V DD_IO IC_OPEN FPo3FPo_OFF2STOHZ15F G STi18

RESET IC_GND IC_OPEN TDo V DD_IO V SS V SS V SS V SS V DD_IO A12A13FPo1FPo0STOHZ14G H STi21

V SS V SS V DD_ COREA CKo5V SS V SS V SS V SS V SS A7A9A10FPo_OFF0A11STOHZ12H J STi20V DD_IOA V DD_IOA V SS V SS CKo3V SS V SS V SS V SS A3A4A5A8A6STOHZ13J K

STi22V SS TMS V SS V DD_

COREA

V DD_IO V SS V SS V SS V SS V DD_IO IC_OPEN A0A2A1STOHZ11K L

STi23

V DD_ COREA TRST TCK V DD_IO V DD_ CORE V DD_ CORE V SS V SS V DD_ CORE V DD_ CORE V DD_IO STio10STio11STio9STOHZ10L M STio25

NC TDi D0V SS V DD_

CORE

V DD_

CORE

D6D10V DD_

CORE

V DD_

CORE

V SS MOT _INTEL MODE_4M0STio8STOHZ9M N STio24NC V DD_IO STio0STOHZ3D1D5D7D11D13R/W _WR DTA_RDY

STio4

V DD_IO STOHZ5STOHZ8N

P STio26NC V SS STio1STio3STOHZ1D3D8D14IRQ STio5STOHZ4STOHZ6V SS STOHZ7NC P

R STio27

NC STOHZ0STio2STOHZ2D2D4D9D12D15CS DS_RD MODE_4M1STio6STio7NC R

T

V SS STio28

STio29

STio31

STio30

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

V SS T

1

23456789101112131415

16

Note: A1 corner identified by metallized marking.

Note: Pinout is shown as viewed through top of package.

1.2 QFP Pinout

Figure 3 - ZL50019 256-Lead 28mm x 28mm LQFP (top view)

15215415615816016216416616817017217417617818022

24

26

28

3020

18

16

14

12

10

8

6

4

2

12010210410610811011411611811252

54

56

5860

50

48

46

44

42

40

38

36

34

32

1008284868890949698928066

687074767872132134136138140142144146148150C K i F P i I C _O P E N I C _O P E N I C _O P E N I C _O P E N O S C o O S C i V D D _I O V S S I C _G N D O D E V D D _I O S T i o _23S T i o _22S T i o _21S T i o _20

62

64

122124126128

182184186188190S T i 25S T i 24V S S V D D _I O S T i _7S T i _6S T i _3S T i _2S T i _1S T i _0C K o 4V S S R E F _F A I L 2R E F 2R E F _F A I L 1R E F 1R E F _F A I L 0R E F 0V S S S T i 27S T i 26S T i _5S T i _4V D D _I O C K o 2C K o 1V S S V D D _C O R E C K o 0V S S V D D _I O R E F _F A I L 3R E F 3V S S V D D _C O R E A STi_22VDD_IO STi_23STi_21STi_20STi_19STi_18STi_17VDD_IO

TRST TCK TMS VSS VDD_CORE

VSS

VDD_COREA

VSS

VSS CKo3VDD_IOA

VDD_COREA

VSS

VSS CKo5VDD_IOA

VSS VDD_COREA

VSS

VSS VDD_CORE

TDo

RESET IC_OPEN IC_GND

VSS VDD_IO STi_15STi_14STi_11STi_10STi_9STi_8STi30STi31STi_16VSS TDi STi29VDD_IO STi28202220218216214212208206204210222240238236234232228226224230242256

254252248246244250200198196194VSS STi_13STi_12S T i o _28S T i o _29S T i o _30S T i o _31V D D _I O V S S S T i o _0S T i o _1S T i o _2S T i o _3S T O H Z _0S T O H Z _1S T O H Z _2S T O H Z _3V D D _I O V S S D 0V D D _C O R E V S S D 1D 2D 3D 4D 5D 7D 8D 9D 6V D D _I O V S S D 10V D D _C O R E

V S S D 11D 12

D 13D 14D 15R /W _W R C S M O T _I N T

E L D S _R D I R Q D T A _R D Y M O D E _4M 0V D D _C O R E V S S M O D E _4M 1V D D _I O V S S S T i o _4S T i o _5S T i o _6S T i o _7S T O H Z _4S T O H Z _5

S T O H Z _6

S T O H Z _7

V D D _I O

V S S N C NC

NC NC NC VDD_IO VSS STio_8STio_9STio_10STio_11STOHZ_8STOHZ_9STOHZ_10STOHZ_11VDD_IO IC_OPEN VSS

VDD_CORE VSS A0A1

A2A3A4A7A6A5A11

A10A9A8VDD_CORE VSS A13A12IC_OPEN VDD_IO VSS FPo_OFF0FPo0FPo_OFF1FPo1FPo2

FPo_OFF2FPo3VDD_CORE VSS OSC_EN VDD_IO VSS STio_12STio_13STio_14STio_15STOHZ_12STOHZ_13STOHZ_14STOHZ_15VDD_IO VSS

STio_16STio_17STio_18STio_19N C N C N C N C N C N C N C V S S V D D _C O R E V S S V S S V D D _I O STio_27

STio_24STio_25STio_26

VSS NC NC NC 192130

NC NC NC N C N C N C

2.0 Pin Description

PBGA Pin Number LQFP Pin

Number

Pin Name Description

E6, E11, F6, F7, F10, F11, L6, L7, L10, L11, M6, M7, M10, M11

19, 33,

45, 83,

95, 109,

146, 173,

213, 233

V DD_CORE Power Supply for the core logic: +1.8V

H4, K5, B9,

L2217, 231,

157, 224

V DD_COREA Power Supply for analog circuitry: +1.8V

D3, D14, E4, E13, F5, F12, G6, G11, K6, K11, L5, L12, N3,

N145, 15, 29,

49, 57,

69, 79,

101, 113,

121, 133,

143, 160,

169, 177,

186, 195,

207, 241,

249

V DD_IO Power Supply for I/O: +3.3V

J2, J3220, 226V DD_IOA Power Supply for the CKo5 and CKo3 outputs: +3.3V

A1, A16, C3, C9, C14, D10, E5, E12, F8, F9, G7, G8, G9, G10, H2, H3, H6, H7,

H8, H9, H10, J4, J5, J7, J8, J9, J10, K2, K4, K7, K8, K9, K10, L8, L9, M5, M12, P3, P14, T1,

T168, 17, 21,

31, 35,

47, 50,

60, 71,

81, 85,

97, 103,

111, 114,

123, 142,

145, 147,

156, 158,

162, 171,

175, 178,

188, 199,

209, 214,

216, 218,

222, 223,

228, 230,

232, 235,

242, 251

V SS Ground

K3234TMS Test Mode Select (5V-Tolerant Input with Internal Pull-up)

JTAG signal that controls the state transitions of the TAP controller.

This pin is pulled high by an internal pull-up resistor when it is not

driven.

L4238TCK Test Clock (5V-Tolerant Schmitt-Triggered Input with Internal

Pull-up)

Provides the clock to the JTAG test logic.

L3239TRST Test Reset (5V-Tolerant Input with Internal Pull-up)

Asynchronously initializes the JTAG TAP controller by putting it in

the Test-Logic-Reset state. This pin should be pulsed low during

power-up to ensure that the device is in the normal functional

mode. When JTAG is not being used, this pin should be pulled low

during normal operation.

M3240TDi Test Serial Data In (5V-Tolerant Input with Internal Pull-up)

JTAG serial test instructions and data are shifted in on this pin.

This pin is pulled high by an internal pull-up resistor when it is not

driven.

G5212TDo Test Serial Data Out (5V-Tolerant Three-state Output)

JTAG serial data is output on this pin on the falling edge of TCK.

This pin is held in high impedance state when JTAG is not

enabled.

B12, B13, C10, C11, F13, G4,

K12

80, 105,

150, 151,

152, 153,

210

IC_OPEN Internal Test Mode (5V-Tolerant Input with Internal Pull-down)

These pins may be left unconnected.

C13, G3144, 208IC_GND Internal Test Mode Enable (5V-Tolerant Input)

These pins MUST be low.

A8, A9, A14, A15, E10, M2, N2, P2, P16, R2, R16, T6, T7, T8, T9, T10, T11, T12, T13, T14,

T15

61, 62,

63, 64,

65, 66,

67, 68,

134, 135,

136, 137,

138, 139,

140, 215,

219, 225,

229, 236,

237

NC No Connect

These pins MUST be left unconnected.

Number Number

Pin Name Description

M14, R1346, 48MODE_4M0,

MODE_4M14M Input Clock Mode 0 to 1 (5V-Tolerant Input with internal pull-down)

These two pins should be tied together and are typically used to select CKi = 4.096MHz operation. See Table7, “ZL50019 Operating Modes” on page37 for a detailed explanation.

See Table17, “Control Register (CR) Bits” on page53 for CKi and FPi selection using the CKIN1 - 0 bits.

D12107OSC_EN Oscillator Enable (5V-Tolerant Input with Internal Pull-down) If

tied high, this pin indicates that there is a 20MHz external

oscillator interfacing with the device. If tied low, there is no

oscillator and CKi will be used for master clock generation.

If the device is in master mode, an external oscillator is required

and this pin MUST be tied high.

C12149OSCo Oscillator Clock Output (3.3V Output)

If OSC_EN = ‘1’, this pin should be connected to a 20MHz crystal

(see Figure23 on page90) or left unconnected if a clock oscillator

is connected to OSCi pin under normal operation (see Figure24

on page91). If OSC_EN = 0, this pin MUST be left unconnected. B14148OSCi Oscillator Clock Input (3.3V Input)

If OSC_EN = ‘1’, this pin should be connected to a 20MHz crystal

(see Figure23 on page90) or to a clock oscillator under normal

operation (see Figure24 on page91). If OSC_EN = 0, this pin

MUST be driven high or low by connecting either to V DD_IO or to

ground.

E9, D8, B8,

D7161, 164,

166, 168

REF0 - 3 DPLL Reference Inputs 0 to 3 (5V-Tolerant Schmitt-Triggered

Inputs)

If the device is in Master mode, these input pins accept 8kHz,

1.544MHz,

2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz or

19.44MHz timing references independently. One of these inputs is

defined as the preferred or forced input reference for the DPLL.

The Reference Change Control Register (RCCR) selects the

control of the preferred reference.These pins are ignored if the

device is in slave mode unless SLV_DPLLEN (bit 13) in the

Control Register (CR) is set. When these input pins are not in use,

they MUST be driven high or low by connecting either to V DD_IO or

to ground.

D9, E8, C8,

E7159, 163,

165, 167

REF_FAIL0 - 3Failure Indication for DPLL References 0 to 3 (5V-Tolerant

Three-state Outputs)

These output pins are used to indicate input reference failure when

the device is in master mode.

If REF0 fails, REF_FAIL0 will be driven high.

If REF1 fails, REF_FAIL1 will be driven high.

If REF2 fails, REF_FAIL2 will be driven high.

If REF3 fails, REF_FAIL3 will be driven high.

If the device is in slave mode, these pins are driven low, unless

SLV_DPLLEN (bit 13) in the Control Register (CR) is set.

Number Number

Pin Name Description

G15, G14, E15, F14102, 106,

110, 112

FPo0 - 3ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5V-Tolerant

Three-state Outputs)

FPo0: 8kHz frame pulse corresponding to the 4.096MHz output

clock of CKo0.

FPo1: 8kHz frame pulse corresponding to the 8.192MHz output

clock of CKo1.

FPo2: 8kHz frame pulse corresponding to 16.384MHz output

clock of CKo2.

FPo3: Programmable 8kHz frame pulse corresponding to

4.096MHz, 8.192MHz, 16.384MHz, or 32.768MHz output clock

of CKo3.

In Divided Slave modes, the frame pulse width of FPo0 - 3 cannot

be narrower than the input frame pulse (FPi) width.

H14, D11100, 104FPo_OFF0 - 1Generated Offset Frame Pulse Outputs 0 to 1 (5V-Tolerant

Three-state Outputs)

Individually programmable 8kHz frame pulses, offset from the

output frame boundary by a programmable number of channels.

F15108FPo_OFF2

or

FPo5Generated Offset Frame Pulse Output 2 or 19.44MHz Frame Pulse Output (5V-Tolerant Three-state Output)

As FPo_OFF2, this is an individually programmable 8kHz frame pulse, offset from the output frame boundary by a programmable number of channels.

By programming the FP19EN (bit 10) of FPOFF2 register to high, this signal becomes FPo5, a non-offset frame pulse corresponding to the 19.44MHz clock presented on CKo5. FPo5 is only available in Master mode or when the SLV_DPLLEN bit in the Control Register is set high while the device is in one of the slave modes.

B7, C7, B5, J6, D6, H5170, 172,

174, 227,

176, 221

CKo0 - 5ST-BUS/GCI-Bus Clock Outputs 0 to 5 (5V-Tolerant

Three-state Outputs)

CKo0: 4.096MHz output clock.

CKo1: 8.192MHz output clock.

CKo2: 16.384MHz output clock.

CKo3: 4.096MHz, 8.192MHz, 16.384MHz or 32.768MHz

programmable output clock.

CKo4: 1.544MHz or 2.048MHz programmable output clock.

CKo5: 19.44MHz output clock.

See Section6.0 on page24 for details. In Divided Slave mode, the

frequency of CKo0 - 3 cannot be higher than input clock (CKi).

CKo4 and CKo5 are only available in Master mode or when the

SLV_DPLLEN bit in the Control Register is set high while the

device is in one of the slave modes.

Number Number

Pin Name Description

B10

155

FPi

ST-BUS/GCI-Bus Frame Pulse Input (5V-Tolerant Schmitt-Triggered Input)

This pin accepts the frame pulse which stays active for 61ns,122ns or 244ns at the frame boundary. The frame pulse frequency is 8kHz. The frame pulse associated with the highest input or output data rate must be applied to this pin when the device is operating in Divided Slave mode or Master mode. The exception is if the device is operating in Master mode with loopback (i.e., CKi_LP is set in the Control Register). In that case,this input must be tied high or low externally. When the device is operating in Multiplied Slave mode, the frame pulse associated with the highest input data rate must be applied to this pin. For all modes (except Master mode with loopback), if the data rate is 16.384Mbps, a 61ns wide frame pulse must be used. By default,the device accepts a negative frame pulse in ST-BUS format, but it can accept a positive frame pulse instead if the FPINP bit is set high in the Control Register (CR). It can accept a GCI-formatted frame pulse by programming the FPINPOS bit in the Control Register (CR) to high.

B11154CKi

ST-BUS/GCI-Bus Clock Input (5V-Tolerant Schmitt Triggered The Input)

This pin accepts a 4.096MHz, 8.192MHz or 16.384MHz clock. The clock frequency associated with twice the highest input or output data rate must be applied to this pin when the device is operating in either Divided Slave mode or Master mode. The exception is if the device is operating in Master mode with loopback (i.e., CKi_LP is set in the Control Register). In that case,this input must be tied high or low externally. The clock frequency associated with twice the highest input data rate must be applied to this pin when the device is operating in Multiplied Slave mode. In all modes of operation (except Master mode with loopback),when data is running at 16.384Mbps, a 16.384MHz clock must be used. By default, the clock falling edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the CKINP bit in the Control Register (CR).

Number Number Pin Name

Description

B6, C6, D5, D4, B4, B3, C5, C4, E3, C2, B2, D2, F3, F4, E2, F2, E1, D1, G1, F1, J1, H1, K1, L1, A7, A5, A6, A4, A3, A2, C1, B1179, 180,

181, 182,

183, 184,

185, 187,

198, 200,

201, 202,

203, 204,

205, 206,

243, 244,

245, 246,

247, 248,

250, 252,

189, 190,

191, 192,

193, 194,

196, 197

STi0 - 31Serial Input Streams 0 to 31 (5V-Tolerant Inputs with Enabled

Internal Pull-downs)

The data rate of each input stream can be selected independently

using the Stream Input Control Registers (SICR[n]). In the

2.048Mbps mode, these pins accept serial TDM data streams at

2.048Mbps with 32 channels per frame. In the 4.096Mbps mode,

these pins accept serial TDM data streams at 4.096Mbps with 64

channels per frame. In the 8.192Mbps mode, these pins accept

serial TDM data streams at8.192Mbps with 128 channels per

frame. In the 16.384Mbps mode, these pins accept TDM data

streams at 16.384Mbps with 256 channels per frame.

N4, P4, R4, P5, N13, P11, R14, R15, M15, L15, L13, L14, E14, D13, D15, C15, D16, E16, C16, B16, A13, A12, A10, A11, N1, M1, P1, R1, T2, T3, T5,

T4

6, 7, 9,

10, 51,

52, 53,

54, 70,

72, 73,

74, 115,

116, 117,

118, 125,

126, 127,

128, 129,

130, 131,

132, 253,

254, 255,

256, 1, 2,

3, 4

STio0 - 31Serial Output Streams 0 to 31 (5V-Tolerant Slew-Rate-Limited

Three-state I/Os with Enabled Internal Pull-downs)

The data rate of each output stream can be selected

independently using the Stream Output Control Registers

(SOCR[n]). In the 2.048Mbps mode, these pins output serial TDM

data streams at 2.048Mbps with 32 channels per frame. In the

4.096Mbps mode, these pins output serial TDM data streams at

4.096Mbps with 64 channels per frame. In the 8.192Mbps mode,

these pins output serial TDM data streams at 8.192Mbps with 128

channels per frame. In the 16.384Mbps mode, these pins output

serial TDM data streams at 16.384Mbps with 256 channels per

frame. These output streams can be used as bi-directionals by

programming BDH (bit 7) and BDL (bit 6) of Internal Mode

Selection (IMS) register.

R3, P6, R5, N5, P12, N15, P13, P15, N16, M16, L16, K16, H16, J16, G16,

F16

11, 12,

13, 14,

55, 56,

58, 59,

75, 76,

77, 78,

119, 120,

122, 124

STOHZ0 - 15Serial Output Streams High Impedance Control 0 to 15

(5V-Tolerant Slew-Rate-Limited Three-state Outputs)

These pins are used to enable (or disable) external three-state

buffers. When an output channel is in the high impedance state,

the STOHZ drives high for the duration of the corresponding output

channel. When the STio channel is active, the STOHZ drives low

for the duration of the corresponding output channel. STOHZ

outputs are available for STio0 - 157 only.

Number Number

Pin Name Description

B15141ODE Output Drive Enable (5V-Tolerant Input with Internal Pull-up)

This is the output enable control for STio0 - 31 and the

output-driven-high control for STOHZ0 - 15. When it is high, STio0

- 31 and STOHZ0 - 15 are enabled. When it is low, STio0 - 31 are

tristated and STOHZ0 - 15 are driven high.

M4, N6, R6, P7, R7, N7, M8, N8, P8, R8, M9, N9, R9, N10, P9,

R1016, 18,

20, 22,

23, 24,

25, 26,

27, 28,

30, 32,

34, 36,

37, 38

D0 - 15Data Bus 0 to 15 (5V-Tolerant Slew-Rate-Limited Three-state

I/Os)

These pins form the 16-bit data bus of the microprocessor port.

N1244DTA_RDY Data Transfer Acknowledgment_Ready (5V-Tolerant

Three-state Output)

This active low output indicates that a data bus transfer is

complete for the Motorola interface. For the Intel interface, it

indicates a transfer is completed when this pin goes from low to

high. An external pull-up resistor MUST hold this pin at HIGH level

for the Motorola mode. An external pull-down resistor MUST hold

this pin at LOW level for the Intel mode.

R1140CS Chip Select (5V-Tolerant Input)

Active low input used by the Motorola or Intel microprocessor to

enable the microprocessor port access.

N1139R/W_WR Read/Write_Write (5V-Tolerant Input)

This input controls the direction of the data bus lines (D0 - 15)

during a microprocessor access. For the Motorola interface, this

pin is set high and low for the read and write access respectively.

For the Intel interface, a write access is indicated when this pin

goes low.

R1242DS_RD Data Strobe_Read (5V-Tolerant Input)

This active low input works in conjunction with CS to enable the

microprocessor port read and write operations for the Motorola

interface. A read access is indicated when it goes low for the Intel

interface.

K13, K15, K14, J11, J12, J13, J15, H11, J14, H12, H13, H15, G12, G1382, 84,

86, 87,

88, 89,

90, 91,

92, 93,

94, 96,

98, 99

A0 - 13Address 0 to 13 (5V-Tolerant Inputs)

These pins form the 14-bit address bus to the internal memories

and registers.

Number Number

Pin Name Description

3.0 Device Overview

The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31).STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored. It is a non-blocking digital switch with 2048 64kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates of 2.048Mbps, 4.096Mbps, 8.192Mbps and 16.384Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs deliver serial data streams with data rates of 2.048Mbps, 4.096Mbps and, 8.192Mbps and 16.384Mbps on a per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external ST-BUS/GCI-Bus tristate drivers for the first sixteen ST-BUS/GCI-Bus outputs (STio0 -15). By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS/GCI-Bus devices.

The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The output data streams will be driven by and have their timing defined by FPi and CKi in Divided Slave mode. In Multiplied Slave mode, the output data streams will be driven by an internally generated clock, which is multiplied from CKi internally. In Master mode, the on-chip DPLL will drive the output data streams and provide output clocks and frame pulses. Refer to Application Note ZLAN-120 for further explanation of the different modes of operation.When the device is in Master mode, the DPLL is phase-locked to one of four DPLL reference signals, REF0 - 3,which are sourced by an external 8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz or 19.44MHz reference signal. The on-chip DPLL also offers jitter attenuation, reference switching, reference monitoring, freerun and holdover functions. The jitter performance exceeds the Stratum 4E specification. The intrinsic jitter of all output clocks is less than 1ns (except for the 1.544MHz output).

M13

41

MOT_INTEL

Motorola_Intel (5V-Tolerant Input with Enabled Internal Pull-up)

This pin selects the Motorola or Intel microprocessor interface to be connected to the device. When this pin is unconnected or

connected to high, Motorola interface is assumed. When this pin is connected to ground, Intel interface should be used.

P1043IRQ

Interrupt (5V-Tolerant Three-state Output)

This programmable active low output indicates that the internal operating status of the DPLL has changed. An external pull-up resistor MUST hold this pin at HIGH level.

G2211RESET

Device Reset (5V-Tolerant Input with Internal Pull-up)This input (active LOW) puts the device in its reset state that disables the STio0 - 31 drivers and drives the STOHZ0 - 15

outputs to high. It also preloads registers with default values and clears all internal counters. To ensure proper reset action, the reset pin must be low for longer than 1μs. Upon releasing the reset signal to the device, the first microprocessor access cannot take place for at least 600μs due to the time required to stabilize the device and the crystal oscillator from the power-down state. Refer to Section Section 17.2 on page 46 for details.

Number Number

Pin Name Description

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