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M463S0924ET1-C7A中文资料

SDRAM Unbuffered uSODIMM

144pin Unbuffered uSODIMM based on 128Mb E-die (x16)

64-bit Non ECC

Revision 1.1

May. 2003

Revision History

Revision 1.0 (Nov., 2002) - First release

Revision 1.1 (May, 2003) - Delete CL=2 @133MHz.

144Pi Unbuffered uSODIMM based on 128Mb E-die (x16)

Ordering Information

Part Number Density Organization Component Composition Interface M463S0924ET1-C(L)7A64MB8M x 648Mx16(K4S281632E) * 4EA LVTTL

Operating Frequencies

- 7A

Speed @CL3133MHz(7.5ns)

CL-tRCD-tRP 3 - 3 - 3

FEATURE

? Burst mode operation

? Auto & self refresh capability (4096 Cycles/64ms)

? LVTTL compatible inputs and outputs

? Single 3.3V ± 0.3V power supply

? MRS cycle with address key programs Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

? All inputs are sampled at the positive going edge of the system clock

? Serial presence detect with EEPROM

? PCB : Height (30mm) , double sided component

PIN CONFIGURATIONS (Front side/back side)

Pin 135791113151719212325272931333537394143454749

Front V SS DQ0DQ1DQ2DQ3V DD DQ4DQ5DQ6DQ7V SS DQM0DQM1V DD A0A1A2V SS DQ8DQ9DQ10DQ11V DD DQ12DQ13

Pin 2468101214161820222426283032343638404244464850

Back V SS DQ32DQ33DQ34DQ35V DD DQ36DQ37DQ38DQ39V SS DQM4DQM5V DD A3A4A5V SS DQ40DQ41DQ42DQ43V DD DQ44DQ45

Pin 5153555759

6163656769717375777981838587899193

Front DQ14DQ15V SS NC NC

CLK0V DD RAS WE CS0*CS1DU V SS NC NC V DD DQ16DQ17DQ18DQ19V SS DQ20

Pin 5254565860

6264666870727476788082848688909294

Back DQ46DQ47V SS NC NC

CKE0V DD CAS *CKE1*A12*A13*CLK1V SS NC NC V DD DQ48DQ49DQ50DQ51V SS DQ52

Pin 959799101103105107109111113115117119121123125127129131133135137139141143

Front DQ21DQ22DQ23V DD A6A8V SS A9A10/AP V DD DQM2DQM3V SS DQ24DQ25DQ26DQ27V DD DQ28DQ29DQ30DQ31V SS **SDA V DD

Pin 9698100102104106108110112114116118120122124126128130132134136138140142144

Back DQ53DQ54DQ55V DD A7BA0V SS BA1A11V DD DQM6DQM7V SS DQ56DQ57DQ58DQ59V DD DQ60DQ61DQ62DQ63V SS **SCL V DD

Voltage Key

* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

PIN NAMES

* These pins are not used in this module.** These pins should be NC in the system which does not support SPD.

Pin Name Function

Pin Name

Function

A0 ~ A11Address input (Multiplexed)

WE Write enable BA0 ~ BA1Select bank DQM0 ~ 7DQM

DQ0 ~ DQ63Data input/output V DD Power supply (3.3V)CLK0Clock input V SS Ground CKE0Clock enable input SDA Serial data I/O CS0Chip select input SCL Serial clock RAS Row address storbe DU Don ′t use CAS

Column address strobe

No connection

PIN CONFIGURATION DESCRIPTION

Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs.

CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM

CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby.

CKE should be enabled 1CLK+t SS prior to valid command.

A0 ~ A11Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8

BA0 ~ BA1Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.

RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.

CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access.

WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active.

DQM0 ~ 7Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking)

DQ0 ~ 63Data input/output Data inputs/outputs are multiplexed on the same pins.

V DD/V SS Power supply/ground Power and ground for the input buffers and the core logic.

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN, V OUT-1.0 ~ 4.6V Voltage on V DD supply relative to Vss V DD, V DDQ-1.0 ~ 4.6V Storage temperature T STG-55 ~ +150°C Power dissipation P D4W Short circuit current I OS50mA Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note Supply voltage V DD 3.0 3.3 3.6V

Input high voltage V IH 2.0 3.0V DDQ+0.3V 1 Input low voltage V IL-0.300.8V2 Output high voltage V OH 2.4--V I OH = -2mA Output low voltage V OL--0.4V I OL = 2mA Input leakage current I LI-10-10uA3

1. V IH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ V IN ≤ V DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF = 1.4V ± 200mV)

Parameter Symbol Min Max Unit

Input capacitance (A0 ~ A11, BA0 ~ BA1) Input capacitance (RAS, CAS, WE)

Input capacitance (CKE0)

Input capacitance (CLK0)

Input capacitance (CS0)

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63)C IN1

C IN2

C IN3

C IN4

C IN5

C IN6

C OUT

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)

Parameter

Sym-bol

Test Condition

Version Unit

Note

-7A Operating current (One bank active)

I CC1Burst length = 1t RC ≥ t RC (min)I O = 0 mA

400mA 1

Precharge standby current in power-down mode

I CC2P CKE ≤ V IL (max), t CC = 10ns 8mA

I CC2PS CKE & CLK ≤ V IL (max), t CC =∞

8Precharge standby current in non power-down mode

I CC2N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns

Input signals are changed one time during 20ns 80

I CC2NS CKE ≥ V IH (min), CLK ≤ V IL (max), t CC =∞Input signals are stable 40Active standby current in power-down mode

I CC3P CKE ≤ V IL (max), t CC = 10ns 20mA

I CC3PS CKE & CLK ≤ V IL (max), t CC =∞

20Active standby current in non power-down mode (One bank active)

I CC3N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns

Input signals are changed one time during 20ns 120mA I CC3NS

CKE ≥ V IH (min), CLK ≤ V IL (max), t CC =∞Input signals are stable 100

Operating current (Burst mode)I CC4I O = 0 mA Page burst

4Banks activated t CCD = 2CLKs 560mA 1

Refresh current I CC5t RC ≥ t RC (min)800mA 2

Self refresh current I CC6

CKE ≤ 0.2V

C 8mA L

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noted, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ )

Notes :

M463S0924ET1(64MB, 8Mx64 Module)

3.3V 1200?

870?

Output

50pF

V OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mA

Vtt = 1.4V

50?

Output

50pF

Z0 = 50?

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)

Parameter

Value Unit AC input levels (Vih/Vil)

2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall time

tr/tf = 1/1ns Output timing measurement reference level 1.4V

Output load condition

See Fig. 2

OPERATING AC PARAMETER

Notes :(AC operating conditions unless otherwise noted)

Parameter

Symbol Version Unit Note - 7A Row active to row active delay t RRD (min)15ns 1RAS to CAS delay t RCD (min)20ns 1Row precharge time t RP (min)20ns 1Row active time t RAS (min)45ns 1

t RAS (max)100us Row cycle time

t RC (min)65ns 1Last data in to row precharge t RDL (min)2CLK 2Last data in to Active delay

t DAL (min) 2 CLK + tRP

-Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stop

t BDL (min)1CLK 2Col. address to col. address delay t CCD (min)

1CLK 3Number of valid output data

CAS latency=32ea

4CAS latency=2

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter

Symbol

- 7A

Unit

Note

Min Max CLK cycle time CAS latency=3t CC 7.51000ns 1

CAS latency=210

CLK to valid output delay CAS latency=3t SAC 5.4ns 1,2

CAS latency=26

Output data hold time

CAS latency=3t OH 3ns 2CAS latency=2

3CLK high pulse width t CH 2.5ns 3CLK low pulse width t CL 2.5ns 3Input setup time t SS 1.5ns 3Input hold time t SH 0.8ns 3CLK to output in Low-Z t SLZ 1

ns 2

CLK to output in Hi-Z

CAS latency=3t SHZ

5.4ns

CAS latency=2

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

RAS

CAS

DQM

BA 0,1

A 10/AP

A 0 ~ A 9, A 11

Note

Mode register set H X L L L L X OP code

1,2Refresh

Auto refresh

H L L L H X

3Self refresh

Entry

L 3Exit

L H L H H H X X

3H X X X 3

Bank active & row addr.H X L L H H X V Row address Read &

column address Auto precharge disable H

L Column address (A 0 ~ A 8)4Auto precharge enable H 4,5Write &

column address Auto precharge disable H X L H L L X V

L Column address (A 0 ~ A 8)

4Auto precharge enable

H 4,5Burst stop H X L H H L X X

Precharge

Bank selection H

L L H L X

V L X

All banks

Clock suspend or active power down

Entry H L H X X X X X

L V V V Exit L H X X X X X Precharge power down mode

Entry

H X X X X

L H H H Exit

L H

H X X X X L

V V

DQM

H V

X 7

No operation command

H X X X X

1. OP Code : Operand code

A 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.

If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Notes :X