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PDSP16510中文资料

PDSP16116/A/MC

Ordering Information

PDSP16116 MC GC1R 10MHz MIL-883 screened -ceramic QFP

PDSP16116 MC AC1R

10MHz

MIL-883 screened -PGA package

PDSP16116A MC GC1R 20MHz MIL-883 screened -ceramic QFP

PDSP16116A MC AC1R 20MHz

MIL-883 screened -PGA package

PDSP16116/A/MC

16 by 16 Bit Complex Multiplier

DS3858ISSUE 3.0June 2000

Fig.1 Simplified Block Diagram

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.

The PDSP16116/A contains four 16 x 16 Array Multipliers,two 32 bit Adder/Subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. In combination with a PDSP16318, the PDSP16116A forms a two chip 10MHz Complex Multiplier Accumulator with 20 bit accumulator registers and output shifters. The PDSP16116 in combination with two PDSP16318s and two PDSP1601s forms a complete 10MHz Radix 2 DIT FFT Butterfly solution which fully supports Block Floating Point Arithmetic. The PDSP16116/A has an extremely high throughput that is suited to recursive algorithms as all calculations are performed with a single pipeline delay (two cycle fall-through).

FEATURES

s Complex Number (16 + 16) X (16 + 16) Multiplication s Full 32 bit Result s 20MHz Clock Rate

s Block Floating Point FFT Butterfly Support s -1 times -1 Trap

s Two's Complement Fractional Arithmetic s TTL Compatible I/O s Complex Conjugation s 2 Cycle Fall Through

144 pin PGA or QFP packages

APPLICATION

ASSOCIATED PRODUCTS

PDSP16318/A Complex Accumulator

PDSP16112/A (16 + 16) X (12 + 12) Complex Multiplier PDSP16330/A Pythagoras Processor PDSP1601/A ALU and Barrel Shifter PDSP16350Precision Digital Modulator PDSP16256Programmable FIR Filter PDSP16510

Single Chip FFT Processor

s Fast Fourier Transforms s Digital Filtering

s Radar and Sonar Processing s Instrumentation s

Image Processing

CHANGE NOTIFICATION

The change notification requirements of MIL-M-38510 will be implemented on this device type. Known customers will be notified of any changes since last buy when ordering further parts if significant changes have been made.Rev A

C D

Date

JULY 1993 OCT 1998 JUN 2000

PDSP16116/A/MC

2Signal

XR15:0

XI15:0

YR15:0

YI15:0

PR15:0

PI15:0

CLK

CEX

CEY

CONX

CONY

ROUND

MBFP

SOBFP

EOPSS

AR15:13

AI15:13

WTA1:0

WTB1:0

WTOUT1:0

SFTA1:0

SFTR2:0

GWR4:0

OSEL1:0

OER, OEI

VDD

GND

The PDSP16116 has a number of features tailored for

System applications.

-1 x -1 Trap

In multiply operations utilising Twos Complement Fractional notation, the -1 x -1 operation forms an invalid result as +1 is not representable in the fractional number range. The PDSP16116/A eliminates this problem by trapping the

-1 x -1 operation and forcing the Multiplier result to become the most positive representable number.

Complex Conjugation

Many algorithms utilising complex arithmetic require conjugation of complex data stream. This operation has traditionally required an adiditional ALU to multiply the imaginary component by -1. The PDSP16116 eliminates the requirement for the extra ALU by offering on chip complex conjugation of either of the two incoming complex data words with no loss in throughput.

Easy Interfacing

As with all PDSP family members the PDSP16116 has registered I/O for data and control. Data inputs have independent clock enables and data outputs have independent three state output enables.

Type INPUT INPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT POWER POWER Description

16 bit input for real x data

16 bit input for imag x data

16 bit input for reaal y data

16 bit input for imag y data

16 bit output for real p data

16 bit output for img p data

Clock, new data is loaded on rising edge of CLK

Clock, enable X-port input register

Clock, enable Y-port input register

Conjugate X data

Conjugate Y data

Rounds the real & imag results

Mode select (BFP/Normal)

Start of BFP operations **

End of pass **

3 MSB's from real part of A-word **

3 MSB's from imag part of A-word **

Word tag from A-word

Word tag from B-word / shift control *

Word tag output **

Shift control for A-word / overflow flag *

Shift control for accumulator resul **

Global weighting register contents **

Selects the desired output configuration

Output enables

+5V Supply All supply pins

0V Supply must be connected

Normal mode Configuration

Tie Low

*Indicates pin performs different functions in BFP / Normal modes.

**Indicates pin is used only in BFP mode

Table.1 Signal Descriptions

PDSP16116/A/MC

Figure 2 - Block Diagram

PDSP16116/A/MC

Figure 3 Pin connection diagrams (not to scale). 4

PDSP16116/A/MC

Figure 3A - Pin connections for AC144 (Power) and GC144 packages

Signal V DD GND PR13PR12PR11PR10PR9PR8PR7PR6PR5GND V DD PR4PR3PR2PR1PR0PI0PI1PI2PI3PI4V DD PI5GND PI6PI7PI8PI9PI10PI11PI12PI13GND V DD

GC 123456789101112131415161718192021222324252627282930313233343536

Signal PI14PI15WTOUT1WTOUT0SFTR0SFTR1SFTR2OEI

CONX CONY ROUND AI13AI14AI15AR13AR14AR15YI15YI14YI13YI12YI11YI10YI9YI8YI7YI6YI5YI4YI3YI2YI1YI0XI0GND V DD

AC D3C2B1D2E3C1E2D1F2F3E1G2G3F1G1H2H1H3J3J1K1J2K2K3L1L2M1N1M2L3N2P1M3N3B2A1

GC 373839404142434445464748495051525354555657585960616263646566676869707172

Signal XI1XI2XI3XI4XI5XI6XI7XI8XI9XI10XI11XI12XI13XI14XI15CEY CEX

XR15XR14XR13XR12XR11XR10XR9XR8XR7XR6XR5XR4XR3XR2XR1XR0YR15YR14YR13

AC N4P3R2P4N5R3P5R4N6P6R5P7N7R6R7P8R8N8N9R9R10P9P10N10R11P11R12R13P12N11P13R14N12N13P14R15

GC 737475767778798081828384858687888990919293949596979899100101102103104105106107108Signal GND V DD YR12YR11YR10

YR9YR8YR7YR6YR5YR4YR3YR2YR1YR0EOPSS

V DD SOBFP WTB1WTB0WTA1WTA0MBFP

CLK OSEL1OSEL0

OER SFTA0SFTA1GWR0GWR1GWR2GWR3GWR4PR15PR14

AC P2

P15M14L13N15

L14

M15

K13

K14

L15

J14

J13

K15

J15

H14H15

H13G13G15F15G14F14F13

E15E14D15

C15D14E13C14B15D13C13B14A15GC 109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144

AC N14M13A14B12C11A13B11A12C10B10A11B13C12A10A9B8A8C8C7A7A6B7B6C6A5B5A4A3B4C5B3A2C4C3B9C9

NOTE. All GND and V DD pins must be used

PDSP16116/A/MC

NORMAL MODE OPERATION

When the MBFP mode select input is held low the ‘Normal’mode of operation is selected. This mode supports all Complex Multiply operations that do not require Block Floating Point arithmetic.Multiplier Satge

Complex two's complement fractional data is loaded into the X and Y input registers via the X and Y Ports on the rising edge of CLK. The Real and Imaginary components of the fractional data are each assumed to have the following format

BIT NUMBER 1514131211109876543210WEIGHTING

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

Where S = sign bit which has an effective weighting -20The value of the 16 bit two’s complement word is Value = (-1xS)+(bit14x2-1)+(bit13x2-2)+(bit12x2-3). . .The X & Y port registers are individually enabled by the CEX & CEY signals respectvely. If the registers are required to be permanently enabled, then these signals may be tied to ground. On each clock cycle the contents of the input registers are passed to the four multipliers to start a new Complex Multiply operation. Each Complex Multiply operation requires four partial products (Xr x Yr), (Xr x Yi), (Xi x Yr), (Xi x Yi), all of which are calculated in parallel by the four 16 x 16Multipliers. Only one clock cycle is required to complete the multiply stage before the Mutliplier results are loaded into the Multiplier output registers for passing on to the Adder/Subtractors in the next cycle. Each multiplier produces a 31bit result with the duplicate sign bit eliminated. The format of the output data from the Multipliers is

BIT NUMBER 30292827262524. . .76543210WEIGHTING

-1

-2

-3

-4

-5

-6

. . .

-23

-24

-25

-26

-27

-28

-29

-30

The effective weighting of the sign bit is -20Result Correction

Due to the nature of the fraction twos complement representation it is possible to represent -1 exactly but not 1.With conventional multipliers this causes a problem when -1is multiplied by -1 as the multiplier produces an incorrect result. The PDSP16116 includes a trap to ensure that the most positive number (value = 1.2-30), (hex = 7FFFFFFFF) is subsituted for the incorrect result. The multiplier result is therefore always a (correct) fractional https://www.wendangku.net/doc/0818531335.html,plex Conjugation

Either the X or Y input data may be complex conjugated by asserting the CONX or CONY signals respectively. Asserting either of these signals has the effect of inverting (multiplying by -1) the imaginary component of the respective input. Table 3 shows the effect of CONX and CONY on the X and Y inputs.

CONX low high low high

CONY low low high high

OPERATION (XR+XI)x(YR+YI)(XR+XI)x(YR-YI)(XR-XI)x(YR+YI)Invalid

FUNCTION X x Y X x Conj Y Conj X x Y Invalid

Table 3 Conjugate Functions

Adder / Subtractor Stage

The 31 bit Real and Imaginary results from the Multipliers are passed to two 32 bit Adder/Subtractors. The Adder calculates the imaginary result ((Xr x Yi) + (Xi x Yr)) and the Subtractor calculates the Real result ((Xr x Yr) = (Xi x Yi)).Each Adder/Subtractor produces a 32 bit result with the following format.

BIT NUMBER 313029282726. . .876543210WEIGHTING

-1

-2

-3

-4

. . .

-22

-23

-24

-25

-26

-27

-28

-29

-30

The effective weighting of the sign bit is -21Rounding

The ROUND control when asserted rounds the most significant 16 bits of the full 32 bit result from the Adder/Subtractor. If the ROUND signal is active (High), then bit 16is set to a one, rounding the most significant 16 bits of the Adder/Subractor result. (The least siginificant 16 bits are unaffected). Inserting a one ensures that the rounding error is never greater than 1LSB, and that no DC bias is introduced as a result of the rounding processes.The format of the Rounded result is;

The effective weighting of the sign is -21Shifter

Each of the two Adder/Subtractors are followed by Shifters controlled via the WTB control input. These shifters can each apply four different shifts, however the same shift is applied to both real and imaginary components. The four shift options are:

i)WTB1:0 = 11 Shift complex product one place to the left giving a shifter output format:

BIT NUMBER 31302928272625. . .76543210WEIGHTING

-1

-2

-3

-4

-5

-6

. . .

-24

-25

-26

-27

-28

-29

-30

-31

The effective weighting of the sign bit is -20

PDSP16116/A/MC

Pin No.J1J2J3J4J5J6J7J8J9J10J11J12J13J14J15K1K2K3K4K5K6K7K8K9K10K11K12K13K14K15L1L2L3L4L5L6L7L8L9L10L11L12L13L14L15M1M2M3M4M5M6M7M8M9M10M11M12M13M14M15

Pin No.E1E2E3E4E5E6E7E8E9E10E11E12E13E14E15F1F2F3F4F5F6F7F8F9F10F11F12F13F14F15G1G2G3G4G5G6G7G8G9G10G11G12G13G14G15H1H2H3H4H5H6H7H8H9H10H11H12H13H14H15

Con.V1N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C 0V N/C N/C 0V N/C N/C N/C 0V N/C N/C N/C 0V N/C N/C N/C N/C N/C N/C N/C V1N/C N/C V1N/C N/C V1N/C N/C N/C V1 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C V1 100?

Con.0V 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C V1 100?V1 100?0V 100?0V 100?V1 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C 0V 100?0V 100?0V 100?0V 100?0V 100?0V 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C V1 100?0V 100?V1 100?0V 100?0V 100?V1 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C 0V 100?0V 100?V1

Con.V1 100?V1 100?V1 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C 0V 100?0V 100?0V 100?V1 100?V1 100?V1 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C 0V 100?0V 100?0V 100?V1 100?V1 100?V1 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C 0V 100?0V 100?0V 100?V1 100?V1 100?V1 100?N/C N/C N/C N/C N/C N/C N/C N/C N/C 0V 0V 100?0V 100?

Pin No.N1N2N3N4N5N6N7N8N9N10N11N12N13N14N15P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15

Con.V1 100?V1 100?0V 100?0V 100?0V 100?0V 100?0V 100?V1 100?V1 100?V1 100?V1 100?V1 100?0V 100?V10V 100?V1 100?0V 0V 100?0V 100?0V 100?0V 100?0V 100?V1 100?V1 100?V1 100?V1 100?V1 100?V1 100?0V 100?0V 100?V10V 100?0V 100?0V 100?0V 100?0V 100?0V 100?V1 100?V1 100?V1 100?V1 100?V1 100?V1 100?V1 100?0V 100?

Pin No.A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

Part No:PDSP11616/A/MC 16 By16 Bit Complex Multiplier Package Type:

AC144

VDD max = +5.5V = V1N/C = not connected

Figure 4(a) - Life Test/Burn-in connections NOTE: PDA is 5% and based on groups 1 and 7

PDSP16116/A/MC

Pin No.

100

101

102

103

104

105

106

107

108

Pin No.

Con.

N/C

Con.

N/C

Pin No.

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Con.

N/C

V1 Pin No.

Part No:PDSP16116/A/MC 16 By 16 Bit Complex Multiplier

Package Type:GC144

VDD max = +5.0V = V1

N/C = not connected

Figure 4(b) Life Test/Burn-in connections

NOTE: PDA is 5% and based on groups 1 and 7

PDSP16116/A/MC

ii)WTB1:0 = 00 No shift applied giving a shifter output format:

The effective weighting of the shift bit is -21.

iii)WTB1:0 = 01 Shift complex product one place to the right giving a shifter output format:

The effective weighting of the sign bit is -22

iv)WTB1:0 = 10 Shift complex product two places to the right giving a shifter output format:

The effective weighting of the sign bit is -23.Overflow

If the left shift option is selected and the Adder/Subtractor contain a 32 bit word, then an invalid result will be passed to the output. An invalid output arising from this combination of events will be flagged by the SFTA0 flag output. The SFTA0Flag will go high if either the real or imaginary reslut is invalid.Output Select

The output from the Shifters is passed to the Output Select Mux, which is controlled via the OSEL inputs. These inputs are not registered and hence allow the output combination to be changed within each cycle. The full complex 64 bit result from the multiplier may therefore be output within a single cycle. The OSEL control selects four different output combinations as as summarised in Table 4.

PR MSR LSR MSR MSI

PI MSI LSI LSR LSI

OSEL00101

OSEL10011

Table 3 - Output Selection

(Where MSR and LSR are the most and least siginificant 16 bit words of the Real Shifter output, MSI and LSI are the most and least significant 16 bit words of the imaginary Shifter output).The output select options allow two different modes for extracting the full 32 bit result from the PDSP16116. The first mode treats the two 16 bit outputs as real and imaginary ports allowing the real and imaginary results to be output in two halves on the real and imaginary output ports. The second mode treats the two 16 bit outputs as one 32 bit output and allows the real and imaginary results to be output as 32 bit words.

PIN DESCRIPTIONS

XR, XI, YR, YI

Data inputs 16 bits: Data is loaded into the input registers from these ports on the rising edge of CLK. The data format is Twos Complement Fractional, where the MSB (sign bit) is bit 15. In normal mode the weighting of the MSB is -20 ie -1.PR, PI

Data outputs 16 bits: Data is clocked into the output registers and passed to the PR and PI outputs on the rising edge of CLK. The data format is Twos Complement Fractional. The field of the internal result selected for output via PR and PI is controlled by signals OSEL1:0 (see Table 4).CLK

Common Clock to all internal register.CEX, CEY

Clock enables for X and Y input ports: When low these inputs enable the CLK signal to the X or Y input registers allowing new data to be clocked into the Multiplier.CONX, CONY

If either of these inputs are high on the rising edge of CLK,then the data in the associated input has its imaginary component inverted (multiplied by -1), see Table 3. CONX and CONY affect data input on the same clock rising edge.ROUND

The ROUND control is used to round the most siginficant 16 bits of the Adder/Subtractor result prior to being passed to the output register. The rounding operation takes place one cycle after the ROUND input is taken high. The ROUND input is not latched and is intended to be tied high or low depending upon the application.MBFP

Mode select: When high, Block Floating Point (BFP) mode is selected. This allows the device to maintain the dynamic range of the data using a series of word tags. This is especially useful in FFT appllications. When low, the chip operates in normal mode for more general applications. This pin is intended to be tied high or low, depending on application.

Bit Number 30Weighting

292827266543210≈≈≈

2–29

–28

–27

–26

–25

–24

–4

–3

–2

312

–1

–23

252

–5

24Bit Number 30Weighting

2928272676543210

≈≈≈

2–30

2–292–282–272–262–252–242–4

2–32–220312–182–222–23Bit Number 30Weighting

292827266543210≈≈≈

2–28

–27

–26

–25

–24

–4

–3

–2

312

–1

–23

25242

–22

PDSP16116/A/MC

Start of BFP: This input should be held low for the first cycle of the first pass of the BFP calculations (see Fig.7). It serves to reset the internal registers associated with BFP control.When operating in normal mode this input should be tied low.EOPSS (BFP MODE ONLY)

End of pass: This input should be held low for the last cycle of each pass and for the lay time between passes. It instructs the control logic to update the value of the global weighting register and prepare the BFP circuitry for the next pass. When operating in normal mode this input should be tied low.AR15:13 (BFP MODE ONLY)

Three Msbs of the real part of the A-word : These are used in the FFT butterfly application to deteremine the magnitude of the real part of the A-word and, hence, to determine if there will be any chage of word growth in the PDSP16318 Complex Accumulator. When operating in normal mode, these inputs are not used and may be tied low.AI15:13 (BFP MODE ONLY)

Three Msbs of the imaginary part of the A-word : used in the same fashion as AR.SFTR2:0 (BFP MODE ONLY)

Accumulator result shift control. These pins should be linked directly to the S2:0 pins on the PDSP16318 Complex Accumulator. They control the accumulator’s barrel shifter (see Table 5). The purpose of this shift is to minimise sign extension in the multiplier or accumulator ALU’s. When operating in normal mode, these output are superfluous.

GWR4:0 (BFP MODE ONLY)

Contents of the global weighting register: This stores the weighting of the largest word present with respect to the weighting of the original input words. Hence, if the contents of the GWR are 00010, this indicates that the largest word currently being processed has its binary point two bits to the right of the original data at the start of the BFP calculations.The contents of this register are updated at the end of each pass, according to the largest value of WTOUT occuring during that pass. (i.e. If WTOUT = 11, then GWR will be increased by 2). The GWR is presented in two’s complement format. These outputs are superfluous in normal mode.WTOUT1:0 (BFP MODE ONLY)

Word tag output. This tag records the weighting of the output words from the current cycle relative to the current global weighting register (see Table 6). It should be stored along with the A’ and B’ words as it will form the input word tags, WTA and WTB, for each complex word during the next pass. These outputs are superfluous in normal mode.

Table 5 - Auccumulator Shifts ( BFP mode )

SFTR2:00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

FUNCTION Reserved Reserved Reserved Shift right by one No shift Shift left by one Shift left by two Reserved

Weighting of the output relative to the current global weighting register WTOUT1:00 00 11 01 1

One less The same One more Two more

Table 6 - Word Tag Weightings

WTA1:0 (BFP MODE ONLY)

Word tag from the A-word. This word records the weighting of the A-word relative to the global weighting register on the previous pass. Although the A-word inself is not processed in the PDSP16116, this information is required by the control logic for the radix-2 butterfly FFT application.These inputs should be tied low in normal mode.WTB1:0 (BFP & NORMAL MODES)

In BFP mode, this is the word tag from the B-word. This is operated in the same manner as WTA but for the B-word. The value of the word tags are used to ensure that the binary weighting of the A word and the product of the complex multiplier are the same at the inputs to the complex accumulator. Depending on which word is the larger, the weighting adjustment is performed using either the internal shifter or an external shifter controlled by SFTA. The word tags are also used to maintain the weighting of the final result to within plus two and minus one binary points relative to the new GWR. (On the first pass all word tags will be ignored).

PDSP16116/A/MC

OSEL1:0

The outputs from the device are selected by the OSEL0 &OSEL1 instruction bits. These controls allow selection of the output combination during the current cycle. (They are not registered). These are four possible output configurations that allow either complex outputs of the most or least significant bytes, or real or imaginary outputs of the full 32 bit word (see Table 4). OSEL0 and OSEL1 should both be tied low when in BFP mode.BFP MODE FFT APPLICATION

The PDSP16116 may be used as the main arithmetic unit of the butterfly processor which will allow the following FFT benchmarks:

1024 point complex radix-2 transform in 517us 512 point complex radix-2 transform in 235us 256 point complex radix-2 transform in 106us

In addition, with pin MBFP tied high, the BFP circuitry within the PDSP16116 can be used to adaptively rescale data throughout the course of the FFT so as to give high-resolution results.

The BFP system on the PDSP16116 can be used with any variation of the Radix-2 Decimation-In-Time FFT - e.g. the

In normal mode, these inputs perform a different function.They directly control the internal shifter at the output port as shown in Table 7.FUNCTION

shift complex product one place to the left no shift applied

shift complex product one place to the right shift complex product two places to the right

WTB1:011000110

SFTA1:0 (BFP & NORMAL MODES)

In BFP mode, these signals act as as the A-word shift control. They allow shifting from one to four places to the right,see Table 8. Depending on the relative weightings of the A-words and the complex product, the A-word may have to be shifted to the right to ensure compatible weightings at the inputs to the PDSP16318 complex accumulator. (The two words must have the same weighting if they are to be added).

In normal mode, SFTA0 performs a different a different function. If WTB1:0 is set to implement a left shift, then overflow will occur if the data is fully 32 bits wide. This pin is used to flag such an overflow. SFTA1 is not used in normal mode.FUNCTION

Shift A-word 1 places to the right Shift A-word 2 places to the right Shift A-word 3 places to the right Shift A-word 4 places to the right

WTB1:00 00 11 01 1

Table 8 - External A-word shift control

Table 7 - Normal Mode Shift Control

Constant Geometry algorithm, the In-Place algorithm etc. An N-point Radix-2 DIT FFT is split into log (N) passes. Each pass consists of N/2 ‘butterflies’, each performing the operation:

A’ = A + B.W B’ = A - B.W Where W is the complex coefficient and A & B are the complex data.

Fig.4 illustrates how a single PDSP16116 may be combined with two PDSP1601’s and two PDSP16318’s to form a complete BFP butterfly processor. The PDSP16318’s are used to perform the complex addition and subtraction of the butterfly operation, while the PDSP1601’s are used to match the data path of the A-word to the pipelining and shifting operations within the PDSP16116.

For more information on the theory and construction of this butterfly processor, refer to application note AN59.BFP MODE OPERATION

The BFP mode on the PDSP16116 is intended for use in the FFT application described above. i.e. it is intended to prevent data degredation during the course of an FFT calculation. The operation of the PDSP16116 based BFP butterfly processor (see Fig.4) is described below.The Block Floating Point System

A block floating point system is essentially an ordinary integer arithmetic system with some clever logic bolted on.The object of the extra logic is to lend the system some of the enormous dynamic range afforded by a true floating point system without suffering the corresponding loss in performance.

The initial data used by the FFT should all have the same binary arithmetic weighting. i.e. the binary point should occupy the same position in every data word, as is normal in integer arithmetic. However, during the course of the FFT, a variety of weightings are used in the data words to increase the dynamic range available. This situation is similar to that within a true floating point system, though the range of numbers representable is more limited. In the BFP system used in the PDSP16116, there are, within any one pass of the FFT, four possible positions of the binary point wihin the integer words.To record the position of its binary point, each word has a 2-bit word tag associated with it. By way of example, in a particular pass we may have the following four positions of binary point avaiable, each denoted by a certain value of word tag:

XX.XXXXXXXXXXXX word tag = 00XXX.XXXXXXXXXXX word tag = 01XXXX.XXXXXXXXXX word tag = 10XXXXX.XXXXXXXXX

word tag = 11

PDSP16116/A/MC

12At the end of each constituent pass of the FFT, the

positions of the binary point supported may change to reflect the trend of data increase or decreases in magnitude. Hence, in the pass following that of the above example, the four positions of binary point supported may be change to: XX.XXXXXXXXXXXX word tag = 00

XXX.XXXXXXXXXXX word tag = 01

XXXX.XXXXXXXXXX word tag = 10

XXXXX.XXXXXXXXX word tag = 11

This variation in the range of binary points supported from pass to pass (i.e. the movement of the binary point relative to its position in the original data) is recorded in the GWR.

Thus we can determine the position of the binary point relative to its initial position by modifying the value of GWR by WTOUT for a given word as shown in Table 6.

As an example, if GWR=01001 and WTOUT=10 then the binary point has moved 10 places to the right of its original position.

Figure 5 - FFT Butterfly Processor

PDSP16116/A/MC

The butterfly operation

The butterfly operation is the arithmetic operation which is repeated many times to produce an FFT. The PDSP16116A based butterfly processor performs this operation in a low power high accuracy chip set.

A new butterfly operation is commenced each cycle,requiring a new set of data for , B, W, WTA and WTB. Five cycles later, the corresponding results A' and B' are produced along with their associated WTOUT. In between, the signals SFTA and SFTR are produced and acted upon by the shifters in the PDSP1601/A and PDSP16318/A. The timing of the data and control signals is shown in Fig.6.

The results (A' and B') of each butterfly calculation in a pass must be stored away to be used later as the input data (A and B) in the next pass. Each result must be stored together with its associated word tag, WTOUT. Although WTOUT is common to both A' and B', it must be stored separately with each word as the words are used on different cycles during the next pass. At the inputs, the word tag associated with the A word is known as WTA and the word tag associated with the B word is known as WTB. Hence, the WTOUTs from one pass will become the WTAs and WTBs for the following pass. It should be noted that the first pass is unique in that word tags need not be input into the butterfly as all data initially has the same weighting. Hence, during the first pass alone, the inputs WTA and WTB are ignored.

Figure 6 - Butterfly Operation

Figre 7 Butterfly Data and Control Signals

;;;;;

n-2n-1

n n+1n+2n+3

;;;;

n n+1n+2n+3n+4n+5n

n+1

n+2

n+3

n+4

n+5

n n+1n+2n+3n+4n+5

n-3n-2n-1n n+1n+2

;;;;

n-2n-1n-1n n+1n+2n-3

n-2

n-1

n+1

n+2

n-5n-4n-3n-2n-1n ;;;;;

n-5

n-4

n-3

n-2

n-1

CLK

Present Br, Bi,Wr, Wi to inputs Present WTA,WTB to inputs Present Ar,Ai to inputs Output SFTA

Output SFTR Output Pr, Pi

Output DAr, DAi

Output WTOUT Output A'r, A'i, B'r, B'i

PDSP16116/A/MC

Control of the FFT

To enable the block floating point hardware to keep track of the data, the following signals are provided :

SOBFP - start of the FFT EOPSS - end of current pass These inform the PDSP16116/A when an FFT is starting and when each pass is complete. Fig.7 shows how these signals should be used and a commentary is provided below.

To commence the FFT, the signal EOPSS should be set high (where it will remain for the duration of the pass). SOBFP should be pulled low during the initial cycle when the first data words A and B are presented to the inputs of the butterfly processor. The following cycle SOBFP must be pulled high

where it should remain for the duration of the FFT. New data is presented to the processor each successive cycle until the end of the first pass of the FFT. On the last cycle of the pass,the signal EOPSS should be pulled low and remain low for a minimum of five cycles *, the time required to clear the pipeline of the butterfly processor so that all the results from one pass are obtained before commencing the following pass. On the initial cycle of each new pass, the signal EOPSS should be pulled high and it should remain high until the final cycle of that pass, when it is pulled low again.

* Should a longer pause be required between passes - to arrange the data for the next pass, for example, then EOPSS may be kept low as long as necessary - the next pass cannot commence until it is brought high again.

FFT Output Normalisation

When an FFT system outputs a series of FFT results for display, storage or transmission, it is essential that all results are compatible, i.e. with the binary point in the same position.However, in order to preserve the dynamic range of the data in the FFT calculation, the PDSP1601/A employs a range of different weightings. Therefore, data must be re-formatted at the end of the FFT to be pre-determined common weighting.This can be done by comparing the exponent of given data word with the pre-determined unversial exponent and then shifting the data word by the difference. The PDSP1601/A,with its multifunction 16 bit barrel shifter, is ideally suited to this task.

What value should the Unversal Exponent take? Well,according to theory, the largest possible data result from an FFT is N times the largest input data. This means that the binary point can move a maximum of log2(N) places to the right. Hence, if we choose the Unverisal Exponent to be log2(N) this should give us sufficient range to represent all data points faithfully.

In practice, data output may never approach the theoreti-cal maximum. Hence, it may be worthwhile to try various Unverisal Exponents and choose the one best suited to the particular application.

Data is output from the butterfly processor with a two-part exponent: the 5-bit GWR applicable to all data words from a given FFT and a 2-bit WTOUT associated with each individual data word. To find the complete exponent for a given word, the GWR for that FFT must be modified by its WTOUT as shown in Table 6. The result is the number of places the binary point has shifted to the right during the course of the FFT.

This value must be compared with the Unversial Exponent to determine the shift required. This is done by subtracting it from the Unversial Exponent. The number of places to be shifted is equal to the difference between the two exponents.The shift can be implemented in a PDSP1601/A. The shift value is fed into the SV port.

Figure 8 - Use of the BFP Control Signals

PDSP16116/A/MC

As FFT data consists of real and imaginary parts, either two PDSP1601As must be used (controlled by the same logic)or a single PDSP1601/A could be used handling real and imaginary data on alternate cycles (using the same instructions for both cycles).

An example of an output normalisation circuit is shown in Fig.8. Only 4 bit data paths are used in calculating the shift.This means that we must be able to trap very small values negative of GWR and force a 15-bit right shift in such cases.

N.B.

It is easier to simply add the word tag to the exponent for the purpose of determing the shift required, instead of modifying it according to Table.6. To compensate for this, the Universal Exponent may be increased by one.

Fig.9 Output Normalisation Circuitry

PDSP16116/A/MC

NOTES

1.Exceeding these ratings may cause permanent damage.

Functional operation under these conditions is not implied.

2.Maximum dissipation or 1 second should not be exceedeed, only one output to be tested at any one time.

3.Exposure to absolute maximum ratings for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply voltage V CC -0.5V to 7.0V Input voltage V IN -0.5V to V CC +0.5V

Output voltage V OUT

-0.5V to V CC +0.5V Clamp diode current per I k (see note 2)18mA Static discharge voltage (HBM)500V Storage temperature range T S -65°C to +150°C Ambient temperature with power applied T AMB

Military -55°C to +125°C Industrial -40°C to +85°C Junction temperature 150°C Package power dissipation 1000mW Thermal resistances

Junction to case ?JC 12°C/W Junction to case ?JA 29°C/W

ELECTRICAL CHARACTERISTICS

Operating conditions (unless otherwise stated):

Industrial: T AMB = -40°C to +85°C, V CC = 5.0V ± 10%, GND = 0V

Military: T AMB = -55°C to +125°C, V CC = 5.0V ± 10%, GND = 0V

Min.-0.4--0.8+10

+50300V OH V OL V IH V IH V IL I IN C IN I OZ I OS

Min.2.4-3.02.2--10

-5010

Typ.

Value Output high voltage Output low voltage Input high voltage Input high voltage Input low voltage Input leakage current Input capacitance

Output leakage current Output S/C current

I OH = 8mA I OL = -8mA CLK input only All other inputs GND

Characteristic

Symbol

Units

Conditions

V V V V V μA pF μA mA

Static Characteristics

PDSP16116/A/MC

Min.5555511-11-14-14-14------1003020--Switching Characteristics

CLK rising edge to P-PORTS CLK rising edge to WTOUT1:0CLK rising edge to GWR4:0CLK rising edge to SFTA1:0CLK rising edge to SFTR2:0

Setup CEX or CEY to CLK rising edge Hold CEX or CEY to CLK rising edge

Setup X or Y port inputs to CLK rising edge Hold X or Y port inputs to CLK rising edge

Setup WTA1:0, WTB1:0, SOBFP or EOPSS inputs to CLK rising edge

Hold WTA1:0, WTB1:0, SOBFP or EOPSS inputs to CLK rising edge

Setup CONX or CONY inputs to CLK rising edge Hold CONX or CONY inputs to CLK rising edge Setup AR15:13 or AI15:13 to CLK rising edge Hold AR15:13 or AI15:13 to CLK rising edge OPSEL to valid P-PORTS

OER or OEI rising PR-PORT or PI-PORT high to Z OER or OEI rising PR-PORT or PI-PORT low to Z OER or OEI falling PR-PORT or PI-PORT Z to high OER or OEI falling PR-PORT or PI-PORT Z to low Clock period Clock high time Clock low time

Vcc Current (CMOS input levels)Vcc Current (TTL input levels)

Min.555558-8-8-8--------50

1212--Max.4530306050-0-2-0-0-0

3535452224---60100

Max.2320203028-0-0-0-0-020********---80130

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns mA mA

Conditions

PDSP16116A PDSP16116Characteristic

Units 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF

2 x LSTTL + 20pF see Fig.9see Fig.9see Fig.9see Fig.9

see Note 4see Note 4

NOTE 4 :- V CC = Max Outputs unloaded, clock freq = Max

Fig.10 Three state delay measurement load

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