当前位置：文档库 › OV9650_Datasheet

OV9650_Datasheet

Advanced Information Preliminary Datasheet

OV9650 Color CMOS SXGA (1.3 MegaPixel) C AMERA C HIP TM with OmniPixel TM Technology O mni

ision

General Description

The OV9650 C AMERA C HIP TM is a low voltage CMOS image sensors that provides the full functionality of a

Applications

?Cellular and Picture Phones ?Toys

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

Functional Description

Figure2 shows the functional block diagram of the OV9650 image sensor. The OV9650 includes:

?Image Sensor Array (1300x1028 active image array)

?Analog Signal Processor

?A/D Converters

?Digital Signal Processor (DSP)

?Output Formatter

?Timing Generator

Functional Description

Image Sensor Array

The OV9650 sensor has an active image array of 1300columns by 1028 rows (1,336,400 pixels). Figure 3 shows a cross-section of the image sensor array.

In addition to the A/D conversion, this block also has the following functions:?Digital Black-Level Calibration (BLC)?Optional U/V channel delay ?Additional A/D range controls In general, the combination of the A/D Range Multiplier drive current

OmniVision

OV9650

Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP ?

Pin Description

NOTE:

D[9:2] for 8-bit YUV or RGB565/RGB555 (D[9] MSB, D[2] LSB)D[9:0] for 10-bit Raw RGB data (D[9] MSB, D[0] LSB)Table 1

Pin Description

Pin Location

Name Pin Type Function/Description

A1PWDN Function (default = 0)Power Down Mode Selection - active high, internal pull-down resistor.

0:Normal mode

1:Power down mode A2AVDD Power Analog power supply (V DD-A = 2.45 to 2.8 VDC)A3SIO_D I/O SCCB serial interface data I/O

A4D2Output Output bit[2] - LSB for 8-bit YUV or RGB565/RGB555A5D4Output Output bit[4]

B1VREF V REF Internal voltage reference - connect to ground through 1μF capacitor B2NVDD V REF Voltage reference B3AGND Power Analog ground

B4SIO_C Input SCCB serial interface clock input B5D3Output Output bit[3]

C1D0Output Output bit[0] - LSB for 10-bit Raw RGB data only

C2DVDD Power Power supply (V DD-C = 1.8 VDC + 10%) for digital core logic C4NC —No connection C5D5Output Output bit[5]

D1D1Output Output bit[1] - for 10-bit RGB only D2VSYNC Output Vertical sync output D4NC —No connection D5NC —No connection E1HREF Output HREF output

E2DOVDD Power

Digital power supply (V DD-IO = 2.5 to 3.3 VDC) for I/O

E3RESET Function (default = 0)Clears all registers and resets them to their default values. Active high, internal pull-down resistor.E4D8Output Output bit[8]E5D6Output Output bit[6]F1PCLK Output Pixel clock output F2XVCLK1Input System clock input F3DOGND Power Digital ground

F4D9Output Output bit[9] - MSB for 10-bit Raw RGB data and 8-bit YUV or RGB565/RGB555F5

Output

Output bit[7]

Electrical Characteristics

NOTE:

Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage.

Table 2

Absolute Maximum Ratings

Ambient Storage Temperature

-40oC to +95oC

Supply Voltages (with respect to Ground)

V DD-A

4.5 V V DD-C 3 V V DD-IO

4.5 V

All Input/Output Voltages (with respect to Ground)-0.3V to V DD-IO +1V Lead-free Temperature, Surface-mount process 245oC ESD Rating, Human Body model 2000V

Table 3

DC Characteristics (-20°C < T A < 70°C)

Symbol Parameter

Condition

Min Typ Max Unit V DD-A DC supply voltage – Analog – 2.45 2.5 2.8V V DD-C DC supply voltage – Core – 1.62 1.8 1.98V V DD-IO DC supply voltage – I/O power – 2.25

– 3.6

V I DDA Active (Operating) Current See Note a a. V DD-A = 2.5V, V DD-C = 1.8V, V DD-IO = 3.0V

I DDA = ∑{I DD-IO + I DD-C + I DD-A }, f CLK = 24MHz at 7.5 fps YUV output, no I/O loading

20mA I DDS-SCCB Standby Current See Note b b. V DD-A = 2.5V, V DD-C = 1.8V, V DD-IO = 3.0V

I DDS:SCCB refers to a SCCB-initiated Standby, while I DDS:PWDN refers to a PWDN pin-initiated Standby 1mA I DDS-PWDN Standby Current 10

μA V IH Input voltage HIGH CMOS

0.7 x V DD-IO

V V IL Input voltage LOW 0.3 x V DD-IO

V V OH Output voltage HIGH CMOS

0.9 x V DD-IO

V V OL Output voltage LOW 0.1 x V DD-IO

V I OH Output current HIGH See Note c

Standard Output Loading = 25pF, 1.2K ?

8mA I OL Output current LOW 15

mA I L

Input/Output Leakage

GND to V DD-IO ± 1

μA

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

Table 4 Functional and AC Characteristics (-20°C < T A < 70°C)

Symbol Parameter Min Typ Max Unit Functional Characteristics

A/D Differential Non-Linearity+ 1/2LSB

A/D Integral Non-Linearity+1LSB

AGC Range18dB

Red/Blue Adjustment Range12dB Inputs (PWDN, CLK, RESET)

f CLK Input Clock Frequency102448MHz

t CLK Input Clock Period2142100ns t CLK:DC Clock Duty Cycle455055% t S:RESET Setting time after software/hardware reset1ms t S:REG Settling time for register change (10 frames required)300ms SCCB Timing (see Figure4)

f SIO_C Clock Frequency400KHz

t LOW Clock Low Period 1.3μs t HIGH Clock High Period600ns t AA SIO_C low to Data Out valid100900ns t BUF Bus free time before new START 1.3μs t HD:STA START condition Hold time600ns t SU:STA START condition Setup time600ns t HD:DAT Data-in Hold time0μs t SU:DAT Data-in Setup time100ns t SU:STO STOP condition Setup time600ns t R, t F SCCB Rise/Fall times300ns t DH Data-out Hold time50ns Outputs (VSYNC, HREF, PCLK, and D[9:0] (see Figure5, Figure6, Figure7, Figure8, Figure10, and Figure11) t PDV PCLK[↓] to Data-out Valid5ns t SU D[9:0] Setup time15ns t HD D[9:0] Hold time8ns t PHH PCLK[↓] to HREF[↑]05ns t PHL PCLK[↓] to HREF[↓]05ns

AC Conditions:? V DD: V DD-C = 1.8V, V DD-A = 2.5V, V DD-IO = 3.0V ? Rise/Fall Times: I/O: 5ns, Maximum

SCCB: 300ns, Maximum ? Input Capacitance: 10pf

? Output Loading: 25pF, 1.2K? to 3V

? f CLK: 24MHz

Timing Specifications

Figure 4 SCCB Timing Diagram

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

Figure 7 VGA Frame Timing

Timing Specifications

Figure 10 CIF Frame Timing

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

Figure 13 RGB 565 Output Timing Diagram

Timing Specifications

OV9650 Light Response

Figure 15 OV9650 Light Response

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

Register Set Table5 provides a list and description of the Device Control registers contained in the OV9650. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read.

Table 5 Device Control Register List

Address (Hex)Register

Name

Default

(Hex)R/W Description

00GAIN00RW AGC[7:0] – Gain control gain setting ?Range: [00] to [FF]

01BLUE80RW AWB – Blue channel gain setting ?Range: [00] to [FF]

02RED80RW AWB – Red channel gain setting ?Range: [00] to [FF]

03VREF12RW Vertical Frame Control

Bit[7:6]:AGC[9:8] (see register GAIN for AGC[7:0])

Bit[5:3]:VREF end low 3 bits (high 8 bits at VSTOP[7:0] Bit[2:0]:VREF start low 3 bits (high 8 bits at VSTRT[7:0]

04COM100RW Common Control 1

Bit[7]:Reserved

Bit[6]:CCIR656 format

Bit[5]:QQVGA or QQCIF format. Effective only when QVGA or QCIF output is selected (register bit COM7[4]) and related

HREF skip mode based on format is selected (register

COM1[3:2])

Bit[4]:Reserved

Bit[3:2]:HREF skip option

00:No skip

01:YUV/RGB skip every other row for YUV/RGB, skip 2

rows for every 4 rows for Raw data

1x:Skip 3 rows for every 4 rows for YUV/RGB, skip 6 rows

for every 8 rows for Raw data

Bit[1:0]:AEC low 2 LSB (see registers AECHM for AEC[15:10] and AECH for AEC[9:2])

05BAVE00RW U/B Average Level

Automatically updated based on chip output format

06GEAVE00RW Y/Ge Average Level

Automatically updated based on chip output format

07RSVD00–Reserved

08RAVE00RW V/R Average Level

Automatically updated based on chip output format

09COM201RW

Common Control 2

Bit[7:5]:Reserved

Bit[4]:Soft sleep mode Bit[3:2]:Reserved

Bit[1:0]:

Output drive capability 00:1x 01:2x 10:2x 11:4x

0A PID 96R Product ID Number MSB (Read only)0B

VER

Product ID Number LSB (Read only)0C COM300RW

Common Control 3

Bit[7]:Reserved

Bit[6]:Output data MSB and LSB swap Bit[5:4]:Reserved Bit[3]:

Pin selection

1:Change RESET pin to EXPST_B (frame exposure

mode timing) and change PWDN pin to FREX (frame exposure enable)

Bit[2]:VarioPixel for VGA and CIF Bit[1]:Reserved

Bit[0]:

Single frame output (used for Frame Exposure mode only)

0D COM400RW

Common Control 4

Bit[7]:VarioPixel for QVGA, QCIF, QQVGA, and QQCIF Bit[6]:Reserved

Bit[5]:

Pixels for sub-sampling mode

0:Get average neighbor pixel in sub-sampling mode 1:Get sum instead of average neghbor pixel in

sub-sampling mode Bit[4:3]:Reserved

Bit[2]:

Tri-state option for output clock at power-down period 0:Tri-state at this period 1:No tri-state at this period

Bit[1]:

Tri-state option for output data at power-down period 0:Tri-state at this period 1:No tri-state at this period Bit[0]:

Reserved

Table 5

Device Control Register List (Continued)

Address (Hex)

Default (Hex)

R/W

Description

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

0E COM501RW Common Control 5

Bit[7]:System clock selection. If the system clock is 48 MHz, this bit should be set to high to get 15 fps for YUV or RGB Bit[6:5]:Reserved

Bit[4]:Slam mode enable

0:Master mode

1:Slam mode (used for slave mode)

Bit[3]:ADC offset manual control

0:Offset is controlled automatically

1:Register OFON[7:4] can enable ADC offset addition Bit[2:1]:Reserved

Bit[0]:Exposure step can be set longer than VSYNC time

1:In Normal mode, AEC changes by 1/16 and in Fast

mode, AEC changes by double

0F COM643RW Common Control 6

Bit[7]:Output of optical black line option

0:Disable HREF at optical black

1:Enable HREF at optical black Bit[6:5]:Reserved

Bit[4]:HREF is high from optical black line

Bit[3]:Enable bias for ADBLC

Bit[2]:ADBLC offset

0:Use 4-channel ADBLC

1:Use 2-channel ADBLC

Bit[1]:Reset all timing when format changes Bit[0]:Enable ADBLC option

10AECH40RW Exposure Value

Bit[7:0]:AEC[9:2] (see registers AECHM for AEC[15:10] and COM1 for AEC[1:0])

11CLKRC00RW Data Format and Internal Clock

Bit[7]:Digital PLL option

0:Disable double clock option, meaning the maximum

PCLK can be as high as half input clock

1:Enable double clock option, meaning the maximum

PCLK can be as high as input clock

Bit[6]:Use external clock directly (no clock pre-scale available) Bit[5:0]:Internal clock pre-scalar

F(internal clock) = F(input clock)/(Bit[5:0]+1)

?Range: [0 0000] to [1 1111]

Table 5 Device Control Register List (Continued)

Address (Hex)Register

Name

Default

(Hex)R/W Description

12COM700RW

Common Control 7

Bit[7]:

SCCB Register Reset 0:No change

1:Resets all registers to default values Bit[6]:Output format - VGA selection Bit[5]:Output format - CIF selection Bit[4]:Output format - QVGA selection Bit[3]:Output format - QCIF selection Bit[2]:Output format - RGB selection Bit[1]:Reserved

Bit[0]:

Output format - Raw RGB (COM7[2] must be set high)

13COM88F RW

Common Control 8

Bit[7]:Enable fast AGC/AEC algorithm

Bit[6]:

AEC - Step size limit (used only in fast condition and COM5[0] is low)

0:Fast condition change maximum step is VSYNC 1:Unlimited step size Bit[5]:Banding filter ON/OFF Bit[4]:Reserved

Bit[3]:Enable AEC time can be less than 1 line option Bit[2]:AGC Enable Bit[1]:AWB Enable Bit[0]:

AEC Enable

14COM94A RW

Common Control 9

Bit[7]:Reserved

Bit[6:4]:

Automatic Gain Ceiling - maximum AGC value 000:2x 001:4x 010:8x 011:16x 100:32x 101:64x 110:128x

Bit[3]:Exposure timing can be less than limit of banding filter when light is too strong

Bit[2]:

Data format - VSYNC drop option 0:VSYNC always exists

1:VSYNC will drop when frame data drops

Bit[1]:Enable drop frame when AEC step is larger than VSYNC Bit[0]:

Freeze AGC/AEC

Table 5

Device Control Register List (Continued)

Address (Hex)

Default (Hex)

R/W

Description

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

15COM1000RW Common Control 10

Bit[7]:Set pin definition

1:Set RESET to SLHS (slave mode horizontal sync) and

set PWDN to SLVS (slave mode vertical sync) Bit[6]:HREF changes to HSYNC

Bit[5]:PCLK output option

0:PCLK always output

1:No PCLK output when HREF is low

Bit[4]:PCLK reverse

Bit[3]:HREF reverse

Bit[2]:Reset signal end point option

Bit[1]:VSYNC negative

Bit[0]:HSYNC negative

16RSVD00–Reserved

17HSTART1A RW Output Format - Horizontal Frame (HREF column) start high 8-bit (low 3bits are at HREF[2:0])

18HSTOP BA RW Output Format - Horizontal Frame (HREF column) end high 8-bit (low 3bits are at HREF[5:3])

19VSTRT01RW Output Format - Vertical Frame (row) start high 8-bit (low 2 bits are at VREF[1:0])

1A VSTOP81RW Output Format - Vertical Frame (row) end high 8-bit (low 2 bits are at VREF[3:2])

1B PSHFT00RW Data Format - Pixel Delay Select (delays timing of the D[9:0] data relative to HREF in pixel units)

?Range: [00] (no delay) to [FF] (256 pixel delay which accounts for whole array)

1C MIDH7F R Manufacturer ID Byte – High(Read only = 0x7F) 1D MIDL A2R Manufacturer ID Byte – Low(Read only = 0xA2)

1E MVFP00RW Mirror/VFlip Enable

Bit[7:6]:Reserved

Bit[5]:Mirror

0:Normal image

1:Mirror image Bit[4]:VFlip enable

0:VFlip disable

1:VFlip enable Bit[3:0]:Reserved

1F LAEC00RW Reserved

20BOS80RW B Channel ADBLC Result

Bit[7]:Offset adjustment sign

0:Add offset

1:Subtract offset

Bit[6:0]:Offset value of 10-bit range (high 7 bits)

Table 5 Device Control Register List (Continued)

Address (Hex)Register

Name

Default

(Hex)R/W Description

21GBOS 80RW

Gb channel ADBLC result

Bit[7]:

Offset adjustment sign 0:Add offset 1:Subtract offset

Bit[6:0]:

Offset value of 10-bit range

GROS

Gr channel ADBLC result

Bit[7]:

Offset adjustment sign 0:Add offset 1:Subtract offset

Bit[6:0]:

Offset value of 10-bit range

ROS

R channel ADBLC result

Bit[7]:

Offset adjustment sign 0:Add offset 1:Subtract offset

Bit[6:0]:

Offset value of 10-bit range

24AEW 78RW AGC/AEC - Stable Operating Region (Upper Limit)25

AEB

AGC/AEC - Stable Operating Region (Lower Limit)26VPT D4RW

AGC/AEC Fast Mode Operating Region

Bit[7:4]:Upper limit of 4 MSB Bit[3:0]:Lower limit of 4 LSB

BBIAS

B Channel Signal Output Bias (effective only when COM6[0] = 1)

Bit[7]:

Bias adjustment sign 0:Add bias 1:Subtract bias

Bit[6:0]:

Bias value of 10-bit range

GbBIAS

Gb Channel Signal Output Bias (effective only when COM6[0] = 1)

Bit[7]:

Bias adjustment sign 0:Add bias 1:Subtract bias

Bit[6:0]:

Bias value of 10-bit range

Gr_COM

Analog BLC and Regulator Control

Bit[7:6]:Reserved

Bit[5]:Bypass Analog BLC Bit[4]:Bypass regulator Bit[3:0]:

Reserved

EXHCH

Dummy Pixel Insert MSB

Bit[7:4]: 4 MSB for dummy pixel insert in horizontal direction Bit[3:2]:HSYNC falling edge delay 2 MSB Bit[1:0]:

HSYNC rising edge delay 2 MSB

2B EXHCL 00RW

Dummy Pixel Insert LSB

8 LSB for dummy pixel insert in horizontal direction

Table 5

Device Control Register List (Continued)

Address (Hex)

Default (Hex)

R/W

Description

OV9650Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP?O

2C RBIAS80RW R Channel Signal Output Bias (effective only when COM6[0] = 1) Bit[7]:Bias adjustment sign

0:Add bias

1:Subtract bias

Bit[6:0]:Bias value of 10-bit range

2D ADVFL00RW LSB of insert dummy lines in vertical direction (1 bit equals 1 line) 2E ADVFH00RW MSB of insert dummy lines in vertical direction

2F YAVE00RW Y/G Channel Average Value

30HSYST08RW HSYNC Rising Edge Delay (low 8 bits)

31HSYEN30RW HSYNC Falling Edge Delay (low 8 bits)

32HREF A4RW HREF Control

Bit[7:6]:HREF edge offset to data output

Bit[5:3]:HREF end 3 LSB (high 8 MSB at register HSTOP) Bit[2:0]:HREF start 3 LSB (high 8 MSB at register HSTART)

33CHLF00RW Bit[7:0]:Reserved 34ARBLM03RW Bit[7:0]:Reserved 35-36RSVD XX–Reserved

37ADC04RW Bit[7:0]:Reserved 38ACOM12RW Bit[7:0]:Reserved

39OFON00RW Bit[7:4]:Reserved

Bit[3]:Line buffer power down - must be set to "1" before chip power down

Bit[2:0]:Reserved

3A TSLB0C RW Line Buffer Test Option

Bit[7:6]:Reserved

Bit[5]:Bit-wise reverse

Bit[4]:UV output value

0:Use normal UV output

1:Use fixed UV value set in registers MANU and MANV

as UV output instead of chip output

Bit[3]:Output sequence is Y U Y V instead of U Y V Y

Bit[2]:Output sequence is Y V Y U instead of Y U Y V

Bit[1]:Reserved

Bit[0]:Digital BLC

Table 5 Device Control Register List (Continued)

Address (Hex)Register

Name

Default

(Hex)R/W Description

3B COM1100RW

Common Control 11

Bit[7]:

Night mode

0:Night mode disable

1:Frame rate will adjust based on COM11[6:5] before

AGC gain increases more than 2. Also, ADVFL and ADVFL will be automatically updated.Bit[6:5]:

Night mode insert frame option 00:Normal frame rate 01:1/2 frame rate 10:1/4 frame rate 11:1/8 frame rate

Bit[4:3]:

Average calculation window option 00:Use full frame 01:Use half frame 10:Use quarter frame 11:Use lower two-thirds Bit[2:1]:Reserved

Bit[0]:

Manual banding filter mode

COM12

Common Control 12

Bit[7]:

HREF option

0:No HREF when VREF is low 1:Always has HREF Bit[6:3]:Reserved

Bit[2]:Enable YUV average Bit[1:0]:

Reserved

3D COM1399RW

Common Control 13

Bit[7:6]:

Gamma selection for signal 00:No gamma function

01:Gamma used for Y channel only

10:Gamma used for Raw data before interpolation 11:Not allowed Bit[5]:Reserved

Bit[4]:Enable color matrix for RGB or YUV Bit[3]:

Enable Y channel delay option 0:Delay UV channel 1:Delay Y channel Bit[2:0]:

Output Y/UV delay

COM14

Common Control 14

Bit[7:2]:Reserved

Bit[1]:

Enable edge enhancement for YUV output (effective only for YUV/RGB, no use for Raw data)Bit[0]:

Edge enhancement option

0:Edge enhancement factor = EDGE [3:0]1:Edge enhancement factor = 2 x EDGE [3:0]

Table 5

Device Control Register List (Continued)

Address (Hex)

Default (Hex)

R/W

Description

OV9650

Color CMOS SXGA (1.3 MegaPixel) OmniPixel? C AMERA C HIP ?O

3F EDGE 88RW

Edge Enhancement Adjustment

Bit[7:4]:Edge enhancement threshold[3:0]

(see register COM22[7:6} for Edge threshold[5:4])Bit[3:0]:Edge enhancement factor

40COM15C0RW Common Control 15

Bit[7:6]:

Data format - output full range enable 0x:Output range: [10] to [F0]10:Output range: [01] to [FE]11:Output range: [00] to [FF]

Bit[5:4]:

RGB 555/565 option (must set COM7[2] high)x0:Normal RGB output 01:RGB 56511:RGB 555

Bit[3]:Swap R/B in RGB565/RGB555 format Bit[2:0]:

Reserved

COM16

Common Control 16

Bit[7:2]:Reserved

Bit[1]:Color matrix coefficient double option Bit[0]:

Reserved

42COM1708RW

Common Control 17

Bit[7:5]:Reserved

Bit[4]:Edge enhancement option Bit[3]:Reserved

Bit[2]:Select single frame out Bit[1]:Tri-state output Bit[0]:Reserved

43-4E RSVD XX –Reserved

4F MTX158RW Matrix Coefficient 150MTX248RW Matrix Coefficient 251MTX310RW Matrix Coefficient 352MTX428RW Matrix Coefficient 453MTX548RW Matrix Coefficient 554MTX670RW Matrix Coefficient 655MTX740RW Matrix Coefficient 756MTX840RW Matrix Coefficient 857

MTX9

Matrix Coefficient 9

MTXS

Matrix Coefficient Sign for coefficient 9 to 2

0:Plus 1:Minus 59-61

RSVD XX –

Reserved

Table 5

Device Control Register List (Continued)

Address (Hex)

Default (Hex)

R/W

Description