fangzhen4-后缀改为mdl,matlab打开

Model {
Name "fangzhen4"
Version 7.6
MdlSubVersion 0
GraphicalInterface {
NumRootInports 0
NumRootOutports 0
ParameterArgumentNames ""
ComputedModelVersion "1.2"
NumModelReferences 0
NumTestPointedSignals 0
}
SavedCharacterEncoding "GBK"
slprops.hdlmdlprops {
$PropName "HDLParams"
$ObjectID 1
Array {
Type "Cell"
Dimension 2
Cell "HDLSubsystem"
Cell "fangzhen4"
PropName "mdlProps"
}
}
SaveDefaultBlockParams on
ScopeRefreshTime 0.035000
OverrideScopeRefreshTime on
DisableAllScopes off
DataTypeOverride "UseLocalSettings"
DataTypeOverrideAppliesTo "AllNumericTypes"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
MaxMDLFileLineLength 120
Created "Wed Dec 21 10:46:34 2011"
Creator "Administrator"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%"
LastModifiedBy "Administrator"
ModifiedDateFormat "%"
LastModifiedDate "Wed Dec 21 14:30:51 2011"
RTWModifiedTimeStamp 246378646
ModelVersionFormat "1.%"
ConfigurationManager "None"
SampleTimeColors off
SampleTimeAnnotations off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ShowTestPointIcons on
ShowSignalResolutionIcons on
ShowViewerIcons on
SortedOrder off
ExecutionContextIcon off
ShowLinearizationAnnotations on
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
SimulationMode "normal"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
CovForceBlockReductionOff on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
CovReportOnPause on
CovModelRefEnable "Off"
CovExternalEMLEnable off
ExtModeBatchMode off
ExtModeEnableFloating on
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigDurationFloating "auto"
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off

ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
ShowModelReferenceBlockVersion off
ShowModelReferenceBlockIO off
Array {
Type "Handle"
Dimension 1
Simulink.ConfigSet {
$ObjectID 2
Version "1.10.0"
Array {
Type "Handle"
Dimension 9
Simulink.SolverCC {
$ObjectID 3
Version "1.10.0"
StartTime "0.0"
StopTime "0.1"
AbsTol "auto"
FixedStep "auto"
InitialStep "auto"
MaxNumMinSteps "-1"
MaxOrder 5
ZcThreshold "auto"
ConsecutiveZCsStepRelTol "10*128*eps"
MaxConsecutiveZCs "1000"
ExtrapolationOrder 4
NumberNewtonIterations 1
MaxStep "auto"
MinStep "auto"
MaxConsecutiveMinStep "1"
RelTol "1e-3"
SolverMode "Auto"
ConcurrentTasks off
Solver "ode23tb"
SolverName "ode23tb"
SolverJacobianMethodControl "auto"
ShapePreserveControl "DisableAll"
ZeroCrossControl "UseLocalSettings"
ZeroCrossAlgorithm "Nonadaptive"
AlgebraicLoopSolver "TrustRegion"
SolverResetMethod "Fast"
PositivePriorityOrder off
AutoInsertRateTranBlk off
SampleTimeConstraint "Unconstrained"
InsertRTBMode "Whenever possible"
}
Simulink.DataIOCC {
$ObjectID 4
Version "1.10.0"
Decimation "1"
ExternalInput "[t, u]"
FinalStateName "xFinal"
InitialState "xInitial"
LimitDataPoints on
MaxDataPoints "1000"
LoadExternalInput off
LoadInitialState off
SaveFinalState off
SaveCompleteFinalSimState off
SaveFormat "Array"
SaveOutput on
SaveState off
SignalLogging on
DSMLogging on
InspectSignalLogs off
SaveTime on
ReturnWorkspaceOutputs off
StateSaveName "xout"
TimeSaveName "tout"
OutputSaveName "yout"
SignalLoggingName "logsout"
DSMLoggingName "dsmout"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
ReturnWorkspaceOutputsName "out"
Refine "1"
}
Simulink.OptimizationCC {
$ObjectID 5
Version "1.10.0"
Array {
Type "Cell"
Dimension 8
Cell "BooleansAsBitfields"
Cell "PassReuseOutputArgsAs"
Cell "PassReuseOutputArgsThreshold"
Cell "ZeroExternalMemoryAtStartup"
Cell "ZeroInternalMemoryAtStartup"
Cell "OptimizeModelRefInitCode"
Cell "NoFixptDivByZeroProtection"
Cell "UseSpecifiedMinMax"
PropName "DisabledProps"
}
BlockReduction on
BooleanDataType on
ConditionallyExecuteInputs on
InlineParams off
UseIntDivNetSlope off
UseSpecifiedMinMax off
InlineInvariantSignals off
OptimizeBlockIOStorage on
BufferReuse on

EnhancedBackFolding off
StrengthReduction off
ExpressionFolding on
BooleansAsBitfields off
BitfieldContainerType "uint_T"
EnableMemcpy on
MemcpyThreshold 64
PassReuseOutputArgsAs "Structure reference"
ExpressionDepthLimit 2147483647
FoldNonRolledExpr on
LocalBlockOutputs on
RollThreshold 5
SystemCodeInlineAuto off
StateBitsets off
DataBitsets off
UseTempVars off
ZeroExternalMemoryAtStartup on
ZeroInternalMemoryAtStartup on
InitFltsAndDblsToZero off
NoFixptDivByZeroProtection off
EfficientFloat2IntCast off
EfficientMapNaN2IntZero on
OptimizeModelRefInitCode off
LifeSpan "inf"
MaxStackSize "Inherit from target"
BufferReusableBoundary on
SimCompilerOptimization "Off"
AccelVerboseBuild off
}
Simulink.DebuggingCC {
$ObjectID 6
Version "1.10.0"
RTPrefix "error"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
SignalInfNanChecking "none"
SignalRangeChecking "none"
ReadBeforeWriteMsg "UseLocalSettings"
WriteAfterWriteMsg "UseLocalSettings"
WriteAfterReadMsg "UseLocalSettings"
AlgebraicLoopMsg "warning"
ArtificialAlgebraicLoopMsg "warning"
SaveWithDisabledLinksMsg "warning"
SaveWithParameterizedLinksMsg "warning"
CheckSSInitialOutputMsg on
UnderspecifiedInitializationDetection "Classic"
MergeDetectMultiDrivingBlocksExec "none"
CheckExecutionContextPreStartOutputMsg off
CheckExecutionContextRuntimeOutputMsg off
SignalResolutionControl "UseLocalSettings"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
TimeAdjustmentMsg "none"
MaxConsecutiveZCsMsg "error"
MaskedZcDiagnostic "warning"
IgnoredZcDiagnostic "warning"
SolverPrmCheckMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskDSMMsg "error"
MultiTaskCondExecSysMsg "error"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
TasksWithSamePriorityMsg "warning"
SigSpecEnsureSampleTimeMsg "warning"
CheckMatrixSingularityMsg "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterUnderflowMsg "none"
ParameterPrecisionLossMsg "warning"
ParameterTunabilityLossMsg "warning"
FixptConstUnderflowMsg "none"
FixptConstOverflowMsg "none"
FixptConstPrecisionLossMsg "none"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
FcnCallInpInsideContextMsg "Use local settings"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SFcnCompatibilityMsg "none"
UniqueDataStoreMsg "none"
BusObj

ectLabelMismatch "warning"
RootOutportRequireBusObject "warning"
AssertControl "UseLocalSettings"
EnableOverflowDetection off
ModelReferenceIOMsg "none"
ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error"
ModelReferenceVersionMismatchMessage "none"
ModelReferenceIOMismatchMessage "none"
ModelReferenceCSMismatchMessage "none"
UnknownTsInhSupMsg "warning"
ModelReferenceDataLoggingMessage "warning"
ModelReferenceSymbolNameMessage "warning"
ModelReferenceExtraNoncontSigs "error"
StateNameClashWarn "warning"
SimStateInterfaceChecksumMismatchMsg "warning"
InitInArrayFormatMsg "warning"
StrictBusMsg "ErrorLevel1"
BusNameAdapt "WarnAndRepair"
NonBusSignalsTreatedAsBus "none"
LoggingUnavailableSignals "error"
BlockIODiagnostic "none"
SFUnusedDataAndEventsDiag "warning"
SFUnexpectedBacktrackingDiag "warning"
SFInvalidInputDataAccessInChartInitDiag "warning"
SFNoUnconditionalDefaultTransitionDiag "warning"
SFTransitionOutsideNaturalParentDiag "warning"
}
Simulink.HardwareCC {
$ObjectID 7
Version "1.10.0"
ProdBitPerChar 8
ProdBitPerShort 16
ProdBitPerInt 32
ProdBitPerLong 32
ProdBitPerFloat 32
ProdBitPerDouble 64
ProdBitPerPointer 32
ProdLargestAtomicInteger "Char"
ProdLargestAtomicFloat "None"
ProdIntDivRoundTo "Undefined"
ProdEndianess "Unspecified"
ProdWordSize 32
ProdShiftRightIntArith on
ProdHWDeviceType "32-bit Generic"
TargetBitPerChar 8
TargetBitPerShort 16
TargetBitPerInt 32
TargetBitPerLong 32
TargetBitPerFloat 32
TargetBitPerDouble 64
TargetBitPerPointer 32
TargetLargestAtomicInteger "Char"
TargetLargestAtomicFloat "None"
TargetShiftRightIntArith on
TargetIntDivRoundTo "Undefined"
TargetEndianess "Unspecified"
TargetWordSize 32
TargetTypeEmulationWarnSuppressLevel 0
TargetPreprocMaxBitsSint 32
TargetPreprocMaxBitsUint 32
TargetHWDeviceType "Specified"
TargetUnknown off
ProdEqTarget on
}
Simulink.ModelReferenceCC {
$ObjectID 8
Version "1.10.0"
UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
CheckModelReferenceTargetMessage "error"
EnableParallelModelReferenceBuilds off
ParallelModelReferenceErrorOnInvalidPool on
ParallelModelReferenceMATLABWorkerInit "None"
ModelReferenceNumInstancesAllowed "Multi"
PropagateVarSize "Infer from blocks in model"
ModelReferencePassRootInputsByReference on
ModelReferenceMinAlgLoopOccurrences off
PropagateSignalLabelsOutOfModel off
SupportModelReferenceSimTargetCustomCode off
}
Simulink.SFSimCC {
$ObjectID 9
Version "1.10.0"
SFSimEnableDebug on
SFSimOverflowDetection on
SFSimEcho on
SimBlas on
SimCtrlC on
SimExtrinsic on
SimIntegrity on
SimUseLoca

lCustomCode off
SimParseCustomCode on
SimBuildMode "sf_incremental_build"
}
Simulink.RTWCC {
$BackupClass "Simulink.RTWCC"
$ObjectID 10
Version "1.10.0"
Array {
Type "Cell"
Dimension 7
Cell "IncludeHyperlinkInReport"
Cell "GenerateTraceInfo"
Cell "GenerateTraceReport"
Cell "GenerateTraceReportSl"
Cell "GenerateTraceReportSf"
Cell "GenerateTraceReportEml"
Cell "GenerateSLWebview"
PropName "DisabledProps"
}
SystemTargetFile "grt.tlc"
GenCodeOnly off
MakeCommand "make_rtw"
GenerateMakefile on
TemplateMakefile "grt_default_tmf"
GenerateReport off
SaveLog off
RTWVerbose on
RetainRTWFile off
ProfileTLC off
TLCDebug off
TLCCoverage off
TLCAssert off
ProcessScriptMode "Default"
ConfigurationMode "Optimized"
ConfigAtBuild off
RTWUseLocalCustomCode off
RTWUseSimCustomCode off
IncludeHyperlinkInReport off
LaunchReport off
TargetLang "C"
IncludeBusHierarchyInRTWFileBlockHierarchyMap off
IncludeERTFirstTime off
GenerateTraceInfo off
GenerateTraceReport off
GenerateTraceReportSl off
GenerateTraceReportSf off
GenerateTraceReportEml off
GenerateCodeInfo off
GenerateSLWebview off
RTWCompilerOptimization "Off"
CheckMdlBeforeBuild "Off"
CustomRebuildMode "OnUpdate"
Array {
Type "Handle"
Dimension 2
Simulink.CodeAppCC {
$ObjectID 11
Version "1.10.0"
Array {
Type "Cell"
Dimension 21
Cell "IgnoreCustomStorageClasses"
Cell "IgnoreTestpoints"
Cell "InsertBlockDesc"
Cell "InsertPolySpaceComments"
Cell "SFDataObjDesc"
Cell "MATLABFcnDesc"
Cell "SimulinkDataObjDesc"
Cell "DefineNamingRule"
Cell "SignalNamingRule"
Cell "ParamNamingRule"
Cell "InlinedPrmAccess"
Cell "CustomSymbolStr"
Cell "CustomSymbolStrGlobalVar"
Cell "CustomSymbolStrType"
Cell "CustomSymbolStrField"
Cell "CustomSymbolStrFcn"
Cell "CustomSymbolStrFcnArg"
Cell "CustomSymbolStrBlkIO"
Cell "CustomSymbolStrTmpVar"
Cell "CustomSymbolStrMacro"
Cell "ReqsInCode"
PropName "DisabledProps"
}
ForceParamTrailComments off
GenerateComments on
IgnoreCustomStorageClasses on
IgnoreTestpoints off
IncHierarchyInIds off
MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
MATLABFcnDesc off
IncDataTypeInIds off
MangleLength 1
CustomSymbolStrGlobalVar "$R$N$M"
CustomSymbolStrType "$N$

R$M"
CustomSymbolStrField "$N$M"
CustomSymbolStrFcn "$R$N$M$F"
CustomSymbolStrFcnArg "rt$I$N$M"
CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
InsertPolySpaceComments off
SimulinkBlockComments on
MATLABSourceComments off
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
UseSimReservedNames off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 12
Version "1.10.0"
Array {
Type "Cell"
Dimension 16
Cell "GeneratePreprocessorConditionals"
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "ModelStepFunctionPrototypeControlCompliant"
Cell "CPPClassGenCompliant"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
Cell "PortableWordSizes"
PropName "DisabledProps"
}
TargetFcnLib "ansi_tfl_table_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
TargetFunctionLibrary "ANSI_C"
UtilityFuncGeneration "Auto"
ERTMultiwordTypeDef "System defined"
ERTCodeCoverageTool "None"
ERTMultiwordLength 256
MultiwordLength 2048
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
ParMdlRefBuildCompliant on
CompOptLevelCompliant on
IncludeMdlTerminateFcn on
GeneratePreprocessorConditionals "Disable all"
CombineOutputUpdateFcns off
CombineSignalStateStructs off
SuppressErrorStatus off
ERTFirstTimeCompliant off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
SupportVariableSizeSignals off
EnableShiftOperators on
ParenthesesLevel "Nominal"
PortableWordSizes off
ModelStepFunctionPrototypeControlCompliant off
CPPClassGenCompliant off
AutosarCompliant off
UseMalloc off
ExtMode off

ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
ExtModeIntrfLevel "Level1"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
hdlcoderui.hdlcc {
$ObjectID 13
Version "1.10.0"
Description "HDL Coder custom configuration component"
Name "HDL Coder"
Array {
Type "Cell"
Dimension 1
Cell ""
PropName "HDLConfigFile"
}
HDLCActiveTab "0"
}
PropName "Components"
}
Name "Configuration"
CurrentDlgPage "Solver"
ConfigPrmDlgPosition " [ 136, 117, 1016, 747 ] "
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 2
}
BlockDefaults {
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
BlockRotation 0
BlockMirror off
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
BlockParameterDefaults {
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
}
System {
Name "fangzhen4"
Location [-23, 124, 1117, 856]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
SIDHighWatermark "14"
Block {
BlockType Reference
Name "AC "
SID "1"
Ports [0, 0, 0

, 0, 0, 1, 1]
Position [43, 180, 67, 215]
BlockRotation 270
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Electrical\nSources/AC Voltage Source"
SourceType "AC Voltage Source"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
Amplitude "100"
Phase "0"
Frequency "50"
SampleTime "0"
Measurements "None"
}
Block {
BlockType Reference
Name "C1"
SID "5"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [336, 175, 364, 245]
BlockRotation 270
BlockMirror on
NamePlacement "alternate"
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "C"
Resistance "1"
Inductance "1e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "0.01"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "C2"
SID "7"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [661, 195, 689, 265]
BlockRotation 270
BlockMirror on
NamePlacement "alternate"
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "C"
Resistance "1"
Inductance "1e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "50e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {

BlockType Reference
Name "Discrete\nPWM Generator"
SID "10"
Ports [0, 1]
Position [625, 84, 690, 136]
BlockMirror on
LibraryVersion "1.633"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib_extras/Discrete \nControl Blocks/Discrete\nPWM Generator"
SourceType "Discrete PWM Generator"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
GeneratorMode "2-arm bridge (4 pulses)"
Fc "1080"
Ts "5e-6"
Internal on
mIndex "0.4"
Freq "10"
Phase "0"
}
Block {
BlockType Reference
Name "L1"
SID "4"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [250, 146, 320, 174]
NamePlacement "alternate"
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1"
Inductance "1e-4"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "L2"
SID "6"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [535, 166, 605, 194]
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "1"
Inductance "0.01"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements

"None"
}
Block {
BlockType Reference
Name "R"
SID "8"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [731, 195, 759, 265]
BlockRotation 270
BlockMirror on
NamePlacement "alternate"
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "R"
Resistance "10"
Inductance "1e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Scope
Name "Scope"
SID "9"
Ports [3]
Position [900, 190, 940, 270]
Floating off
Location [9, 52, 1161, 833]
Open off
NumInputPorts "3"
List {
ListType AxesTitles
axes1 "%"
axes2 "%"
axes3 "%"
}
YMin "-100~124.5~-55"
YMax "100~131.5~25"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Reference
Name "Universal Bridge"
SID "2"
Ports [0, 0, 0, 0, 0, 2, 2]
Position [155, 142, 210, 218]
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Power\nElectronics/Universal Bridge"
SourceType "Universal Bridge"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
Arms "2"
SnubberResistance "1e5"
SnubberCapacitance "inf"
Device "Diodes"
Ron "1e-3"
Lon "0"
ForwardVoltages "[ 0 0 ]"
ForwardVoltage "0"
GTOparameters "[ 10e-6 , 20e-6 ]"
IGBTparameters "[ 1e-6 , 2e-6 ]"
Measurements "None"
Measurements_2 "None"
converterType "Rectifier"
}
Block {
BlockType

Reference
Name "Universal Bridge1"
SID "3"
Ports [1, 0, 0, 0, 0, 2, 2]
Position [435, 142, 490, 218]
BlockMirror on
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Power\nElectronics/Universal Bridge"
SourceType "Universal Bridge"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
Arms "2"
SnubberResistance "1e5"
SnubberCapacitance "inf"
Device "IGBT / Diodes"
Ron "1e-3"
Lon "0"
ForwardVoltages "[ 0 0 ]"
ForwardVoltage "0"
GTOparameters "[ 10e-6 , 20e-6 ]"
IGBTparameters "[ 1e-6 , 2e-6 ]"
Measurements "None"
Measurements_2 "None"
converterType "Rectifier"
}
Block {
BlockType Reference
Name "powergui"
SID "14"
Ports []
Position [100, 280, 166, 319]
Priority "1"
LibraryVersion "1.1923"
UserDataPersistent on
FontName "Verdana"
SourceBlock "powerlib/powergui"
SourceType "PSB option menu block"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
SimulationMode "Continuous"
SampleTime "50e-6"
frequency "60"
SPID off
DisableSnubberDevices off
DisableRonSwitches off
DisableVfSwitches off
SwTol "0"
Interpol off
frequencyindice "50"
echomessages off
HookPort off
DisplayEquations off
FunctionMessages off
EnableUseOfTLC off
x0status "blocks"
RestoreLinks "warning"
ResistiveCurrentMeasurement off
Ylog off
Xlog on
ShowGrid off
save off
variable "ZData"
ZoomFFT off
StartTime "0.0"
cycles "1"
DisplayStyle "1"
FreqAxis off
Max

Frequency "1000"
frequencyindicesteady "1"
display off
methode off
}
Block {
BlockType Reference
Name "ud"
SID "12"
Ports [0, 1, 0, 0, 0, 2]
Position [378, 295, 402, 320]
BlockRotation 270
BlockMirror on
NamePlacement "alternate"
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Measurements/Voltage Measurement"
SourceType "Voltage Measurement"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "ui"
SID "11"
Ports [0, 1, 0, 0, 0, 2]
Position [150, 33, 175, 57]
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Measurements/Voltage Measurement"
SourceType "Voltage Measurement"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "uo"
SID "13"
Ports [0, 1, 0, 0, 0, 2]
Position [810, 218, 835, 242]
LibraryVersion "1.1923"
DialogController "POWERSYS.PowerSysDialog"
FontName "Verdana"
FontSize 11
SourceBlock "powerlib/Measurements/Voltage Measurement"
SourceType "Voltage Measurement"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorCondit

ionals off
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Line {
SrcBlock "Discrete\nPWM Generator"
SrcPort 1
Points [-55, 0; 0, 45]
DstBlock "Universal Bridge1"
DstPort 1
}
Line {
LineType "Connection"
SrcBlock "AC "
SrcPort RConn1
Points [0, -5; 40, 0]
Branch {
ConnectType "DEST_SRC"
DstBlock "Universal Bridge"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
Points [0, -120]
DstBlock "ui"
DstPort LConn1
}
}
Line {
LineType "Connection"
SrcBlock "AC "
SrcPort LConn1
Points [0, 5; 55, 0]
Branch {
ConnectType "DEST_SRC"
Points [20, 0; 0, -35]
DstBlock "Universal Bridge"
DstPort LConn2
}
Branch {
ConnectType "DEST_SRC"
Points [0, -185]
DstBlock "ui"
DstPort LConn2
}
}
Line {
SrcBlock "ui"
SrcPort 1
Points [705, 0]
DstBlock "Scope"
DstPort 1
}
Line {
LineType "Connection"
Points [675, 180; 70, 0]
Branch {
ConnectType "SRC_DEST"
SrcBlock "L2"
SrcPort RConn1
Points [55, 0]
}
Branch {
ConnectType "SRC_SRC"
DstBlock "C2"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
DstBlock "R"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
Points [50, 0]
DstBlock "uo"
DstPort LConn1
}
}
Line {
LineType "Connection"
SrcBlock "Universal Bridge1"
SrcPort LConn1
DstBlock "L2"
DstPort LConn1
}
Line {
LineType "Connection"
Points [675, 280; 70, 0]
Branch {
ConnectType "SRC_DEST"
SrcBlock "Universal Bridge1"
SrcPort LConn2
Points [55, 0; 0, 75; 115, 0]
}
Branch {
ConnectType "SRC_SRC"
DstBlock "C2"
DstPort RConn1
}
Branch {
ConnectType "DEST_SRC"
DstBlock "R"
DstPort RConn1
}
Branch {
ConnectType "DEST_SRC"
Points [50, 0]
DstBlock "uo"
DstPort LConn2
}
}
Line {
LineType "Connection"
Points [350, 160; 30, 0]
Branch {
ConnectType "SRC_DEST"
SrcBlock "L1"
SrcPort RConn1
Points [15, 0]
}
Branch {
ConnectType "SRC_SRC"
DstBlock "C1"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
DstBlock "Universal Bridge1"
DstPort RConn1
}
Branch {
ConnectType "DEST_SRC"
Labels [0, 0]
Points [0, 120]
DstBlock "ud"
DstPort LConn1
}
}
Line {
LineType "Connection"
SrcBlock "Universal Bridge"
SrcPort

RConn1
DstBlock "L1"
DstPort LConn1
}
Line {
LineType "Connection"
Points [350, 270; 50, 0]
Branch {
ConnectType "SRC_DEST"
SrcBlock "Universal Bridge"
SrcPort RConn2
Points [90, 0; 0, 70; 35, 0]
}
Branch {
ConnectType "SRC_DEST"
SrcBlock "C1"
SrcPort RConn1
Points [0, 10]
}
Branch {
ConnectType "DEST_SRC"
Points [20, 0]
DstBlock "Universal Bridge1"
DstPort RConn2
}
Branch {
ConnectType "DEST_SRC"
Points [0, 10]
DstBlock "ud"
DstPort LConn2
}
}
Line {
SrcBlock "ud"
SrcPort 1
Points [495, 0]
DstBlock "Scope"
DstPort 2
}
Line {
SrcBlock "uo"
SrcPort 1
Points [30, 0; 0, 25]
DstBlock "Scope"
DstPort 3
}
}
}