文档库 最新最全的文档下载
当前位置:文档库 › P4C1298-25PMB中文资料

P4C1298-25PMB中文资料

Document # SRAM135 REV OR

DESCRIPTION

The P4C1298/L are a 262,144-bit ultra high speed static RAM organized as 64K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 μA from a 2.0V supply.

Data Retention with 2.0V Supply Three-State Outputs

TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved)– 28-Pin 300 mil DIP, SOJ – 28-Pin 350x550 mil LCC

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)– 15/20/25/35 ns (Commercial/Industrial)– 15/20/25/35/45 ns (Military)Low Power

Single 5V±10% Power Supply

Output Enable & Chip Enable control functions

FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION

P4C1298/P4C1298L

ULTRA HIGH SPEED 64K x 4STATIC CMOS RAM

Access times as fast as 15 nanoseconds are available,permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption.

The P4C1298 is available in a 28-pin 300 mil DIP or SOJ, as well as a 28-pin 350x500 mil LCC package, providing

excellent board level densities.

DIP (P5, C5)SOJ (J5)

LCC (L5)

P4C1298/L

MAXIMUM RATINGS (1)

Symbol Parameter Value Unit V CC

Power Supply Pin with –0.5 to +7V

Respect to GND Terminal Voltage with –0.5 to V TERM Respect to GND V CC +0.5V (up to 7.0V)

T A

Operating Temperature

–55 to +125

°C

Symbol Parameter Value Unit T BIAS Temperature Under –55 to +125°C Bias

T STG Storage Temperature –65 to +150

°C P T Power Dissipation 1.0W I OUT

DC Output Current

50

mA

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Industrial Commercial

Grade(2)Ambient Temperature GND V CC –40°C to +85°C 0°C to +70°C

0V 0V

5.0V ± 10%5.0V ± 10%

Symbol C IN C OUT

Parameter Input Capacitance Output Capacitance

Conditions V IN = 0V V OUT = 0V

57

Unit pF pF

CAPACITANCES (4)

V CC = 5.0V, T A = 25°C, f = 1.0MHz DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage (2)Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow.

3.Transient inputs with V IL and I IL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns.

4.This parameter is sampled and not 100% tested.

Typ. I SB Standby Power Supply

Current (TTL Input Levels)CE ≥ V IH

V CC = Max ., f = Max., Outputs Open

___4010mA mA ___CE ≥ V HC

V CC = Max., f = 0, Outputs Open V IN ≤ V LC or V IN ≥ V HC

Standby Power Supply Current

(CMOS Input Levels)

I SB1

Symbol V IH V IL V HC V LC V CD V OL V OH I LI I LO Parameter

Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load)

Output High Voltage (TTL Load)

Input Leakage Current

Output Leakage Current Test Conditions

V CC = Min., I IN = 18 mA I OL = +8 mA, V CC = Min.I OH = –4 mA, V CC = Min.V CC = Max.V IN = GND to V CC V CC = Max., CE = V IH V OUT = GND to V CC

P4C1298Min 2.2–0.5(3)V CC –0.2–0.5(3)

2.4

–5–5Max

V CC +0.50.8

V CC +0.50.2–1.20.4

+5+5Unit

V V V V V V V

μA

μA Military -55°C to +125°C 0V 5.0V ± 10%___2010___P4C1298L

Min 2.2–0.5(3)

V CC –0.2–0.5(3)

2.4

–10–10Max

V CC +0.50.8V CC +0.50.2–1.20.4

+10+10___

20mA ___N/A Mil

Ind/Comm

Mil

Ind/Comm

10

mA

___

N/A

___

*V CC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = V IL

DATA RETENTION CHARACTERISTICS (P4C1298L ONLY)

Symbol V DR I CCDR t CDR t R ?

Parameter

V CC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time

Test Conditions

CE ≥ V CC –0.2V,V IN ≥ V CC –0.2V or V IN ≤ 0.2V Min 2.0

0t RC §

Typ.*V CC =

2.0V

3.0V

10

15

Max V CC = 2.0V 3.0V

1000

2000

Unit V μA ns ns

DATA RETENTION WAVEFORM

*T A = +25°C

§t RC = Read Cycle Time

?

This parameter is guaranteed but not tested.

I CC

Symbol

Parameter

Temperature

Range Dynamic Operating Current*

Commercial Industrial –15–20–25–35Unit mA mA POWER DISSIPATION CHARACTERISTICS VS. SPEED

115120135160160125115110Military

mA

120

120

150

160

P4C1298/L

AC CHARACTERISTICS—READ CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)(2)

TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)

Sym.t RC t AA t AC t OH t LZ t HZ t PU t PD

Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Chip Enable to Power Up Time Chip Disable to Power Down Time

-15Min 15

33

Max 1515815

-20Min 20

33

0Max

2020

1020

-25Min 25

33

Max 2525

1525

-35

Min

35

33

Max 3535

1535

Unit ns ns ns ns ns ns ns ns

-45Min 45

33

Max

45452045

t OE Output Enable Low to Data Valid ns TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)

t OLZ t OHZ Output Enable Low to Low Z Output Enable High to High Z 810

15

25

30ns ns 0

000

99

15

20

20

Notes:

5.CE is LOW and WE is HIGH for READ cycle.

6.WE is HIGH, and address must be valid prior to or coincident with CE

transition LOW.7.Transition is measured ±200mV from steady state voltage prior to

change with specified loading in Figure 1. This parameter is sampled and not 100% tested.

8.Read Cycle Time is measured from the last valid address to the first

transitioning address.

TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)

(5,6)

P4C1298/L

12.Write Cycle Time is measured from the last valid address to the first

transition address.

13.Transition is measured ±200mV from steady state voltage prior to

change with specified loading in Figure 1. This parameter is sampled and not 100% tested.

Notes:

9.CE and WE must be LOW for WRITE cycle.10. OE is LOW for this WRITE cycle.

11.If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (9)

AC CHARACTERISTICS - WRITE CYCLE

(V CC = 5V ± 10%, All Temperature Ranges)(2)

Input Pulse Levels GND to 3.0V

Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V

Output Load

See Figures 1 and 2

Mode CE WE Output Power Standby H X High Z Standby Read L H D OUT Active Write

L

L

D IN

Active

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P4C1298, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 μF high

frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50?test environment should be terminated into a 50? load with 1.73V (Thevenin Voltage) at the comparator input, and a 116? resistor must be used in series with D OUT to match 166? (Thevenin Resistance).

Figure 1. Output Load

Figure 2. Thevenin Equivalent

AC TEST CONDITIONS

TRUTH TABLE

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)

(9,10)

P4C1298/L

ORDERING INFORMATION

SELECTION GUIDE

The P4C1298 is available in the following temperature, speed and package options.

SOJ SMALL OUTLINE IC PACKAGE

PLASTIC DUAL IN-LINE PACKAGE

P4C1298/L

RECTANGULAR LEADLESS CHIP CARRIER

SIDEBRAZED DUAL IN-LINE PACKAGE

REVISIONS

DOCUMENT NUMBER:SRAM135

DOCUMENT TITLE:P4C1298/P4C1298L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM

REV.ISSUE

DATE

ORIG. OF

CHANGE

DESCRIPTION OF CHANGE

OR Apr-07JDB New Data Sheet

相关文档