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L6599D中文资料

May 2006 Rev 11/36

L6599

High-voltage resonant controller

Features

■50% duty cycle, variable frequency control of resonant half-bridge ■High-accuracy oscillator

■Up to 500kHz operating frequency

■Two-level OCP: frequency-shift and latched shutdown

■Interface with PFC controller ■Latched disable input

■Burst-mode operation at light load ■Input for power-ON/OFF sequencing or brownout protection

■Non-linear soft-start for monotonic output voltage rise

■

600V-rail compatible high-side gate driver with integrated bootstrap diode and high dV/dt immunity

■-300/800mA high-side and low-side gate drivers with UVLO pull-down ■

DIP-16, SO-16N packages

Applications

■LCD & PDP TV

■Desktop PC, entry-level server ■Telecom SMPS

■

AC-DC adapter, open frame SMPS

Order code

Part number Package Packaging L6599D SO-16N T ube L6599TR SO-16N Tape and reel

L6599N

DIP-16

T ube

https://www.wendangku.net/doc/113100535.html,

Contents L6599

Contents

1Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3Typical system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.2Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.3Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.4Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.5Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.6Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.7Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.8Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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L6599Device description

3/36

1 Device description

The L6599 is a double-ended controller specific for the resonant half-bridge topology. It

provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON 180° out-of-phase for exactly the same time.

Output voltage regulation is obtained by modulating the operating frequency. A fixed dead-time inserted between the turn-OFF of one switch and the turn-ON of the other one guarantees soft-switching and enables high-frequency operation.

To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode.

The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.

At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well.

The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep converter's input consumption to a minimum.

IC's functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart.

A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP .

An interface with the PFC controller is provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation.

Pin Settings L6599

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2 Pin Settings

2.1 Connection

2.2 Functions

Table 1.

Pin functions

Name

Function

C SS

Soft start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4)

that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns OFF (V CC < UVLO, LINE < 1.25V or > 6V , DIS > 1.85V , ISEN > 1.5V , DELAY > 3.5V) to make sure it will be soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8V , as long as it stays above 0.75V .

2DELAY

Delayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set both the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the ISEN pin exceeds 0.8V the capacitor is charged by an internal 150μA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2V , the soft start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150μA is kept always on. As the voltage on the pin exceeds 3.5V the IC stops switching and the internal generator is turned OFF , so that the voltage on the pin will decay because of the external resistor. The IC will be soft-restarted as the voltage drops below 0.3V . In this way, under short circuit conditions, the converter will work intermittently with very low input average power.

3CF

Timing capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter.

L6599Pin Settings

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4RFmin

Minimum oscillator frequency setting. This pin provides a precise 2V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. T o close the feedback loop that regulates the converter output voltage by

modulating the oscillator frequency, the phototransistor of an optocoupler will be connected to this pin through a resistor. The value of this resistor will set the maximum operating

frequency. An R-C series connected from this pin to GND sets frequency shift at start-up to prevent excessive energy inrush (soft-start).

5STBY

Burst-mode operation threshold. The pin senses some voltage related to the feedback

control, which is compared to an internal reference (1.25V). If the voltage on the pin is lower than the reference, the IC enters an idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50mV . Soft-start is not invoked. This function realizes burst-mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst-mode is not used.

6ISEN

Current sense input. The pin senses the primary current though a sense resistor or a

capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; hence the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8V threshold (with 50mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases hence limiting the power throughput. Under output short circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5V latches the device off and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.

7LINE

Line sensing input. The pin is to be connected to the high-voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.25V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25V . The comparator is provided with current hysteresis: an internal 15μA current generator is ON as long as the voltage applied at the pin is below 1.25V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal zener. Activating the zener causes the IC to shut down (not latched). Bias the pin between 1.25 and 6V if the function is not used.

8DIS

Latched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 1.85V , shuts the IC down and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the V CC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.

PFC_STOP

Open-drain ON/OFF control of PFC controller. This pin, normally open, is intended for

stopping the PFC controller, for protection purpose or during burst-mode operation. It goes low when the IC is shut down by DIS > 1.85V , ISEN > 1.5V , LINE > 6V and STBY < 1.25V .

The pin is pulled low also when the voltage on pin DELAY exceeds 2V and goes back open as the voltage falls below 0.3V . During UVLO, it is open. Leave the pin unconnected if not used.

GND

Chip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.

Table 1.

Pin functions

Typical system block diagram L6599

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3 Typical system block diagram

Figure 2.

Typical system block diagram

LVG

Low-side gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND during UVLO.

V CC Supply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1μF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC.

13N.C.High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and ease compliance with safety regulations (creepage distance) on the PCB.

OUT

High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.

15HVG

High-side floating gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.

16VBOOT

High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive. This patented structure replaces the normally used external diode.

Table 1.

Pin functions

L6599Electrical data

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4 Electrical data

4.1 Maximum ratings

Note:ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V

4.2 Thermal data

Table 2.

Absolute maximum ratings

Symbol Pin Parameter

Value Unit V BOOT 16 Floating supply voltage -1 to 618 V V OUT 14 Floating ground voltage -3 to V BOOT -18

V dV OUT /dt 14 Floating ground max. slew rate 50

V/ns

V CC 12 IC Supply voltage (I CC ≤ 25 mA) Self-limited V V PFC_STOP 9 Maximum voltage (pin open) -0.3 to V CC V I PFC_STOP 9 Maximum sink current (pin low)

Self-limited

V LINEmax 7

Maximum pin voltage (Ipin ≤ 1mA) Self-limited V

I RFmin

4 Maximum source current 2 mA 1 to 6, 8 Analog inputs & outputs

-0.3 to 5

Table 3.

Thermal data

Symbol Description

Value Unit R thJA Max. thermal resistance junction to ambient (DIP16)80°C/W Max. thermal resistance junction to ambient (SO16)120T STG Storage temperature range

-55 to 150°C T J Junction operating temperature range

-40 to 150

°C P TOT

Recommended max. power dissipation @T A = 70°C (DIP16) 1 W

Recommended max. power dissipation @T A = 50°C (SO16)

0.83

5 Electrical

characteristics

T J = 0 to 105°C, V CC = 15V, V BOOT = 15V, C HVG = C LVG = 1nF; C F = 470pF;

R RFmin = 12k?; unless otherwise specified.

Table 4.Electrical characteristics

Symbol Parameter Test

condition

Min Typ Max Unit IC supply voltage

V CC Operating range After device turn-on8.85 16 V

V CC(ON)Turn-ON threshold Voltage rising10 10.7 11.4 V

V CC(OFF)Turn-OFF threshold Voltage

falling 7.45 8.15 8.85 V Hys Hysteresis 2.55 V

V Z V CC clamp voltage Iclamp = 10mA 16 17 17.9 V Supply current

I start-up Start-up current Before device turn-ON

V CC = V CC(ON) - 0.2V

200 250 μA

I q Quiescent current Device ON, V STBY = 1V 1.5 2 mA

I op Operating current Device ON,

V STBY = V RFmin 3.5 5 mA

I q Residual consumption V DIS> 1.85V or V DELAY

> 3.5V or V LINE < 1.25 V

or V LINE = V clamp

300 400 μA

High-side floating gate-drive supply

I LKBOOT V BOOT pin leakage

current

V BOOT= 580V 5 μA

I LKOUT OUT pin leakage current V

OUT= 562V 5 μA

r DS(on)Synchronous bootstrap

diode ON-resistance

V LVG= High 150 ?Overcurrent comparator

I ISEN Input bias current V ISEN = 0 to V ISENdis-1 μA

t LEB Leading edge blanking After V HVG and V LVG

low-to-high transition

250 ns

V ISENx Frequency shift

threshold Voltage rising

(1)0.76 0.8 0.84 V

Hysteresis Voltage

falling 50 mV V ISENdis Latch OFF threshold Voltage rising (1) 1.44 1.5 1.56 V

td(H-L)Delay to output 300400 ns

8/36

9/36

Symbol Parameter Test condition Min Typ Max Unit

Line sensing V th Threshold voltage Voltage rising or falling

(1)

1.2 1.25 1.3 V I Hyst Current hysteresis V CC > 5V , V LINE = 0.3V 12 15 18 μA

V clamp Clamp level

I LINE = 1mA

6 8 V

DIS function

I DIS Input bias current V DIS = 0 to V th -1 μA

V th Disable threshold

Voltage rising (1)

1.77 1.85 1.93 V

Oscillator

Output duty cycle

Both HVG and LVG

50 52 %

f osc

Oscillation frequency

58.2 60 61.8

kHz

R RFmin = 2.7 k ?240 250 260

Maximum

recommended

500

kHz T D Dead-time Between HVG and LVG

0.2

0.3 0.4

μs V CFp Peak value 3.9 V V CFv Valley value 0.9

V REF Voltage reference at pin 4

(1)

1.92 2

2.08 V

K M Current mirroring ratio 1

A/A RF MIN

Timing resistor range

100

k ?

PFC_STOP function

I leak High level leakage current

V PFC_STOP = V CC ,V DIS = 0V 1 μA

V L

Low saturation level

I PFC_STOP =1mA,V DIS = 2V

0.2 V

Soft-start function

I leak

Open-state current

V(Css) = 2V

0.5

μA R D

ischarge resistance V ISEN > V ISENx 120

Standby function

I DIS Input Bias Current V DIS = 0 to V th -1 μA

V th

Disable threshold

Voltage falling (1) 1.2 1.25 1.3 V

Hys Hysteresis

Voltage rising

Table 4.

Electrical characteristics

10/36

Symbol Parameter Test condition Min Typ

Max Unit

Delayed shutdown function

I leak Open-state current V(DELAY) = 0 0.5 μA

I CHARGE Charge current V DELAY = 1V , V ISEN = 0.85V 100 150 200 μA Vth 1

Threshold for forced

operation at max. frequency

Voltage rising (1)

1.92 2

2.08 V

Vth 2Shutdown threshold Voltage rising (1) 3.3 3.5 3.7 V Vth 3

Restart threshold

Voltage falling (1)

0.25 0.3 0.35 V

Low - side gate driver (voltages referred to GND)

V LVGL Output low voltage I sink = 200mA 1.5 V

V LVGH Output high voltage I source = 5mA

12.8 13.3 V I sourcepk Peak source current -0.3 A I sinkpk Peak sink current 0.8

A t f Fall time 30 ns t r

Rise time 60

UVLO saturation

V CC = 0 to V CC(ON),

I sink = 2mA 1.1 V

High-side gate driver (voltages referred to OUT)V HVGL Output low voltage I sink = 200 mA 1.5 V

V HVGH Output high voltage I source = 5 mA

12.8 13.3 V I sourcepk Peak source current -0.3 A I sinkpk Peak sink current 0.8

A t f Fall time 30 ns t r

Rise time

60 ns HVG-OUT pull-down

k ?

1.Values traking each other

Table 4.

Electrical characteristics

11/36

6 Typical electrical performance

Figure 3.

Device consumption vs

supply voltage

Figure 4.

IC consumption vs junction temperature

Figure 5.

V CC clamp voltage vs junction temperature

Figure 6.

UVLO thresholds vs junction temperature

12/36

Figure 7.

Oscillator frequency vs

junction temperature Figure 8.

Dead-time vs

junction temperature

Figure 9.

Oscillator frequency vs

timing components Figure 10.Oscillator ramp vs

junction temperature

13/36

Figure 11.Reference voltage vs

junction temperature

Figure 12.Current mirroring ratio vs

junction temperature

Figure 13.OCP delay source current vs

junction temperature Figure 14.OCP delay thresholds vs

junction temperature

14/36

Figure 15.Standby thresholds vs

junction temperature

Figure 16.Current sense thresholds vs

junction temperature

Figure 17.Line thresholds vs

junction temperature

Figure 18.Line source current vs

junction temperature

Figure https://www.wendangku.net/doc/113100535.html,tched disable threshold vs

junction temperature

7 Application

information

The L6599 is an advanced double-ended controller specific for resonant half-bridge

topology. In these converters the switches (MOSFETs) of the half-bridge leg are alternately

switched on and OFF (180° out-of-phase) for exactly the same time. This is commonly

referred to as operation at "50% duty cycle", although the real duty cycle, that is the ratio of

the ON-time of either switch to the switching period, is actually less than 50%. The reason is

that there is an internally fixed dead-time T D, inserted between the turn-OFF of either

MOSFET and the turn-ON of the other one, where both MOSFETs are OFF. This dead- time

is essential in order for the converter to work correctly: it will ensure soft-switching and

enable high-frequency operation with high efficiency and low EMI emissions.

To perform converter's output voltage regulation the device is able to operate in different

modes (Figure20), depending on the load conditions:

1.Variable frequency at heavy and medium/light load. A relaxation oscillator (see

"Oscillator" section for more details) generates a symmetrical triangular waveform,

which MOSFETs' switching is locked to. The frequency of this waveform is related to a

current that will be modulated by the feedback circuitry. As a result, the tank circuit

driven by the half-bridge will be stimulated at a frequency dictated by the feedback loop

to keep the output voltage regulated, thus exploiting its frequency-dependent transfer

characteristics.

2. Burst-mode control with no or very light load. When the load falls below a value, the

converter will enter a controlled intermittent operation, where a series of a few

switching cycles at a nearly fixed frequency are spaced out by long idle periods where

both MOSFETs are in OFF-state. A further load decrease will be translated into longer

idle periods and then in a reduction of the average switching frequency. When the

converter is completely unloaded, the average switching frequency can go down even

to few hundred Hz, thus minimizing magnetizing current losses as well as all frequency-

related losses and making it easier to comply with energy saving recommendations.

Figure 20.Multi-mode operation

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7.1 Oscillator

The oscillator is programmed externally by means of a capacitor (CF), connected from pin 3 (CF) to ground, that will be alternately charged and discharged by the current defined with the network connected to pin 4 (RF min ). The pin provides an accurate 2V reference with about 2mA source capability and the higher the current sourced by the pin is, the higher the oscillator frequency will be. The block diagram of Figure 21 shows a simplified internal circuit that explains the operation.

The network that loads the RFmin pin generally comprises three branches:1. A resistor RF min connected between the pin and ground that determines the minimum operating frequency;

A resistor RF max connected between the pin and the collector of the (emitter-grounded) phototransistor that transfers the feedback signal from the secondary side back to the primary side; while in operation, the phototransistor will modulate the current through this branch - hence modulating the oscillator frequency - to perform output voltage regulation; the value of RF max determines the maximum frequency the half-bridge will be operated at when the phototransistor is fully saturated;

An R-C series circuit (C SS + R SS ) connected between the pin and ground that enables to set up a frequency shift at start-up (see Chapter 7.3: Soft-start ). Note that the contribution of this branch is zero during steady-state operation.

The following approximate relationships hold for the minimum and the maximum oscillator

frequency respectively:

f min 13CF RF min

??------------------------------------------=f max 13CF RF min RF max ||()

??--------------------------------------------------------------------------=

17/36

After fixing CF in the hundred pF or in the nF (consistently with the maximum source

capability of the RF min pin and trading this off against the total consumption of the device), the value of RF min and RF max will be selected so that the oscillator frequency is able to cover the entire range needed for regulation, from the minimum value f min (at minimum input voltage and maximum load) to the maximum value f max (at maximum input voltage and minimum load):

A different selection criterion will be given for RF max in case burst-mode operation at no-load will be used (see "Operation at no load or very light load" section).

In Figure 22 the timing relationship between the oscillator waveform and the gate-drive signals, as well as the swinging node of the half-bridge leg (HB) is shown. Note that the low-side gate-drive is turned on while the oscillator's triangle is ramping up and the high-side gate-drive is turned on while the triangle is ramping down. In this way, at start-up, or as the IC resumes switching during burst-mode operation, the low-side MOSFET will be switched on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor will always be charged and ready to supply the high-side floating driver.

RF min 1

3CF f min

??-----------------------------------=RF max RF min

f max

f min

----------1–--------------------=

7.2 Operation at no load or very light load

When the resonant half-bridge is lightly loaded or unloaded at all, its switching frequency will

be at its maximum value. T o keep the output voltage under control in these conditions and to

avoid losing soft-switching, there must be some significant residual current flowing through

the transformer's magnetizing inductance. This current, however, produces some

associated losses that prevent converter's no-load consumption from achieving very low

values.

To overcome this issue, the L6599 enables the designer to make the converter operate

intermittently (burst-mode operation), with a series of a few switching cycles spaced out by

long idle periods where both MOSFETs are in OFF-state, so that the average switching

frequency can be substantially reduced. As a result, the average value of the residual

magnetizing current and the associated losses will be considerably cut down, thus

facilitating the converter to comply with energy saving recommendations.

The device can be operated in burst-mode by using pin 5 (STBY): if the voltage applied to

this pin falls below 1.25V the IC will enter an idle state where both gate-drive outputs are

low, the oscillator is stopped, the soft-start capacitor C SS keeps its charge and only the 2V

reference at RF min pin stays alive to minimize IC's consumption and V CC capacitor's

discharge. The IC will resume normal operation as the voltage on the pin exceeds 1.25V by

50mV.

To implement burst-mode operation the voltage applied to the STBY pin needs to be related

to the feedback loop. Figure23 shows the simplest implementation, suitable with a narrow

input voltage range (e.g. when there is a PFC front-end).

18/36

19/36

Essentially, RF max will define the switching frequency f max above which the L6599 will enter burst-mode operation. Once fixed f max , RF max will be found from the relationship:

Note that, unlike the f max considered in the previous section ("Chapter 7.1: Oscillator "), here f max is associated to some load Pout B greater than the minimum one. Pout B will be such that the transformer's peak currents are low enough not to cause audible noise.

Resonant converter's switching frequency, however, depends also on the input voltage; hence, in case there is quite a large input voltage range with the circuit of Figure 23 the value of Pout B would change considerably. In this case it is recommended to use the

arrangement shown in Figure 24 where the information on the converter's input voltage is added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction R A / (R A + R B ) needed to minimize the change of Pout B . Just be careful in choosing the total value R A + R B much greater than R C to minimize the effect on the LINE pin voltage (see Chapter 7.6: Line sensing function ).

Whichever circuit is in use, its operation can be described as follows. As the load falls below the value Pout B the frequency will try to exceed the maximum programmed value f max and the voltage on the STBY pin (V STBY ) will go below 1.25V . The IC will then stop with both gate-drive outputs low, so that both MOSFETs of the half-bridge leg are in OFF-state. The voltage V STBY will now increase as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.3V, the IC will restart switching. After a while, V STBY will go down again in response to the energy burst and stop the IC. In this way the converter will work in a burst-mode fashion with a nearly constant switching frequency. A further load decrease will then cause a frequency reduction, which can go down even to few hundred hertz. The timing diagram of Figure 25 illustrates this kind of operation, showing the most significant signals. A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close to the IC as possible to reduce switching noise pick-up, will help get clean operation. To help the designer meet energy saving requirements even in power-factor-corrected

systems, where a PFC pre-regulator precedes the DC-DC converter, the device allows that the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the no-load consumption of this stage (0.5 ÷ 1W). There is no compliance issue in that because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load.

To do so, the device provides pin 9 (PFC_STOP): it is an open collector output, normally open, that is asserted low when the IC is idle during burst-mode operation. This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in Figure 26 When the L6599 is in UVLO the pin is kept open, to let the PFC controller start first.

RF max 3

8--RF min f max

f min

----------1–--------------------?=

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