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MAX1937EEI中文资料

General Description

The MAX1937/MAX1938/MAX1939 comprise a family of synchronous, two-phase, step-down controllers capable of delivering load currents up to 60A. The controllers uti-lize Quick-PWM? control architecture in conjunction with active load-current voltage positioning. Quick-PWM con-trol provides instantaneous load-step response, while programmable voltage positioning allows the converter to utilize full transient regulation limits, reducing the out-put capacitance requirement. The two phases operate 180°out-of-phase with an effective 500kHz switching fre-quency, thus reducing input and output current ripple, as well as reducing input filter capacitor requirements.

The MAX1937/MAX1938/MAX1939 are compliant with AMD Hammer, Intel ??Voltage-Regulator Module (VRM)9.0/9.1, and AMD Athlon?Mobile VID code specifica-tions (see Table 1 for VID codes). The internal DAC pro-vides ultra-high accuracy of ±0.75%. A controlled VID voltage transition is implemented to minimize both undervoltage and overvoltage overshoot during VID input change.

Remote sensing is available for high output-voltage accuracy. The MOSFET switches are driven by a 6V gate-drive circuit to minimize switching and crossover conduction losses to achieve efficiency as high as 90%. The MAX1937/MAX1938/MAX1939 feature cycle-by-cycle current limit to ensure that the current limit is not exceeded. Crowbar protection is available to pro-tect against output overvoltage.

Applications

Notebook and Desktop Computers Servers and Workstations Blade Servers High-End Switches High-End Routers Macro Base Stations

Features

?±0.75% Output Voltage Accuracy ?Instant Load-Transient Response

?Up to 90% Efficiency Eliminates Heatsinks ?Up to 60A Output Current ?8V to 24V Input Range

?User-Programmable Voltage Positioning ?Controlled VID Voltage Transition

?500kHz Effective Switching Frequency ?MAX1937: AMD Hammer Compatible ?MAX1938: Intel VRM 9.0/9.1 Compatible ?MAX1939: AMD Athlon Mobile Compatible ?Soft-Start

?Power-Good (PWRGD) Output ?Cycle-by-Cycle Current Limit

?Output Overvoltage Protection (OVP)?R DS(ON)or R SENSE Current Sensing ?Remote Voltage Sensing ?

28-Pin QSOP Package

MAX1937/MAX1938/MAX1939

________________________________________________________________Maxim Integrated Products 1

Pin Configuration

Ordering Information

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.wendangku.net/doc/1e3261886.html,.

Quick-PWM is a trademark of Maxim Integrated Products, Inc.Athlon is a trademark of Advanced Micro Devices, Inc.Intel is a registered trademark of Intel Corp.

Typical Application Circuits and Functional Diagram appear at end of data sheet.

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 2_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V CC to GND............................................................-0.3V to +28V V DD , PWRGD, ILIM, FB to GND...............................-0.3V to +6V EN, GNDS, VPOS, REF, VID_,

TIME to GND............................................0.3V to V VDD + 0.3V PGND to GND .......................................................-0.3V to +0.3V CS1, CS2 to GND......................................................-2V to +28V VLG to GND..............................................................-0.3V to +7V BST1, BST2 to GND ...............................................-0.3V to +35V LX1 to BST1..............................................................-7V to +0.3V LX2 to BST2..............................................................-7V to +0.3V

DH1 to LX1.................................................-0.3V to V BST1 + 0.3V DH2 to LX2.................................................-0.3V to V BST2 + 0.3V DL1, DL2 to PGND......................................-0.3V to V VLG + 0.3V Continuous Power Dissipation (T A = +70°C)

28-Pin QSOP (derate 20.8mW/°C above +70°C)......860.2mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°C

ELECTRICAL CHARACTERISTICS

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

_______________________________________________________________________________________3

ELECTRICAL CHARACTERISTICS (continued)

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 4_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

= 12V, V = V = 5V, PGND = GNDS = GND = 0, VID_ = GND, C = 47pF, C = 0.1μF, V = 1V, T = 0°C to

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

_______________________________________________________________________________________5

ELECTRICAL CHARACTERISTICS

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 6_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

_______________________________________________________________________________________7

EFFICIENCY vs. LOAD CURRENT

AT 1.45V OUTPUT

LOAD CURRENT (A)

E F F I C I E N C Y (%)

809050

100

EFFICIENCY vs. LOAD CURRENT

AT 1.85V OUTPUT

LOAD CURRENT (A)

E F F I C I E N C Y (%

)

FREQUENCY vs. LOAD CURRENT

LOAD CURRENT (A)

F R E Q U E N C Y (k H z )

50100

15020025030035000

FREQUENCY vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

F R E Q U E N C Y (k H z )

175200225250275300325150

FREQUENCY vs. TEMPERATURE

TEMPERATURE (°C)

F R E Q U E N C Y (k H z )

-20

225230

235240245250255260

220

-40

100

V CC INPUT CURRENT vs. INPUT VOLTAGE

INPUT VOLTAGE (V)

V C C I N P U T C U R R E N T (μA )

2508

V DD CURRENT vs. V DD VOLTAGE

M A X 1937 t o c 07

V DD VOLTAGE (V)

V D D C U R R E N T (m A )

5.3

5.1

4.9

4.7

1.55

1.601.651.701.751.801.50

4.5

5.5

Typical Operating Characteristics

(V IN = 12V, V OUT = 1.45V, T A = +25°C, unless otherwise noted.)

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 8

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Typical Operating Characteristics (continued)

(V IN = 12V, V OUT = 1.45V, T A = +25°C, unless otherwise noted.)

CURRENT SHARING

LOAD CURRENT (A)I N D U C T O R C U R R E N T S (A )

4030

0510********-5

CURRENT SHARING

LOAD CURRENT (A)

I N D U C T O R C U R R E N T S (A )

0510********-5

V IN = 12V V OUT = 1.45V I OUT = 0A

OUTPUT INDUCTOR CURRENTS:10A/div OUTPUT RIPPLE VOLTAGE:20mV/div 2μs/div

MAX1937 toc12

INDUCTOR CURRENT WAVEFORMS

WITH 0A LOAD

V IN = 12V V OUT = 1.45V I OUT = 40A

OUTPUT INDUCTOR CURRENTS:10A/div

OUTPUT RIPPLE VOLTAGE:20mV/div

2μs/div

MAX1937 toc13

INDUCTOR CURRENT WAVEFORMS

WITH 40A LOAD

OUTPUT VOLTAGE vs. LOAD CURRENT

AT 1.45V OUTPUT

LOAD CURRENT (A)

V O U T

1.375

1.400

1.425

1.450

1.350

V DD CURRENT vs. V DD VOLTAGE

IN SHUTDOWN

V DD VOLTAGE (V)

V D D C U R R E N T (m A )

5.3

5.1

4.9

4.7

3540455055

656070304.5

5.5

ENABLE SIGNAL

OUTPUT VOLTAGE:0.5V/div

POK SIGNAL

20ms/div

MAX1937 toc18

SHUTDOWN WAVEFORM

WITH 40A LOAD

INDUCTOR CURRENT:10A/div

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

_______________________________________________________________________________________9

CURRENT-SENSE THRESHOLD vs. V ILIM

V ILIM (V)

C U R R E N T -S E N S E T H R E S H O L

D (m V )

1.3

1.1

0.9

0.7

6080100120140160400.5

1.5

Typical Operating Characteristics (continued)

(V IN = 12V, V OUT = 1.45V, T A = +25°C, unless otherwise noted.)

ENABLE SIGNAL

OUTPUT VOLTAGE:0.5V/div

POK SIGNAL 1ms/div

MAX1937 toc16

SOFT-START WAVEFORMS

WITH 40A LOAD

INDUCTOR CURRENT:10A/div

ENABLE SIGNAL

OUTPUT VOLTAGE:0.5V/div

POK SIGNAL 20ms/div

MAX1937 toc17

SHUTDOWN WAVEFORM

WITH NO LOAD

INDUCTOR CURRENT:10A/div

40μs/div

MAX1937 toc14

LOAD TRANSIENT 1A TO 40A TO 1A

TRANSIENT CONTROL SIGNAL:C6 = 47pF R2 = 91.1k Ω

INDUCTOR CURRENTS:10A/div

OUTPUT VOLTAGE:50mV/div

ENABLE SIGNAL

OUTPUT VOLTAGE:0.5V/div

POK SIGNAL 1ms/div

MAX1937 toc15

SOFT-START WAVEFORMS

WITH NO LOAD

INDUCTOR CURRENT:10A/div

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 10______________________________________________________________________________________

REFERENCE VOLTAGE vs. TEMPERATURE

TEMPERATURE (°C)

R E F E R E N C E V O L T A G E (V )

-20

1.992

1.994

1.996

1.998

2.0001.990

-40

100

FB VOLTAGE vs. TEMPERATURE

TEMPERATURE (°C)

F B V O L T A

G E (V )

-15

0.795

0.800

0.8050.810

0.790

-40

FB VOLTAGE vs. TEMPERATURE

TEMPERATURE (°C)

F B V O L T A

G E (V )

-20

1.450

1.455

1.4601.465

1.445

-40

100

OUTPUT VOLTAGE:200mV/div POK SIGNAL

40μs/div MAX1937 toc20

VID CODE CHANGE ON-THE-FLY WITH 40A

LOAD 1.2V TO 1.45V TO 1.2V

VID CODE CHANGE CONTROL SIGNAL

OUTPUT VOLTAGE:200mV/div

POK SIGNAL

40μs/div

MAX1937 toc21

VID CODE CHANGE ON-THE-FLY WITH 1A

LOAD 1.2V TO 1.45V TO 1.2V

VID CONTROL SIGNAL

Typical Operating Characteristics (continued)

(V IN = 12V, V OUT = 1.45V, T A = +25°C, unless otherwise noted.)

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

______________________________________________________________________________________11

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 12

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The MAX1937/MAX1938/MAX1939 is a family of syn-chronous, two-phase step-down controllers capable of

delivering load currents up to 60A. The controllers use Quick-PWM control architecture in conjunction with active load current voltage positioning. Quick-PWM control provides instantaneous load-step response,while programmable voltage positioning allows the con-verter to utilize full transient regulation limits, reducing the output capacitance requirement. Furthermore, the two phases operate 180°out-of-phase with an effective 500kHz switching frequency, thus reducing input and output current ripple, as well as reducing input filter capacitor requirements.

The MAX1937/MAX1938/MAX1939 are compliant with the AMD Hammer, Intel VRM 9.0/VRM 9.1, and AMD Athlon Mobile VID code specifications (see Table 1 for VID codes). The internal DAC provides ultra-high accu-racy of ±0.75%. A controlled VID voltage transition is implemented to minimize both undervoltage and over-voltage overshoot during VID input change.

Remote sensing is available for high output-voltage accuracy. The MOSFET switches are driven by with a 6V gate-drive circuit to minimize switching and crossover conduction losses to achieve efficiency as high as 90%. The MAX1937/MAX1938/ MAX1939 fea-ture cycle-by-cycle current limit to ensure current limit is not exceeded. Crowbar protection is available to pro-tect against output overvoltage.

sets the high-side switch on-time. This fast, low-jitter,one-shot circuitry varies the on-time in response to the input and output voltages. The high-side switch on-time is inversely proportional to the voltage applied to V CC and directly proportional to the output voltage. This algorithm results in a nearly constant switching fre-quency, despite the lack of a fixed-frequency clock generator. The benefits of a constant switching fre-quency are twofold: the frequency selected avoids noise-sensitive regions, and the inductor ripple current operating point remains relatively constant, resulting in easy design methodology and predictable output volt-age ripple:

where the constant K is 4μs and V DROP is the voltage drop across the low-side MOSFET’s on-resistance plus the drop across the current-sense resistor (V DROP ≈75mV), if used.

The on-time one-shot has good accuracy at the operat-ing point specified in the Electrical Characteristics . On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wide range. For example, the regulators run slower with input voltages greater than 12V because of the very short on-times required.

t K V V V ON OUT DROP

VCC

=+()

Pin Description (continued)

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

______________________________________________________________________________________

While the on-time is set by the input and output voltage,other factors contribute to the switching frequency. The on-time guaranteed in the Electrical Characteristics is influenced by switching delays in the external high-side MOSFET. Resistive losses in the inductor, both MOSFETs,output capacitor ESR, and PC board copper losses in the output and ground, tend to raise the switching fre-quency at higher output currents. Switch dead-time can also increase the effective on-time, reducing the switching frequency. This effect occurs when the inductor current reverses at light or negative load cur-rents. With reversed inductor current, the inductor’s

Table 1. VID Programmed Output Voltage

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 14______________________________________________________________________________________

EMF causes LX to go high earlier than normal, extend-ing the on-time by a period equal to the DH rising dead-time.

When the controller operates in continuous mode, the dead-time is no longer a factor, and the actual switch-ing frequency is:

where V DROP1is the sum of the parasitic voltage drops

in the inductor discharge path, including the synchro-nous rectifier, inductor, and PC board resistances;V DROP2is the sum of the resistances in the charging path, including the high-side MOSFET, inductor, and PC board resistances.

Synchronized 2-Phase Operation

The two phases of the MAX1937/MAX1938/MAX1939operate 180°out-of-phase to reduce input filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers cost and saves board space, making the MAX1937/MAX1938/MAX1939 ideal for cost-sensitive applica-tions.

With dual synchronized out-of-phase operation, the MAX1937/MAX1938/MAX1939s’ high-side MOSFETs turn on 180°out-of-phase. The instantaneous input current peaks of both regulators do not overlap, resulting in reduced input voltage ripple and RMS ripple current.This reduces the input capacitance requirement, allowing fewer or less expensive capacitors, and reduces shield-ing requirements for EMI. The 180°out-of-phase wave-forms are shown in the Typical Operating Characteristics.Each phase operates with a 250kHz switching frequen-cy. Since the two regulators operate 180°out-of-phase,an effective switching of 500kHz is seen at the input and output. In addition to being at a higher frequency (compared to a single-phase regulator), both the input and output ripple have lower amplitude.

Phase Overlap

To minimize the crosstalk noise in the two phases, the maximum duty cycle of the MAX1937/MAX1938/MAX1939 is less than 50%. To provide a fast transient response, these devices have a phase-overlap mode that allows the two phases to operate in phase when a heavy-load transient is detected. In-phase operation continues until the output voltage returns to the nominal output voltage regulation value.

Once regulation is achieved, the controller returns to 180°out-of-phase operation. A minimum current-adap-tive phase-selection algorithm is used to determine which phase is used to start the first out-of-phase cycle. Once the output voltage returns to the nominal output voltage regulation value, the subsequent cycle starts with the phase that has the lowest inductor current. For example,if the current-sense inputs indicate that phase 2 has lower inductor current than phase 1, the controller turns on phase 2’s high-side MOSFET first when returning to normal operation.

Differential Voltage Sensing and Error

Comparator

The MAX1937/MAX1938/MAX1939 use differential sensing of the output voltage to achieve the highest possible accuracy of the output voltage. This allows the error comparator to sense the actual voltage at the load, so that the controller can compensate for losses in the power output and ground lines.

FB and GNDS are used for the differential output voltage sensing. The controller triggers the next cycle (turn on the high-side MOSFET) when the error comparator is low (V FB - V GNDS is less than the VID regulation voltage),V CS is below the current-limit threshold, and the mini-mum off-time one-shot has timed out.

Traces from FB and G NDS should be routed close to each other and as far away as possible from sources of noise (such as the inductors and high di/dt traces). If noise on these connections cannot be prevented, then use RC filters. To filter FB, connect a 100Ωseries resistor from the positive sense trace to FB, and connect a 1000pF capacitor from FB to GND right at the FB pin. For GNDS, connect a 100Ωseries resistor from the negative sense trace to GNDS, and connect a 1000pF capacitor from GNDS to GND at the GNDS pin.

For VRM applications, connect a 10k Ωresistor from FB to the output locally (on the VRM board), and connect a 10k Ωresistor from GNDS to PGND locally (on the VRM board). FB and GNDS also connect to the output at the load (off the VRM board, at the microprocessor). This provides the benefits of differential output voltage sens-ing mentioned above and the safety of regulating the output voltage on the board in case the external sense connections get disconnected.

External Linear Regulator

A 6V linear regulator (U2) is used to step down the main supply. The output of this linear regulator is con-nected to VLG to provide power for the low-side gate drive and bootstrap circuit. Using 6V for this supply improves efficiency by providing a stronger gate drive than a 5V supply. To reduce switching noise on VLG ,

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

______________________________________________________________________________________

connect a capacitor (C VLG ) from VLG to PGND. Place this capacitor as close as possible to the VLG pin.

The MAX1937/MAX1938/MAX1939 also require an exter-nal 5V supply connected to V DD . A diode with a forward voltage drop of about 1V (D1) is used to stepdown the 6V supply to power the IC, as shown in Figure 1. The diode connects between the linear regulator output and the RC filter used to filter the voltage at V DD (R1, C VDD ,and C3). In the PC board layout, place C VDD as close as possible to the V DD pin.

High-Side Gate-Drive Supply (BST_)

The drive voltage for the high-side MOSFETs is gener-ated using a bootstrap circuit. The capacitor, C BST_,should be sized properly to minimize the ripple voltage for switching. The ripple voltage should be less than 200mV. For more information on selecting capacitors for the BST circuit, see the S electing a BS T Capacitor section. To minimize the forward voltage drop across the bootstrap diodes (D2), use Schottky diodes. The recommended value for the boost capacitors (C BST_) is 0.22μF.

Figure 1. MAX1937 Application Circuit

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 16______________________________________________________________________________________

MOSFET Drivers

The DH_ and DL_ drivers are optimized for driving large high-side (N1 and N2) and larger low-side MOSFETs (N3 and N4). This is consistent with the low duty-cycle operation of the controller. The DL_ low-side drive wave-form is always the complement of the DH_ high-side drive waveform, with a fixed dead-time between one MOSFET turning off and the other turning on to prevent cross-conduction or shoot-through current.

The internal transistor that drives DL_ low is robust with a 0.5Ω(typ) on-resistance. This helps prevent DL_ from being pulled up during the fast rise time of the LX_node due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET.However, some combinations of high-side and low-side MOSFETs may cause excessive gate-drain coupling,leading to poor efficiency, EMI, and shoot-through cur-rents. This is often remedied by adding a resistor (typi-cally less than 5Ω) in series with BST_, which increases the turn-on time of the high-side MOSFET without degrading the turn-off time.

Current-Limit Circuit

The MAX1937/MAX1938/MAX1939 use either the on-resistance of the low-side MOSFETs or a current-sense resistor to monitor the inductor current. Using the low-side MOSFETs’ on-resistance as the current-sense ele-ment provides a lossless and inexpensive solution ideal for high-efficiency or cost-sensitive applications. The dis-advantage to this method is that the on-resistance of MOSFETs vary from part to part, and overtemperature,which means it cannot be counted on for high accuracy.If high accuracy is needed, use current-sense resistors,which provide an accurate current limit under all condi-tions but reduce efficiency slightly because of the power lost in the resistors.

The current-limit circuit employs a “valley” current-sensing algorithm to monitor the inductor current. If the current-sense signal does not drop below the current-limit threshold, the controller does not initiate a new cycle. This limits the maximum value of I VALLEY to the current set by the current-limit threshold (Figure 2).

The current-limit threshold is adjustable over a wide range, allowing for a range of current-sense resistor values. The voltage on ILIM sets the current-limit threshold between PGND and CS_ to 0.1 ?V ILIM . The 10mV to 200mV adjustment range corresponds to ILIM voltages from 100mV to 2V. The ILIM voltage is set by a resistor-divider between REF and GND. See the Setting the Current Limit section for details.

Current Balancing

The DC current balancing between phases depends on the accuracy of the current-sense elements and the off-set of the current-balance amplifier.

The maximum offset of the current-balance amplifier (V CBOFFSET ) is ±3mV. The current-balance accuracy can be calculated from:

Current-balance accuracy = V CBOFFSET / (I L ?R CS )where I L is the peak inductor current and R CS is the value of the current-sense resistor.

The current-balance accuracy is most important at full load. With a load current of 50A (I L = 25A) and 2m Ωcurrent-sense resistors, the worst-case current-balance accuracy is:

Current-balance accuracy = 0.003 / (25 ?0.002) = 6%If the on-resistance of the low-side MOSFETs is used for current sensing, the part-to-part variation of the MOSFET on-resistance is a significant factor in the cur-rent balance. The matching between MOSFETs should be on the order of 15%, worst case. Thus, even if the current-balance amplifier has no offset, the DC-current balance could be as bad as 15%. In practice, a little help is received from the thermal ballasting of the MOSFETs. That is to say, the positive temperature coef-ficient of the on-resistance of MOSFETs reduces the mismatch current between the two phases.

Voltage Positioning (VPOS)

During a load transient, the output voltage instantly changes by the ESR of the output capacitors times the change in load current (ΔV OUT = -ESR COUT ?ΔI LOAD ).Conventional DC-DC converters respond by regulating the output voltage back to its nominal state after the load transient occurs (Figure 3). However, the CPU requires that the output voltage remain within a specific voltage band. Dynamically positioning the output volt-age allows the use of fewer output capacitors and reduces power consumption under heavy load.

For a conventional (nonvoltage-positioned) circuit, the total output voltage deviation from light load to full load and back to light load is:

V P-P1= 2 ?(ESR COUT ?ΔI LOAD ) + V SAG + V SOAR where V SAG and V SOAR are defined in the Output Capacitor Selection section. Setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output current suddenly decreases. The total voltage change for a voltage-posi-tioned circuit is:

V P-P2= (ESR COUT ?ΔI LOAD ) + V SAG +V SOAR

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

______________________________________________________________________________________

The maximum allowable voltage change during a tran-sient is fixed by the supply range of the CPU (V P-P1=V P-P2). This means that the voltage-positioned circuit tolerates twice the ESR in the output capacitors.Because the ESR specification is achieved by parallel-ing several capacitors, fewer capacitors are needed for the voltage-positioned circuit. Figure 4 shows transient response regions.

An additional benefit of voltage positioning is reduced power consumption at high-load currents. Because the output voltage is lower under heavy load, the CPU draws less current. The result is lower power dissipa-tion in the CPU.

Voltage Reference (REF)

A 2V reference is provided on the MAX1937/MAX1938/MAX1939 through the REF pin. REF is capable of sourcing or sinking up to 50μA. In addition to providing a reference for the IC, REF is used for setting the cur-rent limit and voltage positioning. Connect a 0.47μF capacitor from REF to G ND. This capacitor should be placed as close as possible to the REF pin.

A UVLO is provided for the reference voltage. The ref-erence voltage must rise above 1.600V to activate the controller. The controller is disabled if the reference voltage falls below 1.584V.

Enable Input (EN) and Soft-Start

When EN is low, DL_ and DH_ are held low (turning off the MOSFETs), leaving LX_ high impedance. In addi-tion, the reference is turned off and PWRG D is pulled low. In shutdown, total current consumption is about 50μA (typ).

In the case of shutdown by VID code, only DL_ and DH_ are held low. The rest of the controller is enabled.When EN is driven high, the startup sequence begins.Once the reference voltage rises above its 1.6V UVLO threshold, the controller begins switching and starts to ramp up the output voltage. The output voltage is ramped up in 25mV steps every 50μs until the output reaches the nominal output voltage.

Fault Conditions

The MAX1937/MAX1938/MAX1939 contain internal cir-cuitry to protect themselves and surrounding circuitry from damage from output overvoltage and output undervoltage conditions. When either of these condi-tions occurs, DH_ is pulled low, DL_ is driven high, and PWRG D is pulled low. These pins remain in this state until either power is cycled on V DD or EN is toggled high-low-high.

Setting the Output Voltage (VID_)

An internal DAC is used to set the output regulation voltage. A 5-bit code on inputs VID0–VID4 is used to specify the output voltage. Some codes disable the output. There is an internal 100k Ωpullup resistor to VDD on each of the VID_ inputs. Connecting VID_ to G ND sets the bit to logic low (0); connecting VID_ to VDD or leaving it unconnected sets the bit to logic high (1). Use external pullup resistors to speed the low-to-high logic transition, or for lower logic voltages. See Table 1 for a list of codes and corresponding output regulation voltages for each of the parts.

The VID_ codes for the MAX1937 comply with AMD Hammer code. The VID_ codes on the MAX1938 are

Figure 2. Inductor Current Waveform

1.4V

A. CONVENTIONAL CONVERTER (50mV/div)

B. VOLTAGE-POSITIONED OUTPUT (50mV/div)

VOLTAGE POSITIONING THE OUTPUT

Figure 3. Voltage-Positioning and Nonvoltage-Positioning Waveforms

M A X 1937/M A X 1938/M A X 1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 18______________________________________________________________________________________

set for Intel VRM 9.0/9.1 and AMD Athlon. The MAX1939 is set for AMD Athlon Mobile.

VID_ Change Slew Rate (TIME)

The MAX1937/MAX1938/MAX1939 allow the VID_ code

to be changed while the converter is operating (on-the-fly). The slew rate at which the output voltage is chang-ing is controlled through TIME. The slew rate is adjusted externally by connecting a 47k Ωto 470k Ωresistor (R TIME ) from TIME to GND. To set the slew rate,select the R TIME resistor using the following equation:

where SR is the slew rate of the output voltage in V/μs.

The output voltage is stepped up or down in 25mV steps until it reaches the voltage set by the new VID code.

Power-Good Output (PWRGD)

PWRGD is an open-drain output that is pulled low when the output voltage deviates more than 12.5% from its regulation voltage (set by VID_ inputs). PWRG D is pulled low in shutdown, input UVLO, and during start-up. Any fault condition forces PWRGD low until the fault is cleared, and the IC is reset by cycling power at V DD or momentarily toggling EN. For logic-level output volt-ages, connect an external pullup resistor between PWRGD and the logic power supply. A 100k Ωresistor works well in most applications.

Design Procedure

Output Inductor Selection

For most applications, an inductor value of 0.5μH to 1μH is recommended. The inductance is set by the desired amount of inductor current ripple (LIR). A larger inductance value minimizes output ripple current and increases efficiency, but slows transient response. For the best compromise of size, cost, and efficiency, a LIR of 30% to 40% is recommended (LIR = 0.3 to 0.4). The inductor value is found from:

where f sw is the actual switching frequency of a phase.The selected inductor should have the lowest possible equivalent DC resistance and a saturation current greater than the peak inductor current (I PEAK ). I PEAK is found from:

Output Capacitor Selection

The output capacitor must have low enough ESR to meet output ripple and load-transient requirements.Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to a no-load condition without tripping the OVP circuit.In CPU core power supplies and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:

R ESR = V STEP(MAX)/ ΔI LOAD(MAX)

The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of OS-CONs, SP capacitors, POSCAPs, and other electrolytic capacitors). Generally, ceramic capacitors are not rec-ommended for bulk output capacitance but make excellent high-frequency decoupling capacitors.

Once enough capacitance is added to meet the over-shoot requirement, undershoot at the rising load edge

L V V V V f I LIR OUT IN OUT

IN SW LOAD MAX =

×?()

×××()

Figure 4. Transient Response Regions

MAX1937/MAX1938/MAX1939

Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change

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(V SAG ) is no longer a problem. The amount of overshoot from stored inductor energy can be calculated as:

where I PEAK is the peak inductor current.

The undershoot at the rising load edge of a load tran-sient is calculated from:

where ΔI LOAD is the change in load current, and K is 4μs.

To ensure stability, make sure that the zero frequency created by the output capacitance, and the ESR of the output capacitor do not exceed 50kHz. The zero fre-quency is found from:

Currently, aluminum electrolytic, Sanyo POSCAP, and Panasonic SP capacitors have ESR zero frequencies well below 50kHz. When using ceramic capacitors, it might be necessary to use a series resistance to ensure that the ESR zero is below 50kHz.

Input Capacitor Selection

The input capacitor reduces peak currents drawn from

the power source and reduces noise and voltage ripple on the input caused by the circuit’s switching. The input capacitor must meet the ripple current requirement (I RMS ) imposed by the switching currents as defined by the following equation:

I RMS has a maximum value when the input voltage equals twice the output voltage (V IN = 2V OUT ), so I RMS(MAX)= I LOAD / 2. For most applications, nontanta-lum capacitors (ceramic, aluminum electrolytic, poly-mer, or OS-CON) are preferred at the input because of their robustness with high inrush currents typical of sys-

tems that may be powered from very low impedance

sources.

Multiple smaller value capacitors can be used in paral-lel to satisfy the ESR and capacitance requirements.

Selecting a BST Capacitor

The BST capacitors must be large enough to handle the gate-charging requirements of the high-side MOSFETs. For most applications, 0.22μF ceramic capacitors are recommended.

BST capacitors are needed to keep the voltage on the BST_ pins from dropping too much when the high-side MOSFET gates are charged. A capacitor value that prevents V BST _ from dropping more than 100mV to 200mV is adequate. The capacitance needed for the BST_ capacitor is calculated from:

where Q GH is the total gate charge of the high-side MOSFET and ΔV BST_is the amount that the voltage on the BST_ pin drops when the gate is charged. If using multiple MOSFETs in parallel, use the sum of all the gate charges for Q GH .

Setting the Current Limit

Current limit sets the maximum value of the inductor “valley” current. I VALLEY is calculated from the following equation:

The current-limit threshold (I LIMIT ) must be set higher

than the valley current:

The current-limit threshold is set by the voltage at ILIM and the value of the current-sense resistors:

where V ILIM is the voltage on the ILIM pin (0.1V to 2V)and R CS is the value of the current-sense resistor. If the on-resistance of the low-side MOSFET is used for cur-rent sensing, then the maximum value of the on-resis-tance (overtemperature and part-to-part variation) must be used for R CS .

I I LIMIT VALLEY

C Q V BST GH BST __

=Δ

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Two-Phase Desktop CPU Core Supply Controllers with Controlled VID Change 20______________________________________________________________________________________

V ILIM is set from 0.5V to 2V by connecting ILIM to a resistor-divider from REF to G ND. Select resistors R3and R4 such that the current through the divider is at least 5μA:

A typical value for R3 is 200k Ω; then solve for R4 using:

Setting the Voltage Positioning

Voltage positioning dynamically changes the output-voltage set point in response to the load current. When the output is loaded, the signals fed back from the cur-rent-sense inputs adjust the output voltage set point,thereby decreasing power dissipation. The load-tran-sient response of this control loop is extremely fast yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. To under-stand the benefits of dynamically adjusting the output voltage, see the Voltage Positioning (VPOS)section.The amount of output voltage change is adjusted by an external gain resistor (R VPOS ). Connect R VPOS between REF and VPOS. The output voltage changes in response to the load current as follows:

where V VID is the programmed output voltage set by

the VID code (Table 1), and the voltage-positioning transconductance (g m(VPOS)) is typically 20μS. R CS is the value of the current-sense resistor connected from CS_ to PG ND. If the on-resistance of the low-side MOSFETs is used instead of current-sense resistors for current sensing, then use the maximum on-resistance of the low-side MOSFETs for R CS in the equation above.

MOSFET Power Dissipation

Power dissipation in the high-side MOSFET is worst at high duty cycles (maximum output voltage, minimum input voltage). Two major factors contribute to the high-side power dissipation, conduction losses, and switch-ing losses. Conduction losses are because of current flowing through a resistance, and can be calculated from:

where R DS(ON)is the on-resistance of the high-side MOSFET and V IN is the input voltage. To minimize con-duction losses, select a MOSFET with a low R DS(ON).Switching losses are also a major contributor to power dissipation in the high-side MOSFET. Switching losses are difficult to precisely calculate and should be mea-sured in the circuit. To estimate the switching losses,use the following equation:

where I PEAK and I VALLEY are the maximum peak and

valley inductor currents, t FALL and t RISE are the fall and rise times of the high-side MOSFET, and f SW is the switching frequency (about 250kHz).

The total power dissipated in the high-side MOSFET is then found from:

P D(HS)= P D(HS)COND + P D(HS)SW The power dissipation in the low-side MOSFET is high-est at low duty cycles (high input voltage, low output voltage), and is mainly because of conduction losses:Switching losses in the low-side MOSFET are small because of its voltage being clamped by the body diode. Switching losses can be estimated from:

where I LOADMAX/2is the maximum average inductor

current, t DT is the time/cycle that the low-side MOSFET conducts through its body diode, and V DF is the for-ward voltage drop across the body diode.

The total power dissipation in the low-side MOSFET is:

P D(LS)= P D(LS)COND + P D(LS)SW

IC Power Dissipation

During normal operation, power dissipation in the con-troller is mostly from the gate drivers. This can be cal-culated from the following equation:

P GATE = 2 ?V VLG ?f SW ?( Q GH + Q GL )

P I t I t V f

D HS SW PEAK fall VALLEY rise IN SW

()()?×+××2

R R k 34400 +≤Ω