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RTL8211E_G-VB_VL-CG_DataSheet_1.8

RTL8211E_G-VB_VL-CG_DataSheet_1.8
RTL8211E_G-VB_VL-CG_DataSheet_1.8

RTL8211E-VB-CG RTL8211E-VL-CG RTL8211EG-VB-CG

INTEGRATED 10/100/1000M ETHERNET

TRANSCEIVER

DATASHEET

(CONFIDENTIAL: Development Partners Only)

Rev. 1.8 10 Ju ly 2013

Track ID: JATR-8275-15

Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211 Fax: +886-3-577-6047 https://www.wendangku.net/doc/1f7182600.html,

COPYRIGHT

?2013 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER

Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.

LICENSE

This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and US6,327,625.

USING THIS DOCUMENT

This document is intended for the software engineer’s reference and provides detailed programming information.

Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

Integrated 10/100/1000M Ethernet Transceiver ii Track ID: JATR-8275-15 Rev. 1.8

Integrated 10/100/1000M Ethernet Transceiver iii Track ID: JATR-8275-15 Rev. 1.8

REVISION HISTORY

Revision Release Date Summary 1.0 2009/08/31 First release. 1.1 2010/08/13 Added RTL8211EG-CG product data. 1.2 2010/08/16 Corrected minor typing errors. 1.3 2010/12/17 Added RTL8211E-VL-CG model number.

Revised Table 24 BMCR (Basic Mode Control Register, Address 0x00), page 31. Revised Table 33 GBCR (1000Base-T Control Register, Address 0x09), page 37. Revised Table 41 INSR (Interrupt Status Register, Address 0x13), page 42. Revised Table 57 Power Sequence Parameter, page 55.

Revised Table 63 MDC/MDIO Management Timing Parameters, page 59. Added section 10.6.2 MII Transmission Cycle Timing, page 60.

Added section 10.6.3 MII Reception Cycle Timing (RTL8211EG-VB Only), page 60. Revised Table 66 GMII Timing Parameters, page 62. Revised section 12 Ordering Information, page 68.

1.4 2011/05/17 Revised section 2 Features, page

2.

Revised section 3 System Applications, page 3. Added section 4 Block Diagram, page 5. Revised Table 6 Reset, page 11.

Revised Table 10 Power and Ground, page 12. Added section 7.5 Interrupt, page 15.

Revised section 7.7 Hardware Configuration, page 16.

Revised Figure 7 LED and PHY Address Configuration, page 17. Revised section 7.9.2 Register Setting, page 18.

Revised section 7.10.4 Management Interface, page 19.

Revised section 7.10.5 Access to Extension Page (ExtPage), page 21. Added section 7.16 PHY Reset (Hardware Reset), page 29.

Revised Table 24 BMCR (Basic Mode Control Register, Address 0x00), page 31. Revised Table 38 PHYCR (PHY Specific Control Register, Address 0x10), page 39. Revised Table 58 Absolute Maximum Ratings, page 56.

Revised Table 59 Recommended Operating Conditions, page 56. Revised Table 62 DC Characteristics, page 58.

Revised section 10.6.1 MDC/MDIO Timing, page 59.

Revised section 10.6.2 MII Transmission Cycle Timing (RTL8211EG-VB Only), page 60.Revised Table 68 Ordering Information, page 68.

1.5 2011/10/28 Revised section 4 Block Diagram, page 5.

Revised Table 36 MAADR (MMD Access Address Data Register, Address 0x0E), page 39.

Revised Table 40 INER (Interrupt Enable Register, Address 0x12), page 41. Revised Table 57 Power Sequence Parameter, page 55. Revised Table 62 DC Characteristics, page 58.

Revised Table 64 MII Transmission Cycle Timing, page 60. Revised Table 65 MII Reception Cycle Timing, page 61. Revised section 10.6.5 RGMII Timing Modes, page 63.

Integrated 10/100/1000M Ethernet Transceiver iv Track ID: JATR-8275-15 Rev. 1.8

Revision Release Date Summary 1.6 2012/04/03 Revised Table 21 Register Mapping and Definitions, page 30.

Added Table 23 ExtPage Register Mapping and Definition, page 31.

Added Table 43 LDPSR (Link Down Power Saving Register, Address 0x1B), page 42. Added Table 44 EPAGSR (Extension Page Select Register, Address 0x1E), page 42. Added Table 52 LACR (LED Action Control Register, ExtPage 0x2c, Address 0x1a), page 45.

Added Table 53 LCR (LED Control Register, ExtPage 0x2c, Address 0x1c), page 45. Added Table 54 ACCR (Auto-Crossover Control Register, ExtPage 0x2d, Address 0x18)45, page 45.

Revised section 11.4 Mechanical Dimensions Notes (RTL8211EG-VB), page 67.

1.7 2013/01/07 Revised section 1 General Description, page 1.

Revised section 2 Features, page 2.

Revised section 7.10.4 Management Interface, page 19. Revised section 8 Register Descriptions, page 30. Added Table 20. Register Access Types, page 30. Revised section 9.5 Power Sequence, page 55. Revised Table 68. Ordering Information, page 68.

1.8 2013/07/10 R evised section 7.13 LED Configuration, page 27.

Added Table 55. SCR (SSC Control Register, ExtPage 0xa0, Address 0x1a), page 45. Revised section 10.3 Crystal Requirements, page 57.

Revised section 10.4 Oscillator/External Clock Requirements, page 57.

Table of Contents

1.GENERAL DESCRIPTION (1)

2.FEATURES (2)

3.SYSTEM APPLICATIONS (3)

3.1.A PPLICATION D IAGRAM (RTL8211E-VB) (3)

3.2.A PPLICATION D IAGRAM (RTL8211EG-VB) (4)

3.3.A PPLICATION D IAGRAM (RTL8211E-VL) (4)

4.BLOCK DIAGRAM (5)

5.PIN ASSIGNMENTS (6)

5.1.RTL8211E-VB/RTL8211E-VL P IN A SSIGNMENTS (48-P IN QFN) (6)

5.2.P ACKAGE I DENTIFICATION (6)

5.3.RTL8211EG-VB P IN A SSIGNMENTS (64-P IN QFN) (7)

5.4.P ACKAGE I DENTIFICATION (7)

6.PIN DESCRIPTIONS (8)

6.1.T RANSCEIVER I NTERFACE (8)

6.2.C LOCK (8)

6.3.RGMII (9)

6.4.GMII(RTL8211EG-VB O NLY) (9)

6.5.M ANAGEMENT I NTERFACE (10)

6.6.R ESET (11)

6.7.M ODE S ELECTION (11)

6.8.LED D EFAULT S ETTINGS (11)

6.9.R EGULATOR AND R EFERENCE (12)

6.10.P OWER AND G ROUND (12)

6.11.N OT C ONNECTED (12)

7.FUNCTION DESCRIPTION (13)

7.1.T RANSMITTER (13)

7.1.1.RGMII/GMII (1000Mbps) Mode (13)

7.1.2.MII (100Mbps) Mode (13)

7.1.3.MII (10Mbps) Mode (13)

7.2.R ECEIVER (13)

7.2.1.RGMII/GMII (1000Mbps) Mode (13)

7.2.2.MII (100Mbps) Mode (13)

7.2.3.MII (10Mbps) Mode (14)

7.3.E NERGY E FFICIENT E THERNET (EEE) (14)

7.4.W AKE-O N-LAN(WOL) (14)

7.5.I NTERRUPT (15)

7.6.MDI I NTERFACE (15)

7.7.H ARDWARE C ONFIGURATION (16)

7.8.LED AND PHY A DDRESS C ONFIGURATION (17)

7.9.G REEN E THERNET (1000/100M BPS M ODE O NLY) (18)

7.9.1.Cable Length Power Saving (18)

7.9.2.Register Setting (18)

7.10.MAC/PHY I NTERFACE (19)

7.10.1.MII (19)

Integrated 10/100/1000M Ethernet Transceiver v Track ID: JATR-8275-15 Rev. 1.8

7.10.2.GMII (19)

7.10.3.RGMII (19)

7.10.4.Management Interface (19)

7.10.5.Access to Extension Page (ExtPage) (21)

7.10.6.Access to MDIO Manageable Device (MMD) (21)

7.11.A UTO-N EGOTIATION (22)

7.11.1.Auto-Negotiation Priority Resolution (24)

7.11.2.Auto-Negotiation Master/Slave Resolution (25)

7.11.3.Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution (25)

7.12.C ROSSOVER D ETECTION AND A UTO-C ORRECTION (26)

7.13.LED C ONFIGURATION (27)

7.14.P OLARITY C ORRECTION (28)

7.15.P OWER (29)

7.16.PHY R ESET (H ARDWARE R ESET) (29)

8.REGISTER DESCRIPTIONS (30)

8.1.R EGISTER M APPING AND D EFINITIONS (30)

8.2.MMD R EGISTER M APPING AND D EFINITION (31)

8.3.E XT P AGE R EGISTER M APPING AND D EFINITION (31)

8.4.R EGISTER T ABLES (31)

8.4.1.BMCR (Basic Mode Control Register, Address 0x00) (31)

8.4.2.BMSR (Basic Mode Status Register, Address 0x01) (33)

8.4.3.PHYID1 (PHY Identifier Register 1, Address 0x02) (34)

8.4.4.PHYID2 (PHY Identifier Register 2, Address 0x03) (34)

8.4.5.ANAR (Auto-Negotiation Advertising Register, Address 0x04) (34)

8.4.6.ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) (35)

8.4.7.ANER (Auto-Negotiation Expansion Register, Address 0x06) (36)

8.4.8.ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07) (36)

8.4.9.ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08) (37)

8.4.10.GBCR (1000Base-T Control Register, Address 0x09) (37)

8.4.11.GBSR (1000Base-T Status Register, Address 0x0A) (38)

8.4.12.MACR (MMD Access Control Register, Address 0x0D) (38)

8.4.13.MAADR (MMD Access Address Data Register, Address 0x0E) (39)

8.4.14.GBESR (1000Base-T Extended Status Register, Address 0x0F) (39)

8.4.15.PHYCR (PHY Specific Control Register, Address 0x10) (39)

8.4.16.PHYSR (PHY Specific Status Register, Address 0x11) (40)

8.4.17.INER (Interrupt Enable Register, Address 0x12) (41)

8.4.18.INSR (Interrupt Status Register, Address 0x13) (42)

8.4.19.RXERC (Receive Error Counter, Address 0x18) (42)

8.4.20.LDPSR (Link Down Power Saving Register, Address 0x1B) (42)

8.4.21.EPAGSR (Extension Page Select Register, Address 0x1E) (42)

8.4.22.PAGSEL (Page Select Register, Address 0x1F) (43)

8.4.23.PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) (43)

8.4.24.PS1R (PCS Status1 Register, MMD Device 3, Address 0x01) (43)

8.4.25.EEECR (EEE Capability Register, MMD Device 3, Address 0x14) (44)

8.4.26.EEEWER (EEE Wake Error Register, MMD Device 3, Address 0x16) (44)

8.4.27.EEEAR (EEE Advertisement Register, MMD Device 7, Address 0x3c) (44)

8.4.28.EEELPAR (EEE Link Partner Ability Register, MMD Device 7, Address 0x3d) (44)

https://www.wendangku.net/doc/1f7182600.html,CR (LED Action Control Register, ExtPage 0x2c, Address 0x1a) (45)

8.4.30.LCR (LED Control Register, ExtPage 0x2c, Address 0x1c) (45)

8.4.31.ACCR (Auto-Crossover Control Register, ExtPage 0x2d, Address 0x18) (45)

8.4.32.SCR (SSC Control Register, ExtPage 0xa0, Address 0x1a) (45)

Integrated 10/100/1000M Ethernet Transceiver vi Track ID: JATR-8275-15 Rev. 1.8

9.1.PCB L AYOUT (46)

9.2.I NDUCTOR AND C APACITOR P ARTS L IST (47)

9.3.M EASUREMENT C RITERIA (48)

9.4.E FFICIENCY M EASUREMENT (54)

9.5.P OWER S EQUENCE (55)

10.CHARACTERISTICS (56)

10.1.A BSOLUTE M AXIMUM R ATINGS (56)

10.2.R ECOMMENDED O PERATING C ONDITIONS (56)

10.3.C RYSTAL R EQUIREMENTS (57)

10.4.O SCILLATOR/E XTERNAL C LOCK R EQUIREMENTS (57)

10.5.DC C HARACTERISTICS (58)

10.6.AC C HARACTERISTICS (59)

10.6.1.MDC/MDIO Timing (59)

10.6.2.MII Transmission Cycle Timing (RTL8211EG-VB Only) (60)

10.6.3.MII Reception Cycle Timing (RTL8211EG-VB Only) (61)

10.6.4.GMII Timing Modes (RTL8211EG-VB Only) (62)

10.6.5.RGMII Timing Modes (63)

11.MECHANICAL DIMENSIONS (66)

11.1.RTL8211E-VB/RTL8211E-VL M ECHANICAL D IMENSIONS (48-P IN QFN) (66)

11.2.M ECHANICAL D IMENSIONS N OTES (RTL8211E-VB/RTL8211E-VL) (66)

11.3.RTL8211EG-VB M ECHANICAL D IMENSIONS (64-P IN QFN) (67)

11.4.M ECHANICAL D IMENSIONS N OTES (RTL8211EG-VB) (67)

12.ORDERING INFORMATION (68)

List of Tables

T ABLE 1.T RANSCEIVER I NTERFACE (8)

T ABLE 2.C LOCK (8)

T ABLE 3.RGMII (9)

T ABLE 4.GMII(RTL8211EG-VB O NLY) (9)

T ABLE 5.M ANAGEMENT I NTERFACE (10)

T ABLE 6.R ESET (11)

T ABLE 7.M ODE S ELECTION (11)

T ABLE 8.LED D EFAULT S ETTINGS (11)

T ABLE 9.R EGULATOR AND R EFERENCE (12)

T ABLE 10.P OWER AND G ROUND (12)

T ABLE 11.N OT C ONNECTED (12)

T ABLE 12.CONFIG P INS VS.C ONFIGURATION R EGISTER (16)

T ABLE 13.C ONFIGURATION R EGISTER D EFINITIONS (16)

T ABLE 14.M ANAGEMENT F RAME F ORMAT (20)

T ABLE 15.M ANAGEMENT F RAME D ESCRIPTION (20)

T ABLE 16.1000B ASE-T B ASE AND N EXT P AGE B IT A SSIGNMENTS (22)

T ABLE 17.LED D EFAULT D EFINITIONS (27)

T ABLE 18.LED R EGISTER T ABLE (27)

T ABLE 19.LED C ONFIGURATION T ABLE (28)

T ABLE 20.R EGISTER A CCESS T YPES (30)

Integrated 10/100/1000M Ethernet Transceiver vii Track ID: JATR-8275-15 Rev. 1.8

T ABLE 22.MMD R EGISTER M APPING AND D EFINITION (31)

T ABLE 23.E XT P AGE R EGISTER M APPING AND D EFINITION (31)

T ABLE 24.BMCR(B ASIC M ODE C ONTROL R EGISTER,A DDRESS 0X00) (31)

T ABLE 25.BMSR(B ASIC M ODE S TATUS R EGISTER,A DDRESS 0X01) (33)

T ABLE 26.PHYID1(PHY I DENTIFIER R EGISTER 1,A DDRESS 0X02) (34)

T ABLE 27.PHYID2(PHY I DENTIFIER R EGISTER 2,A DDRESS 0X03) (34)

T ABLE 28.ANAR(A UTO-N EGOTIATION A DVERTISING R EGISTER,A DDRESS 0X04) (34)

T ABLE 29.ANLPAR(A UTO-N EGOTIATION L INK P ARTNER A BILITY R EGISTER,A DDRESS 0X05) (35)

T ABLE 30.ANER(A UTO-N EGOTIATION E XPANSION R EGISTER,A DDRESS 0X06) (36)

T ABLE 31.ANNPTR(A UTO-N EGOTIATION N EXT P AGE T RANSMIT R EGISTER,A DDRESS 0X07) (36)

T ABLE 32.ANNPRR(A UTO-N EGOTIATION N EXT P AGE R ECEIVE R EGISTER,A DDRESS 0X08) (37)

T ABLE 33.GBCR(1000B ASE-T C ONTROL R EGISTER,A DDRESS 0X09) (37)

T ABLE 34.GBSR(1000B ASE-T S TATUS R EGISTER,A DDRESS 0X0A) (38)

T ABLE 35.MACR(MMD A CCESS C ONTROL R EGISTER,A DDRESS 0X0D) (38)

T ABLE 36.MAADR(MMD A CCESS A DDRESS D ATA R EGISTER,A DDRESS 0X0E) (39)

T ABLE 37.GBESR(1000B ASE-T E XTENDED S TATUS R EGISTER,A DDRESS 0X0F) (39)

T ABLE 38.PHYCR(PHY S PECIFIC C ONTROL R EGISTER,A DDRESS 0X10) (39)

T ABLE 39.PHYSR(PHY S PECIFIC S TATUS R EGISTER,A DDRESS 0X11) (40)

T ABLE 40.INER(I NTERRUPT E NABLE R EGISTER,A DDRESS 0X12) (41)

T ABLE 41.INSR(I NTERRUPT S TATUS R EGISTER,A DDRESS 0X13) (42)

T ABLE 42.RXERC(R ECEIVE E RROR C OUNTER,A DDRESS 0X18) (42)

T ABLE 43.LDPSR(L INK D OWN P OWER S AVING R EGISTER,A DDRESS 0X1B) (42)

T ABLE 44.EPAGSR(E XTENSION P AGE S ELECT R EGISTER,A DDRESS 0X1E) (42)

T ABLE 45.PAGSEL(P AGE S ELECT R EGISTER,A DDRESS 0X1F) (43)

T ABLE 46.PC1R(PCS C ONTROL 1R EGISTER,MMD D EVICE 3,A DDRESS 0X00) (43)

T ABLE 47.PS1R(PCS S TATUS 1R EGISTER,MMD D EVICE 3,A DDRESS 0X01) (43)

T ABLE 48.EEECR(EEE C APABILITY R EGISTER,MMD D EVICE 3,A DDRESS 0X14) (44)

T ABLE 49.EEEWER(EEE W AKE E RROR R EGISTER,MMD D EVICE 3,A DDRESS 0X16) (44)

T ABLE 50.EEEAR(EEE A DVERTISEMENT R EGISTER,MMD D EVICE 7,A DDRESS 0X3C) (44)

T ABLE 51.EEELPAR(EEE L INK P ARTNER A BILITY R EGISTER,MMD D EVICE 7,A DDRESS 0X3D) (44)

T ABLE https://www.wendangku.net/doc/1f7182600.html,CR(LED A CTION C ONTROL R EGISTER,E XT P AGE 0X2C,A DDRESS 0X1A) (45)

T ABLE 53.LCR(LED C ONTROL R EGISTER,E XT P AGE 0X2C,A DDRESS 0X1C) (45)

T ABLE 54.ACCR(A UTO-C ROSSOVER C ONTROL R EGISTER,E XT P AGE 0X2D,A DDRESS 0X18) (45)

T ABLE 55.SCR(SSC C ONTROL R EGISTER,E XT P AGE 0XA0,A DDRESS 0X1A) (45)

T ABLE 56.I NDUCTOR AND C APACITOR P ARTS L IST (47)

T ABLE 57.P OWER S EQUENCE P ARAMETERS (55)

T ABLE 58.A BSOLUTE M AXIMUM R ATINGS (56)

T ABLE 59.R ECOMMENDED O PERATING C ONDITIONS (56)

T ABLE 60.C RYSTAL R EQUIREMENTS (57)

T ABLE 61.O SCILLATOR/E XTERNAL C LOCK R EQUIREMENTS (57)

T ABLE 62.DC C HARACTERISTICS (58)

T ABLE 63.MDC/MDIO M ANAGEMENT T IMING P ARAMETERS (59)

T ABLE 64.MII T RANSMISSION C YCLE T IMING (60)

T ABLE 65.MII R ECEPTION C YCLE T IMING (61)

T ABLE 66.GMII T IMING P ARAMETERS (62)

T ABLE 67.RGMII T IMING P ARAMETERS (65)

T ABLE 68.O RDERING I NFORMATION (68)

Integrated 10/100/1000M Ethernet Transceiver viii Track ID: JATR-8275-15 Rev. 1.8

List of Figures

F IGURE 1.A PPLICATION D IAGRAM (RTL8211E-VB) (3)

F IGURE 2.A PPLICATION D IAGRAM (RTL8211EG-VB) (4)

F IGURE 3.A PPLICATION D IAGRAM (RTL8211EG-VL) (4)

F IGURE 4.B LOCK D IAGRAM (5)

F IGURE 5.RTL8211E-VB/RTL8211E-VL P IN A SSIGNMENTS (48-P IN QFN) (6)

F IGURE 6.RTL8211EG-VB P IN A SSIGNMENTS (64-P IN QFN) (7)

F IGURE 7.LED AND PHY A DDRESS C ONFIGURATION (17)

F IGURE 8.MDC/MDIO R EAD T IMING (20)

F IGURE 9.MDC/MDIO W RITE T IMING (21)

F IGURE 10.PHY R ESET T IMING (29)

F IGURE 11.S WITCHING R EGULATOR (46)

F IGURE 12.I NPUT V OLTAGE O VERSHOOT <4V(G OOD) (48)

F IGURE 13.I NPUT V OLTAGE O VERSHOOT >4V(B AD) (48)

F IGURE 14.C ERAMIC 10μF0603(X5R)(G OOD) (49)

F IGURE 15.L=GLK2510P-2R2M,C=C ERAMIC 4.7μF0805X5R TDK(R IPPLE 12.4M V) (49)

F IGURE 16.L=GLK2510P-2R2M,C=C ERAMIC 10μF0603X5R YAGEO(R IPPLE 13.2M V) (50)

F IGURE 17.L=GLK2510P-4R7M,C=C ERAMIC 4.7μF0805X5R TDK(R IPPLE 12M V) (50)

F IGURE 18.L=GLK2510P-4R7M,C=C ERAMIC 10μF0603X5R YAGEO(R IPPLE 11.2M V) (51)

F IGURE 19.L=GTSD32P-2R2M,C=C ERAMIC 4.7μF0805X5R TDK(R IPPLE 9.2M V) (51)

F IGURE 20.C ERAMIC 10μF(Y5V)(B AD) (52)

F IGURE 21.E LECTROLYTIC 100μF(R IPPLE T OO H IGH) (52)

F IGURE 22.GTSD32P-2R2M(G OOD) (53)

F IGURE 23.1μH B EAD (B AD) (53)

F IGURE 24.S WITCHING R EGULATOR E FFICIENCY M EASUREMENT C HECKPOINT (54)

F IGURE 25.P OWER S EQUENCE (55)

F IGURE 26.MDC/MDIO S ETUP,H OLD T IME, AND V ALID FROM MDC R ISING E DGE T IME D EFINITIONS (59)

F IGURE 27.MDC/MDIO M ANAGEMENT T IMING P ARAMETERS (59)

F IGURE 28.MII I NTERFACE S ETUP/H OLD T IME D EFINITIONS (60)

F IGURE 29.MII T RANSMISSION C YCLE T IMING (60)

F IGURE 30.MII R ECEPTION C YCLE T IMING (61)

F IGURE 31.GMII T IMING (62)

F IGURE 32.RGMII T IMING M ODES (F OR TXC) (63)

F IGURE 33.RGMII T IMING M ODES (F OR RXC) (64)

Integrated 10/100/1000M Ethernet Transceiver ix Track ID: JATR-8275-15 Rev. 1.8

1.General Description

The Realtek RTL8211E-VB-CG/RTL8211E-VL-CG/RTL8211EG-VB-CG are highly integrated Ethernet transceivers that comply with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3 standards. They provide all the necessary physical layer functions to transmit and receive Ethernet packets over CAT.5 UTP cable.

The RTL8211E-VB(VL)/RTL8211EG-VB uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable high-speed data transmission and reception over UTP cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented in the RTL8211E-VB(VL)/RTL8211EG-VB to provide robust transmission and reception capabilities at 10Mbps, 100Mbps, or 1000Mbps.

Data transfer between MAC and PHY is via the Reduced Gigabit Media Independent Interface (RGMII) or Gigabit Media Independent Interface (GMII) for 1000Base-T, 10Base-T, and 100Base-TX. The RTL8211E-VB supports 3.3V or 2.5V signaling for RGMII; the RTL8211EG-VB provides 3.3V or 2.5V signaling for RGMII/GMII, and the RTL8211E-VL supports 1.5/1.8V signaling for RGMII.

Integrated 10/100/1000M Ethernet Transceiver 1Track ID: JATR-8275-15 Rev. 1.8

Integrated 10/100/1000M Ethernet Transceiver 2 Track ID: JATR-8275-15 Rev. 1.8

2. Features

1000Base-T IEEE 802.3ab Compliant 100Base-TX IEEE 802.3u Compliant 10Base-T IEEE 802.3 Compliant Supports RGMII (RTL8211E-VB,

RTL8211E-VL, RTL8211EG-VB) Supports GMII (RTL8211EG-VB) Supports IEEE 802.3az-2010 (Energy

Efficient Ethernet) Built-in Wake-on-LAN (WOL) Supports Interrupt function Supports Parallel Detection

Crossover Detection & Auto-Correction Automatic polarity correction

Supports PHYRSTB core power Turn-Off Baseline Wander Correction Supports 120m for CAT.5 cable in

1000Base-T Supports 3.3V or 2.5V signaling for RGMII

(RTL8211E-VB) and RGMII/GMII (RTL8211EG-VB) Supports 1.5V and 1.8V signaling for RGMII

(RTL8211E-VL) Supports 25/50MHz external crystal or OSC Provides 125MHz clock source for MAC Provides 3 network status LEDs Supports Link Down power saving Green Ethernet (1000/100Mbps mode only) Built-in switching regulator Packages

48-pin QFN (RTL8211E-VB,

RTL8211E-VL)

64-pin QFN (RTL8211EG-VB)

0.11μm process with very low power

consumption

Integrated 10/100/1000M Ethernet Transceiver 3 Track ID: JATR-8275-15 Rev. 1.8

3. System Applications

DTV (Digital TV) MAU (Media Access Unit)

CNR (Communication and Network Riser) Game Console

Printer and Office Machine DVD Player and Recorder

Ethernet Hub Ethernet Switch

In addition, can be used in any embedded system with an Ethernet MAC that needs a UTP physical connection.

3.1.

Application Diagram (RTL8211E-VB)

Figure 1. Application Diagram (RTL8211E-VB)

Integrated 10/100/1000M Ethernet Transceiver 4

Track ID: JATR-8275-15 Rev. 1.8

3.2.

Application Diagram (RTL8211EG-VB)

Figure 2. Application Diagram (RTL8211EG-VB)

3.3.

Application Diagram (RTL8211E-VL)

Figure 3. Application Diagram (RTL8211EG-VL)

Integrated 10/100/1000M Ethernet Transceiver 5 Track ID: JATR-8275-15 Rev. 1.8

4.

Block Diagram

Figure 4. Block Diagram

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Track ID: JATR-8275-15 Rev. 1.8

5. Pin Assignments

5.1. RTL8211E-VB/RTL8211E-VL Pin Assignments

(48-Pin QFN)

Figure 5. RTL8211E-VB/RTL8211E-VL Pin Assignments (48-Pin QFN)

5.2. Package Identification

Green package is indicated by the ‘G’ in GXXXV (Figure 5). The version is shown in the location marked ‘V’.

Integrated 10/100/1000M Ethernet Transceiver 7 Track ID: JATR-8275-15 Rev. 1.8

5.3. RTL8211EG-VB Pin Assignments (64-Pin QFN)

DVDD33LED1/PHY_AD1

LED2RXD 3

T X E R

GND VDDREG

CKXTAL2

CKXTAL1AVDD33AVDD10LED0/PHY_AD0MDC ENSWREG

PMEB INTB MDIO

RXDV/PHY_AD2RSET D V D D 10

T X D 5

T X D 4

T X C L K

T X D 3

T X D 1

D V D D 33

T X D 2

P H Y R S T B

T X D 0

G T X _C L K

T X D 7

D V D D 10

T X D 6

RXD 1RXD2RXD0

DVDD33

RXC RXD4/SELRGV DVDD33

RXD5/TXDLY RXD6/RXDLY RXD7/AN0RXER /AN1T X E N

COL/Mode NC

CRS R E G _O U T

M D I [0]+

M D I A V D D 10

M D I M D I A V D D 33

M D I A V D D 10

M D I M D I N C

G N D

G N D

C L K 125

M D I 1065 GND (Exposed Pad)

[0]-

[1]+

[1]-

[2]+

[2]-

[3]+

[3]-

Figure 6. RTL8211EG-VB Pin Assignments (64-Pin QFN)

5.4. Package Identification

Green package is indicated by the ‘G’ in GXXXV (Figure 6). The version is shown in the location marked ‘V’.

Integrated 10/100/1000M Ethernet Transceiver 8

Track ID: JATR-8275-15 Rev. 1.8

6. Pin Descriptions

Some pins have multiple functions. Refer to the Pin Assignments figure on page 6 (RTL8211E-VB/RTL8211E-VL) and page 7 (RTL8211EG-VB) for a graphical representation.

I: Input LI:Latched Input During Power up or Reset O: Output IO:Bi-Directional Input and Output

P: Power PD:Internal Pull Down During Power On Reset

PU: Internal Pull Up During Power On Reset OD:Open Drain

G: Ground

6.1. Transceiver Interface

Table 1. Transceiver Interface

Pin No. (48-pin) Pin No. (64-pin)

Pin Name Type Description

1 5 MDI[0]+ IO

2 6 MDI[0]?

IO In MDI mode, this is the first pair in 1000Base-T, i.e., the BI_DA+/- pair, and

is the transmit pair in 10Base-T and 100Base-TX.

In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in 10Base-T and 100Base-TX. 4 8 MDI[1]+ IO 5 9 MDI[1]?

IO In MDI mode, this is the second pair in 1000Base-T, i.e., the BI_DB+/- pair,

and is the receive pair in 10Base-T and 100Base-TX.

In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. 7 11 MDI[2]+ IO

8 12 MDI[2]?

IO In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. 10 14 MDI[3]+ IO

11 15 MDI[3]?

IO In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair.

6.2. Clock

Table 2. Clock

Pin No. (48-pin) Pin No. (64-pin) Pin Name Type Description 42 61 CKXTAL1

I

25/50MHz Crystal Input.

If a 25/50MHz oscillator is used, connect CKXTAL1 to the oscillator’s output (see section 10.3, page 57 for clock source specifications).

43 62 CKXTAL2 O 25/50MHz Crystal Output.

Connect to GND if an external 25/50MHz oscillator drives CKXTAL1.

46 1 CLK125 O/PD 125MHz Reference Clock Generated from Internal PLL.

This pin should be kept floating if the 125MHz clock is not used by MAC.

Note: To conduct crystal ppm measurement for models transiting from the RTL8211D to the RTL8211E, the design of the external circuit must be modified, i.e. the output resistor should be connected to CKXTAL1 rather than CKXTAL2.

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Track ID: JATR-8275-15 Rev. 1.8

6.3. RGMII

Table 3. RGMII

Pin No. (48-pin) Pin No. (64-pin) Pin Name Type (48-pin) Type (64-pin)

Description 22 - TXC I/PU

- 34 GTX_CLK I The transmit reference clock will be 125MHz, 25MHz, or 2.5MHz depending on speed. 23 36 TXD0 I/PD 24 39 TXD1 I/PD 25 40 TXD2 I/PD 26 41 TXD3 I/PU

Transmit Data. Data is transmitted from MAC to PHY via TXD[3:0]. 27 - TXCTL - 35 TXEN I

Receive Control Signal from the MAC. 19 24 RXC O The continuous receive reference clock will be 125MHz,

25MHz, or 2.5MHz, and is derived from the received data stream.

14 19 RXD0 O/LI/PU O

16 21 RXD1 O/LI/PD O

17 22 RXD2 O/LI/PU O 18 23 RXD3 O/LI/PU O

Receive Data. Data is transmitted from PHY to MAC via RXD[3:0]. 13 - RXCTL

- 18 RXDV O/LI/PD Transmit Control Signal to the MAC. 16 27 TXDLY O/LI/PD RGMII Transmit Clock Timing Control.

1: Add 2ns delay to TXC for TXD latching

32 28 RXDLY O/LI/PD RGMII Receiver Clock Timing Control.

1: Add 2ns delay to RXC for RXD latching

6.4. GMII (RTL8211EG-VB Only)

Table 4. GMII (RTL8211EG-VB Only)

Pin No. (48-pin) Pin No. (64-pin) Pin Name Type Description - 34 GTX_CLK I The transmit reference clock is 125MHz.

-

42 TXCLK

O

The transmit reference clock will be 25MHz, or 2.5MHz depending on speed.

- 36 TXD0 I - 39 TXD1 I

- 40 TXD2 I - 41 TXD3 I - 43 TXD4 I - 44 TXD5 I - 45 TXD6 I - 46 TXD7 I Transmit Data.

Data is transmitted from MAC to PHY via TXD[7:0]. - 35 TXEN I Transmit Enable.

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Pin No. (48-pin) Pin No. (64-pin)

Pin Name Type Description - 47 TXER I Transmit Error.

When both TXER and TXEN are asserted, the transmit error symbol is transmitted onto the cable.

When TXER is asserted and TXEN is de-asserted, the carrier extension symbol is transmitted onto the cable.

Connect to GND if MAC does not have a TXER pin.

- 24 RXC O The continuous receive reference clock will be 125MHz, 25MHz, or

2.5MHz. It is derived from the received data stream.

- 19 RXD0 O - 21 RXD1 O

- 22 RXD2 O - 23 RXD3 O - 25 RXD4 O/LI/PU - 27 RXD5 O/LI/PD - 28 RXD6 O/LI/PD - 29 RXD7 O/LI/PU Receive Data.

Data is transmitted from PHY to MAC via RXD[7:0]. - 18 RXDV O/LI/PD Receive Data Valid. - 30 RXER O/LI/PU Receive Error.

When both RXER and RXDV are asserted, an error symbol is received from the cable.

When RXER is asserted and RXDV is de-asserted, it means false carrier or carrier extension symbol is detected on the cable.

- 31 COL/Mode O/LI/PD Collision In Half Duplex Mode. - 32 CRS O/PD Carrier Sense.

6.5. Management Interface

Table 5. Management Interface

Pin No. (48-pin) Pin No. (64-pin) Pin Name Type Description

30 53 MDC I/PU Management Data Clock. 31

54 MDIO IO/PU Input/Output of Management Data.

Pull up 3.3V for 3.3V RGMII (RTL8211E/EG-VB) & GMII (RTL8211EG-VB).Pull up 2.5V for 2.5V RGMII (RTL8211E/EG-VB) & GMII (RTL8211EG-VB).Pull up 1.5/1.8V for 1.5/1.8V RGMII (RTL8211E-VL).

33 55 PMEB O/OD Power Management Event (supports 3.3V and 5V pull up).

Set low if received a magic packet or wake up frame; active low. This pin will be kept floating if this function is not used.

20 56 INTB O/OD Interrupt.

Set low if status changed; active low.

This pin should be kept floating if this function is not used.

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Track ID: JATR-8275-15 Rev. 1.8

6.6. Reset

Table 6. Reset Pin No. (48-pin) Pin No. (64-pin) Pin Name Type Description

29

38

PHYRSTB

I

Hardware Reset. Active low.

For a complete PHY reset, this pin must be asserted low for at least 10ms.All registers will be cleared after a hardware reset.

6.7. Mode Selection

Table 7. Mode Selection

Pin No. (48-pin) Pin No. (64-pin) Pin Name Type (48-pin) Type (64-pin)Description 34 50 PHY_AD0 O/LI/PU 35 51 PHY_AD1 O/LI/PD 13 18 PHY_AD2 O/LI/PD

PHY Address Configuration. 17 29 AN0 O/LI/PU

18 30 AN1 O/LI/PU Auto-Negotiation (NWay) Configuration. - 31 COL/Mode - O/LI/PD RGMII/GMII Mode Configuration.

Pull Up for RGMII. Pull Down for GMII.

14 25 SELRGV O/LI/PU Pull Up for 3.3V RGMII (RTL8211E/EG-VB) & GMII

(RTL8211EG-VB).

Pull Down for 2.5V RGMII (RTL8211E/EG-VB) & GMII (RTL8211EG-VB).

Pull Up for 1.5/1.8V RGMII (RTL8211E-VL).

Note: For theRTL8211E-VL, SELRGV should not be Pulled Down.

Note: See section 7.7 Hardware Configuration, page 16 for details.

6.8. LED Default Settings

Table 8. LED Default Settings Pin No. (48-pin) Pin No. (64-pin)

Pin Name Type Description

34 50 LED0 O/LI/PU Blinking =Transmitting or Receiving. 35 51 LED1 O/LI/PD Low=Link Up (Any speed)

High=Link Down (Any speed)

Note: High/Low active depends on hardware configuration setting.

32 52 LED2 O/LI/PD No default setting. See Table 19 LED Configuration Table, page 28 for

configuration details.

Note: See section 7.13 LED Configuration, page 27 for details.

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