Bridgeless SEPIC 1
Bridgeless SEPIC Recti?er With Unity Power Factor and Reduced Conduction Losses
Esam H.Ismail,Senior Member,IEEE
Abstract—In this paper,a new bridgeless single-phase ac–dc converter with an automatic power factor correction(PFC)is proposed.The proposed recti?er is based on the single-ended primary inductance converter(SEPIC)topology and it utilizes a bidirectional switch and two fast diodes.The absence of an input diode bridge and the presence of only one diode in the?owing-current path during each switching cycle result in less conduction loss and improved thermal management compared to existing PFC recti?ers.Other advantages include simple control circuitry,re-duced switch voltage stress,and low electromagnetic-interference noise.Performance comparison between the proposed and the conventional SEPIC PFC recti?er is performed.Simulation and experimental results are presented to demonstrate the feasibility of the proposed technique.
Index Terms—Bridgeless recti?er,discontinuous current mode (DCM),power factor correction(PFC),recti?er,single-ended pri-mary inductance converter(SEPIC),total harmonic distortion (THD).
I.I NTRODUCTION
I N RECENT years,the demand for improving power quality
of the ac system has become a great concern due to the rapidly increased numbers of electronic equipment.To reduce harmonic contamination in power lines and improve the trans-mission ef?ciency,power factor correction(PFC)research be-came an active topic in power electronics,and signi?cant efforts have been made on the developments of the PFC converters [1]–[4].As a matter of fact,the PFC circuits are becoming mandatory on single-phase power supplies as more stringent power quality regulations and strict limits on the total harmonic distortion(THD)of input current are imposed[5].
The preferable type of PFC is active PFC since it makes the load behave like a pure resistor,leading to near-unity load power factor and generating negligible harmonics in the input line current[6].Most active PFC circuits as well as switched-mode power supplies in the market today comprise a front-end bridge recti?er,followed by a high-frequency dc–dc converter such as a boost,a buck–boost,a Cuk,a single-ended primary inductance converter(SEPIC),and a?yback converter.This approach is suitable for a low-to-medium power range.As the power level increases,the high conduction loss caused by the high forward voltage drop of the diode bridge begins to degrade the overall system ef?ciency,and the heat generated within
Manuscript received April2,2008;revised September18,2009.First published October31,2008;current version published April1,2009.
The author is with the Department of Electrical Engineering,College of Technological Studies,Al-Shaab36051,Kuwait(e-mail:eismail@https://www.wendangku.net/doc/1b9305023.html,). Digital Object Identi?er
10.1109/TIE.2008.2007552
Fig.1.Conventional bridgeless boost recti?er[7].
the bridge recti?er may destroy the individual diodes.Hence,
it becomes necessary to utilize a bridge recti?er with higher
current-handling capability or heat-dissipating characteristics.
This increases the size and cost of the power supply,which is
unacceptable for an ef?cient design.Another reason for high
conduction losses in conventional active PFC circuits is due to
the fact that during each switching cycle,there are always three
power semiconductors in the?owing-current path(two slow-
recovery diodes plus an active switch or a fast-recovery diode).
In an effort to improve the power supply ef?ciency,a num-
ber of bridgeless PFC circuit topologies have been proposed
[7]–[24].All the presented bridgeless topologies so far im-
plement a boost-type circuit con?guration(also referred to as
dual-boost PFC recti?ers)because of its low cost and its high
performance in terms of ef?ciency,power factor,and simplic-
ity.In[25],a systematic review of the bridgeless PFC boost
recti?er implementations that have received the most attention
is presented along with their performance comparison with the
conventional PFC boost recti?er.A simpli?ed schematic of the
conventional bridgeless PFC boost recti?er is shown in Fig.1.
The switching conduction sequences for the recti?er of Fig.1
are as follows:1)during positive ac line cycle,Q1?D q2,
D1?D q2,and2)during negative ac line cycle,Q2?D q1,
D2?D q1.Thus,during each switching cycle,the current path
goes through only two semiconductor devices instead of three.
As a result,the total conduction losses on the semiconductor de-
vices will be considerably lower compared to the conventional
PFC boost recti?er.These features have led power supply com-
panies to start looking for bridgeless PFC circuit topologies.
Although the bridgeless boost recti?er is very simple and
popular,it has the same major practical drawbacks as the
conventional boost converter.These drawbacks are that the
dc output voltage is always higher than the peak input volt-
age,input–output isolation cannot be easily implemented,high
startup inrush current,as well as a lack of current limiting
during overload conditions.Moreover,it is well known that 0278-0046/$25.00?2009IEEE
Fig. 2.(a)Proposed bridgeless SEPIC recti?er.(b)Circuit diagram for positive half-line cycle.(c)Circuit diagram for negative half-line cycle.
the boost converter operating in discontinuous current mode (DCM)can offer a number of advantages,such as inherent PFC function,very simple control,soft turn-on of the main switch,and reduced diode reversed-recovery losses.However, the DCM operation requires a high-quality boost inductor since it must switch extremely high peak ripple currents and voltages. As a result,a more robust input?lter must be employed to suppress the high-frequency components of the pulsating input current,which increases the overall weight and cost of the recti?er.
In order to overcome these problems,a new bridgeless PFC circuit based on the SEPIC topology is introduced in this paper. Unlike the boost converter,the SEPIC and Cuk converters offer several advantages in PFC applications,such as easy implemen-tation of transformer isolation,inherent inrush current limita-tion during startup and overload conditions,lower input current ripple,and less electromagnetic interference(EMI)associated with the DCM topology[26]–[30].The proposed bridgeless SEPIC recti?er is shown in Fig.2(a).This circuit is formed by connecting two SEPICs,one with a positive input source and the other having an inverted input source.The proposed recti?er utilizes a bidirectional switch and two fast diodes.However, the two power switches,namely,Q1and Q2,can be driven with the same PWM signal,which signi?cantly simpli?es the implementation of the control circuit.The operational circuits during a positive and a negative half-line cycle are shown in Fig.2(b)and(c),respectively.Note that during each switching cycle,there is either one or two semiconductors in the?owing-current path;hence,the conduction losses as well as the thermal stresses on the semiconductor devices are further reduced, and the circuit ef?ciency is improved compared with that of the bridgeless boost recti?er.Another advantage of the pro-posed recti?er is a reduction in the semiconductor voltage stress as compared with that of the conventional SEPIC PFC recti?er. The voltage stress is reduced to a level that is comparable with that of the PFC boost recti?er.On the other hand,compo-nents’current stresses are comparable with their counterparts in the conventional SEPIC.The proposed recti?er structure uti-lizes three inductors,which are often described as a disadvan-tage.However,the three inductors can be coupled on the same magnetic core[31],allowing considerable size and cost reduc-tion,and additionally,the“near-zero-ripple-current”condition at the input port of the recti?er can be achieved without com-promising performance.This condition is very desirable,partic-ularly for the DCM operation,because the generated EMI noise is minimized,reducing input?ltering requirements dramati-cally.Moreover,both the conventional SEPIC PFC recti?er and the proposed recti?er of Fig.2(a)have the same count of total components when the coupled inductor technique is imple-mented.The major drawback of the proposed bridgeless SEPIC PFC recti?er in Fig.2(a)is that it requires an additional gate-drive transformer.
The remainder of this paper is organized as follows.Prin-ciple of operation and theoretical analysis are presented in Section II.Detailed analysis,modeling,and comparisons are presented in Section III.A simpli?ed design procedure example and simulation results are included in Section IV.Section V provides a detailed analysis of the proposed converter with coupled inductors.Finally,results from a laboratory prototype and conclusion are given in Sections VI and VII,respectively.
II.O PERATION OF THE P ROPOSED B RIDGELESS PFC
SEPIC R ECTIFIER
The operation of the converter will be explained assuming that the three inductors are working in DCM.Operating the SEPIC in DCM offers advantages over continuous-current-mode(CCM)operation,such as a near-unity power factor can be achieved naturally and without sensing the input line current[26].Also,in DCM,both Q1and Q2are turned on at zero current,while diodes D o1and D o2are turned off at zero current.Thus,the loss due to the switching losses and the reverse recovery of the recti?er are considerably reduced.
The theoretical analysis of the proposed recti?er is performed during one switching period in a positive half-period of the input voltage[Fig.2(b)].Similar to the conventional SEPIC and Cuk converters,the DCM for the proposed recti?er occurs when the current through diode D o1drops to zero before the end of the switch-off time.Thus,the circuit operation in one switching cycle,T s,can be divided into three stages,as shown in Fig.3.To simplify the analysis,it is assumed that the recti?er of Fig.2(a)
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Fig.3.Topological stages for the proposed recti?er during switching cycle T s.(a)Switch-on topology.(b)Switch-off topology.(c)DCM topology.
is operating in steady state,and the following assumptions are made during one switching cycle:
1)The input voltage v ac is considered to be an ideal recti?ed
sine wave,i.e.,v ac=V m sin(ωt),where V m is the peak amplitude andωis the line angular frequency.
2)All components are ideal;thus,the ef?ciency is100%.
3)The switching frequency(f s)is much higher than the
ac line frequency(f L),so that the input voltage can be considered constant during one switching period(T s). 4)All the capacitors are big enough such that their switching
voltage ripples are negligible during the switching period T s.Moreover,the capacitor voltages v C1and v C2follow the input voltage v ac,while the output voltage V o is equally divided between C o1and C o2,i.e.,V o1=V o2= V o/2.Note that the assumption of v C1and v C2following v ac can be justi?ed by considering the two loops contain-ing(v ac,L1,C1,L2)and(v ac,L1,C2,L3)[Fig.2(a)].
These two loops are independent of the converter topol-ogy.Since the net change in the inductor current is zero during one switching cycle T s,it follows that the steady-state average voltage across all inductors must be equal to zero during each switching period T s(volt–second balance).Thus,during each T s,the steady-state average
voltage across C1(v c1-avg)and C2(v c2-avg)must equal the input voltage v ac.In a practical SEPIC recti?er,C1 and C2have a small capacitance(0.5–2μF),so that both v c1-avg and v c2-avg track the ac line voltage,i.e., v ac=v c1=v c2.A small high-frequency ripple voltage also appears across C1and C2.
With these assumptions,the main theoretical waveforms of the recti?er in DCM during one switching cycle are shown in Fig.4.The circuit operation during a switching period T s in a positive half-line cycle will be brie?y discussed next.
Stage1[t0,t1],Fig.3(a):When the switch Q1is turned on,Q2is conducting through its antiparallel body diode D q2. Therefore,turning on or off Q2has no effect on the circuit operation.Thus,both of the switches Q1and Q2can be driven by the same control signal,which helps in reducing the cost and complexity of the system.In this stage,the three-inductor currents increase linearly at a rate that is proportional to the input voltage v ac.The rate of increase of the three inductor currents are given by
di Ln
dt
=
v ac
L n
,n=1,2,3.(1)
Referring to Fig.3(a),the switch current is equal to the sum of the three inductors’currents.Thus,the peak switch current I Q1-pk is given by
I Q1,pk=
V m
L e
D1T s(2) where
1
L e
=
1
L1
+
1
L2
+
1
L3
(3)
and D1is the switch duty cycle.This interval ends when Q1is turned off,initiating the next subinterval.
Stage2[t1,t2],Fig.3(b):At the instant t l,switch Q1is turned off,diode D o1is turned on,simultaneously providing a path for the three inductor currents.In this stage,the three inductor currents decrease linearly at a rate that is proportional to the output voltage V o1.The three inductors’currents are given by
di Ln
dt
=
?V o1
L n
,n=1,2,3.(4)
This interval ends when the diode current i Do1reaches the ground level.The normalized length of this interval is given by
D2=
2v ac D1
V o
?D2=2D1
M
sinωt(5)
where M=V o/V m is the voltage conversion ratio.
Stage3[t2,T s],Fig.3(c):In this stage,all the semiconduc-tors are in their OFF state,as shown in Fig.3(c).The three inductors behave as current sources,which keep the currents constant.The capacitors C1and C2are being charged or discharged by the currents i L2and i L3,respectively.In this stage,the voltage across the three inductors is zero.
1150IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS,VOL.56,NO.4,APRIL
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Fig.4.Theoretical waveforms in DCM of the proposed recti?er.
Fig.4shows the blocking voltage of diode D o2during the switching cycle.For D o2to be off during the entire positive ac line cycle,the following condition must be satis?ed:
V o
2
?v ac≥0?M≥2.(6)
Equation(6)shows that the step-down property is lost(com-pared to the conventional SEPIC),which may be considered as a disadvantage in some applications.However,the constraint in(6)can be removed by implementing input–output galvanic isolation.On the other hand,similar to the conventional SEPIC, galvanic isolation can be obtained easily by employing two winding inductors for both L2and L3instead of two sepa-rate ones.
III.A NALYSIS,M ODELING,AND C OMPARISON
A.Voltage Conversion Ratio M
The voltage conversion ratio M=V o/V m in terms of circuit parameters can be found by evaluating the average diode D o1 current I Do1during one line cycle of the ac input voltage,i.e.,
I Do1=
1
T L
T L
ˉi
Do1
dt(7)
where T L is the period of the line voltage.The symbol“ˉ”denotes the average value during one switching cycle T s.From Fig.4,the average output diode current over one switching period is given by
ˉi
Do1
=
1
T s
T s
i Do1(t)dt?ˉi Do1=
D21T s v2ac
L e v o
.(8) Substituting(8)into(7)and evaluating(7)give
I Do1=
V2m
2R e V o
=
V2ac,rms
R e V o
(9)
where R e is the emulated input resistance of the converter and equals
R e=
2L e
D21T s
.(10)
On the other hand,the average output current during one line cycle is simply equal to
I o=
V o
R L
.(11)
Since the integral of the steady-state capacitor C o1current over one line-cycle integration period is zero,the average value of the diode D o1current during one line cycle is equal to the average current through the load R L.Thus,by equating(9)and (11),the desired voltage conversion ratio M is
M=
R L
2R e
=
D1
√
2K e
(12)
where the dimensionless parameter K e is de?ned as
K e=
2L e
R L T s
.(13)
The voltage conversion ratio M in(12)is the same expres-sion obtained for the conventional SEPIC PFC recti?er in DCM [28],except for the de?nition of L e.
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https://www.wendangku.net/doc/1b9305023.html,rge-signal circuit model of the proposed recti?er.
B.Boundaries Between CCM and DCM
Referring to the diode D o1current waveform in Fig.4,the DCM operation mode requires that the sum of the duty cycle and the normalized switch-off time length be less than one,i.e.,
D2<1?D1.(14) Substituting(5)into(14)and using(12),the following condi-tion for DCM is obtained:
K e 1 2(M+2)2 .(15) For values of K e>K e-crit,the converter operates in CCM; otherwise,the converter operates in DCM. C.Input Line Current Assuming that the ef?ciency is close to unity,the averaged input current over one switching period can be obtained from the instantaneous power balancing between the input and output ports of the recti?er;thus, v ac·ˉi L1=v o1·ˉi Do1=v o×ˉi Do1 2 (16) whereˉi L1represents the input inductor current averaged during one switching cycle.Substituting(8)into(16),we obtain ˉi L1= v ac R e .(17) Similar to the conventional SEPIC PFC recti?er,(17)shows that the input port of the proposed recti?er obeys Ohm’s law so that the input current is sinusoidal and in phase with the input voltage.At this point,a large signal circuit model can be developed by using(16)and(17),as shown in Fig.5.This model can greatly reduce the long computation time when it is implemented in simulation software to predict the steady-state and large-signal dynamic characteristics of the real circuit. D.Semiconductor Stresses The semiconductors’voltage and current stresses for the proposed and the conventional SEPIC topology are listed in Table I.Referring to Table I,the ratio between the peak switch (or diode)voltages for the two topologies is given by V(Q-pk) BL V(Q-pk) Conv.= M+2 2(M+1) (18) TABLE I C OMPARISON B ETWEEN THE C ONVENTIONAL PFC SEPIC AN D THE P ROPOSED B RIDGELESS SEPIC T OPOLOGY IN DCM where the subscripts“BL”and“Conv.”refer to bridgeless and conventional,respectively.Moreover,Table I shows that the semiconductors’current stresses are expressed in terms of M and K e.However,the value of K e-crit for the proposed topol- ogy is always less than the one obtained by the conventional SEPIC[28],provided that both topologies are operating at the same voltage conversion ratio M.The expression of K e-crit for the conventional SEPIC is given by K(e-crit) Conv. = 1 2(M+1)2 .(19) Therefore,to ensure a fair comparison between the two topologies,the semiconductors’current stresses need to be compared for the same ratio value of K e/K e-crit.When both converters are operating at the same ratio of K e/K e-crit,then the ratio between the switch and diode rms currents for the proposed topology and the conventional SEPIC becomes I(Q-rms) BL I(Q-rms) Conv. = I(Do-rms) BL I(Do-rms) Conv. = M+2 M+1 .(20) Similarly,the ratio between the peak switch(or diode)cur- rents for the two topologies becomes I(Q-pk) BL I(Q-pk) Conv. = M+2 M+1 .(21) The graphical representation of(18),(20),and(21)is shown in Fig.6,where the?gure shows that the switch and diode in the bridgeless SEPIC topology are subjected to lower voltage stress compared to the conventional SEPIC PFC recti?er.Whereas, the switch and diode current stresses in the proposed topology are slightly higher than their counterparts in the conventional SEPIC.This increase,however,is compensated by fewer semi- conductor components needed in the bridgeless topology.Also, 1152IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS,VOL.56,NO.4,APRIL 2009 Fig.6.Switch-and-output-diode voltage and current stress ratio between the proposed bridgeless and conventional SEPIC recti?ers as a function of M. the increase in the semiconductor current stress becomes less pronounced as M increases. E.Input Current and Output Voltage Ripples The peak-to-peak input inductor current ripple in both the conventional SEPIC and proposed converters is proportional to the operating duty cycle.When both converters are operating at the same ratio of K e/K e-crit,then the ratio between the input current ripples is given by Δi L1,BL Δi L1,Conv.= L1,Conv. L1,BL ×1+M 2+M .(22) From(22),it is clear that if both recti?ers are designed to have the same input current ripple,then the amount of input inductance required by the bridgeless SEPIC is always less than that of the conventional SEPIC.The low-frequency peak–peak output voltage ripple is given by Δv o= 1 C o 3T L/8 T L/8 [ˉi Do1?I o]dt =T L V o 2C o 1 R e M2 1 π + 1 2 ?1 R L (23) where C o1=C o2=C o.The output voltage ripple in the proposed topology is twice that of the conventional SEPIC. However,connecting an additional capacitor across the load terminals with a capacitance of(C L=C o/2)produces the same output voltage ripple as that of the conventional SEPIC. IV.D ESIGN P ROCEDURE AND S IMULATION A simpli?ed design procedure is presented in this section to determine the component values of the proposed recti?er. Suppose that we want to design the PFC recti?er with the following power stage speci?cations: 1)input voltage v ac=120V rms at50Hz; 2)output voltage V o=400V dc; 3)output power P out=200W; 4)switching frequency f s=50kHz; 5)maximum input current rippleΔi L1=20%of funda- mental current; 6)output voltage rippleΔv o=±1%of V o. From the aforementioned data,and assuming that the ef?ciency is100%,the values of the circuit components are calculated as follows. 1)The voltage conversion ratio M is M= 400 √ 2120 =2.36.(24) 2)The value of K e-crit can now be evaluated from(15)as K e-crit=26.34×10?3.(25) To ensure DCM operation,the following value of K e is selected: K e=0.85×K e-crit=22.4×10?3.(26) Thus,evaluating(13)gives an equivalent inductance L e value of L e= K e R L 2f s =179.1μH.(27) 3)From(12),the required switch duty ratio D1is found as D1= 2K e×M=0.5.(28) 4)From the given speci?cations,the required input current ripple is Δi L1=20%× V m R e =0.47A(29) where R e is evaluated from(10)by R e= 2L e D21T s =72Ω.(30) To achieve this requirement,the input inductance value L1must be L1= V m D1 f sΔi L1 =3.6mH.(31) If we choose the value of L2to be equal to the value of L3,then L2=L3= 2L1L e L1?L e =377μH.(32) 5)The required output capacitance to maintain peak–peak output voltage ripple of2%of V o can be calculated from (23)as C o1=C o2=400μF.(33) 6)The coupling capacitor C1is an important element in the SEPIC topology since its value greatly in?uences the quality of input line current.The capacitor C1must be chosen such that its voltage follows the shape of the input ac line voltage waveform with the lowest voltage ripple as possible.Also,C1should not cause low-frequency ISMAIL:BRIDGELESS SEPIC RECTIFIER WITH UNITY POWER FACTOR AND REDUCED CONDUCTION LOSSES 1153 Fig.7.Simulated waveforms for the converter of Fig.2(a)in DCM. oscillations with inductors L1,L2,and L3.Based on these constraints,the value of C1=C2=1μF is chosen for this particular design. 7)For design purposes,it is important to have the closed- form expressions for the inductor currents during the DCM stage(i.e.,i x and i y).These expressions are impor-tant for evaluating the rms currents in the three inductors and the coupling capacitors C1and C2.Referring to Fig.4,the average currents in L1and C1during one switching cycle can be expressed as ˉi L1= D21T s v ac 2L1 1+ 2v ac V o +i x(34) ˉi C1= D21T s v ac 2 2v ac V o 1 L e ?1 L2 ?1 L2 ?i y(35) respectively.The current i x can be simply found by equating(34)and(17)which gives i x= v ac R e 1? L e L1 1+ 2v ac V o .(36) On the other hand,since the average capacitor C1voltage during one switching cycle is equal to the input voltage,it follows that the low-frequency component(average value over one switching period)of i C1can be represented by ˉi C1 =C1ωV m cos(ωt).(37) Hence,i y can found by equating(35)and(37). To verify the aforementioned design values,the proposed cir- cuit of Fig.2(a)is simulated by using PSpice circuit simulator. 1154IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS,VOL.56,NO.4,APRIL 2009 Fig.8.Simulated line current for the converter of Fig.2(a)in DCM under distorted input voltage. TABLE II P ERFORMANCE C OMPARISON OF THE R ECTIFIERS Fig.9.Bridgeless SEPIC recti?er with coupled inductors. For the simulation,all switching devices and components are assumed ideal with no losses.Fig.7(a)shows that the input line current follows the input line voltage.The percentage of the THD in the input line current is 0.03%.The waveforms of the three inductors’currents at peak input voltage are shown in Fig.7(b)for several switching periods.Fig.7(c)shows that the peak–peak output voltage ripple is 8V with an average dc value close to 400V .Fig.7(d)shows the intermediate capacitor voltage V C 1and the inverted input line voltage v ac for a complete ac cycle.It is clear from Fig.7(d)that V C 1follows the input voltage v ac .Fig.7(e)shows the switch Q 1as well as the output diodes (D o 1and D o 2)currents over a complete ac cycle.The simulated results con?rm the operating principles of the proposed bridgeless PFC SEPIC recti?er. The simulated results in Fig.7are obtained when the input voltage is a pure sinusoid.However,(17)predicts that the proposed recti?er operates as a voltage follower,meaning that the input current naturally follows the input voltage pro?le. Fig.10.Simulated waveforms for the converter of Fig.9. TABLE III E XPERIMENTAL C ONVERTER P ARAMETERS To demonstrate this behavior,the circuit of Fig.2(a)has been simulated with a distorted input voltage.In this case,the input voltage contains third,?fth,and seventh harmonic components,with their magnitude being equal to 2.5%of the fundamental component,V m .Thus,the THD in the input voltage is 4.33%.Fig.8shows the simulated input current waveform under a dis-torted input voltage condition.It is evident from Fig.8that volt-age distortions are re?ected almost perfectly in the input line current.In other words,the single harmonic distortion in the input voltage is almost identical to the single harmonic distor-tion in the input line current.However,this does not mean any practical restriction if the PFC circuit is targeted to meet the IEC 61000-3-2limits,since the compliance with harmonic limits is always checked with an ideal sinusoidal line voltage waveform.The performance of the proposed recti?er is compared with the conventional SEPIC recti?er through PSpice simulation. ISMAIL:BRIDGELESS SEPIC RECTIFIER WITH UNITY POWER FACTOR AND REDUCED CONDUCTION LOSSES 1155 Fig.11.Experimental waveforms for the converter of Fig.2. The recti?ers were simulated for the following input and output data speci?cations:v ac=120V rms,V o=400V dc,P out= 200W,and f s=50kHz.To ensure a fair comparison,the inductance values in each topology are selected such that K= 0.9K crit.Moreover,an equivalent series resistor of50and 100mΩis placed in series with all the inductors and capac-itors,respectively.Furthermore,actual PSpice semiconductor models have been used to simulate the switches:STY60NM60 (600V,60A,R DS-ON=50mΩ)for the active switch and MUR460ultrafast recti?er(600V,4A,V F=1.05V at 3A)for the diode.Table II shows the simulation results.It is evident from Table II that the proposed recti?er leads to an improvement of1.5%in the conversion ef?ciency compared to the conventional SEPIC recti?er.Note that although the switch and diodes in the proposed scheme are subjected to a higher current stress than the conventional SEPIC,it has a better con-version ef?ciency.This is because,during each switching cycle, there are fewer numbers of semiconductors in the?owing-current path. V.B RIDGELESS SEPIC R ECTIFIER W ITH C OUPLE D I NDUCTORS In the proposed circuit of Fig.2(a),the three inductors have identical voltage waveforms;hence,they can be magnetically coupled into a single magnetic core,as shown in Fig.9.Note that Fig.9shows that the inductors L1and L2are magnetically coupled together by a mutual inductance M12,whereas L1and L3are magnetically coupled together by a mutual inductance M13.There is no magnetic coupling between L2and L3.In this case,a standard EI magnetic core can be used for the practical implementation of the magnetic circuit[31]. 1156IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS,VOL.56,NO.4,APRIL 2009 The topological stages for the coupled inductor circuit of Fig.9are similar to the three topological stages for the uncou-pled case (Fig.3).Referring to Fig.9,k 12and k 13represent the coupling coef?cient between L 1–L 2and L 1–L 3,respectively.By proper coupling between the three windings,it is possible to obtain an input current having very low high-frequency content (near-zero current ripples).This can be demonstrated by writing the characteristic equations of the coupled inductors L 1,L 2,and L 3during switch-on time which is given by d dt ??i L 1i L 2i L 3??=1Δ??L 2L 3?M 12L 3?L 2M 13?M 12L 3L 1L 3?M 213M 12M 13?L 2M 13M 12M 13L 1L 2?M 2 12????v ac v C 1v C 2 ??(38)where Δ=L 1L 2L 3?L 2M 213?L 3M 2 12>0 (39)M 12=k 12 L 1L 2, (0 L 1L 3,(0 (41) Note that (39)must be positive since the total inductance matrix is symmetric positive de?nite,i.e.,it has a positive determinant.At steady state,v C 1=v C 2=v ac ,and then from (38),the following condition must be satis?ed for zero current ripples in the input current: di L1 dt =0?L 2L 3?L 3M 12?L 2M 13=0.(42) During switch-off time,one can show that the condition for zero current ripples in the input current is similar to (42). It should be mentioned here that the steady-state analysis presented in Sections II and III for the uncoupled inductors is also valid for the coupled-inductor extension,except for the de?nition of the effective inductance L e (3).This is because only the inductors L 2and L 3determine the switching current ripple.Thus,for the coupled-inductor case,the de?nition of L e becomes L e = L 2L 3 L 2+L 3 . (43) In the proposed topology,it is preferred that inductors L 2and L 3have equal values so that they carry the same ripple current.In this case,the condition in (39)and (42)reduces to k 212+k 213<1 (44) M 12+M 13=L 2?k 12+k 13= L 2 L 1 (45) respectively.To demonstrate the effect of coupling the inductors on the input current,the circuit of Fig.9has been simulated using PSpice for the same power stage speci?cations and under the same operating condition (i.e.,for the same value of K e )and with the same capacitor values mentioned in Section IV.The parameters of the coupled inductors used are L 1=900μH,L 2=L 3=358.2μH,and k 12=k 13=0.315. The simulated input voltage and input current waveforms are shown in Fig.10(a),while the waveforms of the three induc-tor currents at a peak input voltage during several switching Fig.12.Experimental waveforms for the converter of Fig.2during a few switching periods. periods are shown in Fig.10(b).It is evident from Fig.10that the high-frequency switching ripple current is signi?cantly suppressed due to the coupling of the three inductors.Thus,the generated EMI noise level is greatly minimized,as well as the requirement for input ?ltering. VI.E XPERIMENTAL R ESULTS A laboratory prototype,whose parameters are listed in Table III,has been constructed to evaluate the performance of the proposed scheme of Fig.2.In addition,a 68-μF capacitor is connected across the load to improve the ripple percentage.It should be mentioned here that the experimental circuit is not optimized for maximum ef?ciency since the choice of the parameters is based on the availability of off-the-shelf compo-nents.The experimental waveforms of the converter at full load are shown in Figs.11and 12.The input voltage and input line current (i L 1)waveforms are shown in Fig.11(a).The input line current waveform is obtained without utilizing an input ?lter and results in a measured THD of about 2.5%.Fig.11(b)shows the voltages across the output capacitors C o 1and C o 2and the load.It is evident that the output voltage is almost evenly split between C o 1and C o 2.The measured output voltage is 198.2V with a 5.7-V peak–peak voltage ripple.The low-frequency current envelope of the active switch i Q 1and the output diode i Do1are shown in Fig.11(c)and (d),respectively.Note that the peak switch and diode current ful?ll the theoretical predicted results shown in Table I.Fig.11(e)shows the input voltage and the voltage across the capacitor C 1.It can be observed from ISMAIL:BRIDGELESS SEPIC RECTIFIER WITH UNITY POWER FACTOR AND REDUCED CONDUCTION LOSSES1157 Fig.11(e)that the capacitor voltage v C1closely tracks the input voltage v ac.On the other hand,Fig.12shows the experimental waveforms over a few switching periods.The switch-gating signals(V GS)and the discontinuous inductor currents(i L1, i L2,and i L3)are shown in Fig.12(a),whereas the blocking voltages of the switch Q1and diodes D o1and D o2are shown in Fig.12(b).The experimental results are in good agreement with the theoretical predictions.Finally,the measured full-load ef?ciency is about91.8%,which can be further improved by utilizing better components and improving the PCB layout. VII.C ONCLUSION In this paper,a simple single-phase bridgeless SEPIC recti-?er with low input current distortion and low conduction losses has been proposed and veri?ed https://www.wendangku.net/doc/1b9305023.html,parisons are made between the proposed topology and the conventional SEPIC.The main features of the proposed converters include high ef?ciency,low voltage stress on the semiconductor de-vices,and simplicity of design.These advantages are desirable features for high-power and high-voltage applications.The proposed bridgeless PFC con?guration,as described in this paper,has been implemented to verify the performance of the system.The measured THD was2.5%with power conversion ef?ciency close to92%.Finally,the proposed concept can be extended easily to other power conversion systems to satisfy the requirement of high-voltage demands. R EFERENCES [1]C.Qiao and K.M.Smedley,“A topology survey of single-stage power factor corrector with a boost type input-current-shaper,”IEEE Trans. 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[25]L.Huber,Y.Jang,and M.M.Jovanovic,“Performance evaluation of bridgeless PFC boost recti?ers,”in Proc.IEEE Appl.Power Electron. Conf.,Feb.2007,pp.165–171. [26]J.Sebastian,J.Uceda,J.A.Cobos,J.Arau,and F.Aldana,“Improving power factor correction in distributed power supply systems using PWM and ZCS-QR SEPIC topologies,”in Proc.IEEE Power Electron.Spec. Conf.,1991,pp.780–791. [27]M.Brkovic and S.Cuk,“Input current shaper using Cuk converter,”in Proc.Int.Telecommun.Energy Conf.,1992,pp.532–539. [28]D.S.L.Simonetti,J.Sebastian,and J.Uceda,“The discontinuous conduction mode Sepic and Cuk power factor preregulators:Analysis and design,”IEEE Trans.Ind.Electron.,vol.44,no.5,pp.630–637, Oct.1997. [29]G.Spiazzi and L.Rosseto,“High-quality recti?er based on coupled- inductor Sepic topology,”in Proc.IEEE Appl.Power Electron.Conf., 1994,pp.336–341. [30]F.S.Dos Reis,J.Sebastian,and J.Uceda,“Characterization of conducted noise generation for Sepic,Cuk and Boost converters working as power factor preregulators,”in Proc.IEEE IECON,pp.965–970. [31]S.Cuk,“A new zero-ripple switching DC-to-DC converter and inte- grated magnetics,”IEEE Trans.Magn.,vol.MAG-19,no.2,pp.57–75, Mar. 1983. Esam H.Ismail(M’93–SM’07)received the B.S. (magna cum laude)and M.S.degrees in electrical engineering from the University of Dayton,Dayton, OH,in1983and1985,respectively,and the Ph.D. degree in electrical engineering from the University of Colorado,Boulder,in1993. From1985–1988,he was a Lecturer with the College of Technological Studies,Al-Shaab,Kuwait, where he is currently an Associate Professor with the Department of Electrical Engineering.His research interests include single-and three-phase low-harmonic recti?cation,high-frequency power conversion,soft-switching techniques,and the development of new converter topologies. Dr.Ismail was an Assistant Deputy Director General for Applied Education and Research with the Public Authority for Applied Education and Training from2000to2005.He is a member of Tau Beta Pi. 数据结构课程设计 设计说明书 进制转换的实现 学生JUGG 学号￥#·· 班级Dota all star——成绩优秀 指导教师Puck dota科学与技术 天灾元年 3 月 14 日 Dota all star 课程设计任务书 天灾元年—近卫戊年第二学期 专业：ganker 学号：sadofaiofo ： 课程设计名称：数据结构课程设计 设计题目：进制转换的实现 完成期限：自天灾元年年 3 月 1 日至近卫戊年年 3 月14 日共 2 周 设计依据、要求及主要容（可另加附页）： 进制数制是人们利用符号进行计数的科学方法。数制有很多种，在计算机中常用的数制有：十进 制，二进制、八进制和十六进制。十六进制数有两个基本特点:它由十六个字符0～9以及A，B，C，D， E，F组成（它们分别表示十进制数0～15），十六进制数运算规律是逢十六进一，例如：十六进制数4AC8 可写成（4AC8）16，或写成4AC8H。 要求： （1）输入一个十进制数N，将它转换成R进制数输出，并可以进行逆转换。 （2）输入数据包含多个测试实例，每个测试实例包含两个整数N(32位整数)和R（2<=R<=16, R<>10）。 （3）为每个测试实例输出转换后的数，每个输出占一行。如果R大于10，则对应的数字规则参考 16进制（比如，10用A表示，等等）。 （4）界面友好。 指导教师（签字）：教研室主任（签字）： 批准日期：年月日 摘要 由于数制计算和不同数制之间转换的需要，设计了一个10进制转换其它进制(36进制以)及逆转换的软件，该软件具有简单的将10进制数转换成2、8、16进制数以及较复杂的高进制数的转换和逆转功能。本软件采用C语言编写以VC++作为软件开发环境，采用顺序栈存储方式来存储运算中的数位，借助栈后进先出的特点，易于结果输出。操作简单，界面清晰，易于为用户所接受。 关键词：进制转换；顺序栈；逆转换 目录 1、系统方案.......................................... - 3 - 1.1、方案比较与选择............................... - 3 - 1.1.1、单片机选择与论证........................ - 3 - 1.1.2、显示器件选择与论证...................... - 3 - 1.1.3、键盘形式选择与论证...................... - 4 - 1.1.4排阻形式选择与论证........................ - 4 - 2理论分析与计算 ..................................... - 8 - 2.1、D/A转换器的主要技术指标......................... - 8 - 1．分辨率......................................... - 8 - 2．转换精度....................................... - 8 - 3．输出电压（或电流）的建立时间（转换速度） ...... - 8 - 4. 温度系数 2.2 数模转换器 2.2.1权电阻网络DAC的原理分析..................... - 9 - 3、电路与程序设计.................................. - 11 - 3.1.1、总体框图设计........................... - 11 - 3.1.2、显示电路............................... - 11 - 3.1.3、权电路................................. - 12 - 3.1.4、按键电路............................... - 13 - 3.1.5、驱动电路............................... - 14 - 1. 圆柱体转动惯量(齿轮、联轴节、丝杠、轴的转动惯量) 8 2 MD J = 对于钢材：341032-??= g L rD J π ) (1078.0264s cm kgf L D ???- M-圆柱体质量(kg)； D-圆柱体直径(cm)； L-圆柱体长度或厚度(cm)； r-材料比重(gf /cm 3)。 2.丝杠折算到马达轴上的转动惯量： 2i Js J =(kgf· cm·s 2) J s –丝杠转动惯量(kgf·cm·s 2)； i-降速比，1 2 z z i = 3. 工作台折算到丝杠上的转动惯量 g w 22 ? ?? ???=n v J π g w 2s 2 ? ?? ??=π(kgf·cm·s 2) v -工作台移动速度(cm/min)； n-丝杠转速(r/min)； w-工作台重量(kgf)； g-重力加速度，g=980cm/s 2； s-丝杠螺距(cm) 2. 丝杠传动时传动系统折算到驱轴上的总转动惯量： ()) s cm (kgf 2g w 1 22 22 1????? ???????? ??+++=πs J J i J J S t J 1-齿轮z 1及其轴的转动惯量； J 2-齿轮z 2的转动惯量(kgf·cm·s 2)； J s -丝杠转动惯量 (kgf·cm·s 2)； s-丝杠螺距，(cm)； w-工件及工作台重量(kfg). 5. 齿轮齿条传动时折算到小齿轮轴上的转动惯量 2 g w R J = (kgf·cm·s 2) R-齿轮分度圆半径(cm); w-工件及工作台重量(kgf) 6. 齿轮齿条传动时传动系统折算到马达轴上的总转动惯量 ???? ??++=2221g w 1R J i J J t J 1，J 2-分别为Ⅰ轴， Ⅱ轴上齿轮的转动惯量(kgf·cm·s 2)； R-齿轮z 分度圆半径(cm)； w-工件及工作台重量(kgf)。 马达力矩计算 (1) 快速空载时所需力矩： 0f amax M M M M ++= (2) 最大切削负载时所需力矩： t 0f t a M M M M M +++= (3) 快速进给时所需力矩： 0f M M M += 式中M amax —空载启动时折算到马达轴上的加速力矩(kgf·m)； M f —折算到马达轴上的摩擦力矩(kgf·m)； M 0—由于丝杠预紧引起的折算到马达轴上的附加摩擦力矩(kgf·m)； M at —切削时折算到马达轴上的加速力矩(kgf·m)； M t —折算到马达轴上的切削负载力矩(kgf·m)。 在采用滚动丝杠螺母传动时，M a 、M f 、M 0、M t 的计算公式如下： (4) 加速力矩： 2a 106.9M -?= T n J r (kgf·m) s T 17 1= J r —折算到马达轴上的总惯量； T —系统时间常数(s)； n —马达转速(r/min)； 当n=n max 时，计算M amax n=n t 时，计算M at n t —切削时的转速(r/min) 数学快速计算法 二位数乘法速算总汇 1、两位数的十位相同的,而个位的两数则是相补的(相加等于10)女口:78 X 72= 37 X 33= 56 X 54= 43 X 47 = 28 X 22 46 X 44 (1) 分别取两个数的第一位,而后一个的要加上一以后,相乘。 (2) 两个数的尾数相乘,(不满十,十位添作0) 78X 72=5616 37 X 33=1221 56 X 54= 3024 43 X 47= 2021 (7+1) X 7=56 (3+1) X 3=12 (5+1) X 5=30 (4+1) X 4=20 8X 2=16 7 X 3=21 6 X 4=24 3 X 7=21 口决:头加1,头乘头,尾乘尾 2、两个数的个位相同,十位的两数则是相补的 如:36 X 76= 43 X 63= 53 X 53= 28 X 88= 79 X 39 (1) 将两个数的首位相乘再加上未位数 (2) 两个数的尾数相乘(不满十,十位添作0) 36X 76=2736 43 X 63=2709 3X 7+6=27 4 X 6+3=27 6X 6=36 3 X 3=9 口决:头乘头加尾,尾乘尾 3、两位数的十位差1,个位的两数则是相补的。 如:48 X 52 12 X 28 39 X 11 48 X 32 96 X 84 75 X 65 即用较大的因数的十位数的平方,减去它的个位数的平方。 48 X 52=2496 12 X 28 = 336 39 X 11= 819 48 X 32=1536 2500-4=2496 400-64=336 900-81=819 1600-64=1536 口决:大数头平方 —尾平方 4、一个乘数十位加个位是 9,另一个乘数十位和个位是顺数 X 78 = 81 X 23 = 27 X 89 = 5 23 2 如:12 X 13= 13 X 15= 14 X 15= 16 X 18= 17 X 19= 19 X 18= (1) 尾数相乘 ,写在个位上 (满十进位 ) (2) 被乘数加上乘数的尾数 12X 13=156 13 X 15= 195 14 X 15=210 16 X 18= 288 2X 3=6 3 X 5=154X 5=20 6 X 8=48 12+3=15 13+5=18 14+5=19 16+8=24 口决:尾数相乘 ,被乘数加上乘数的尾数 （满十进位 ） 6、任何二位数数乘于 11 如 :36 X 45 = 72 X 67 = 45 1 、解 : 3+1=4 4 X 4 = 1的6补5 数是 4X 5=20所以 36 X 45= 1620 2、解: 7+1=8 8 X 6 = 4的8补7 数是 8X 3=24所以 72 X 67 = 4824 3、解: 4+1=5 5 X 7=3的5补8 数是 5X 2=10所以 45 X 78 = 3510 5、10-20 的两位数乘法 一、实验目的 （1）进一步熟练掌握8086汇编语言编译调试工具和环境的操作； （2）掌握完整8086汇编的程序设计编写方法； （3）掌握简单的数值码制转换方法； （4）掌握键盘输出的DOS功能调用方法。 二、实验要求： 将AX中的一个二进制数（对应的十进制数范围是0-65535），转换成压缩性BCD 码表示的十进制，并从屏幕输出转换结果。要求用减法实现，并比较与除法方法进行运行速度比较。 三、实验及报告要求： 3.1、简要说明算法，并画出正确的程序流程图； 3.2、给出完整正确的源程序代码，要求给每一句伪指令或指令加上注释； 3.3、分别在ＤＯＳ和Windows下编译、连接源程序生成可执行文件并调试，比较两个环境下生成的机器码的长度、寄存器内容、计算结果的异同。 3.4、如何观察转换过程中标志寄存器中各标志位的结果？如何观察转换结果的变化？试改变被转换数值，对结果与编制为的变化加以说明和解释。 3.5、写出完整的实验报告，特别是“实验结果”与“实验总结体会”部分，是评分的主要依据。 3.6、实验总结中要求结合实验中的经验、教训或体会对汇编语言格式、调试方法和微机原理学习方法作出总结。 四、程序流程图 减法。即五位数先循环减10000，直到不够减了，做减法的次数就是万分位的结果；将不够减之前一次的余数恢复，再循环减去1000，直到不够减了，做减法的次数就是千分位的结果；以此类推，最后恢复的正余数就是个位的结果. 除法。即五位数先除以10000，得到的商存放万位数的变量上；再将余数除以1000，得到的商存放千位数的变量上；之后将余数除以100，得到的商存放百分位的变量上；以此类推，最后的余数存放在个位的变量上。 第11章 数模与模数转换器 习题与参考答案 【题11-1】 反相运算放大器如图题11-1所示，其输入电压为10mV ，试计算其输出电压V O 。 图题11-1 解：输出电压为： mV mV V R R V IN F O 10010101 =?=-= 【题11-2】 同相运算放大器如图题11-2所示，其输入电压为10 mV ，试计算其输出电压V O 。 图题11-2 解：mV mV V R R V IN F O 110101111 =?=+=）（ 【题11-3】 图题11-3所示的是权电阻D/A 转换器与其输入数字信号列表，若数字1代表5V ，数字0代表0V ，试计算D/A 转换器输出电压V O 。 11-3 【题11-4】 试计算图题11-4所示电路的输出电压V O 。 图题11-4 解：由图可知，D 3~D 0=0101 因此输出电压为：V V V V O 5625.151650101254 === ）（ 【题11-5】 8位输出电压型R/2R 电阻网络D/A 转换器的参考电压为5V ，若数字输入为，该转换器输出电压V O 是多少？ 解：V V V V O 988.21532565100110012 58≈== ）（ 【题11-6】 试计算图题11-6所示电路的输出电压V O 。 图题11-6 解：V V V D D V V n n REF O 5625.1516501012 5~240==-=-=）（）（ 【题11-7】 试分析图题11-7所示电路的工作原理。若是输入电压V IN =，D 3～D 0是多少？ 图题11-7 解：D3=1时，V V V O 6221234== ，D3=0时，V O =0。 D2=1时，V V V O 3221224== ，D2=0时，V O =0。 D1=1时，V V V O 5.1221214== ，D1=0时，V O =0。 D0=1时，V V V O 75.0221204 ==，D0=0时，V O =0 由此可知：输入电压为，D3~D0=1101，这时V O =6V++=，大于输入电压V IN =，比较器输出低电平，使与非门74LS00封锁时钟脉冲CLK ，74LS293停止计数。 【题11-8】 满度电压为5V 的8位D/A 转换器，其台阶电压是多少？分辨率是多少？ 解：台阶电压为mV mV V STEP 5.192/50008== 分辨率为：%39.00039.05000/5.195000/===mV V STEP Cems环保数据折算公式 流速 Vs = Kv * Vp 其中 Vs 为折算流速 Kv为速度场系数 Vp 为测量流速 粉尘 1 粉尘干基值 DustG = Dust / ( 1 – Xsw / 100 ) 其中 DustG 为粉尘干基值 Dust 为实测的粉尘浓度值 Xsw 为湿度 2 粉尘折算 DustZ = DustG * Coef 其中 DustZ 为折算的粉尘浓度值 DustG 为粉尘干基值 Coef 为折算系数，它的计算方式如下: Coef = 21 / ( 21 - O2 ) / Alphas 其中 O2 为实测的氧气体积百分比。 Alphas 为过量空气系数(燃煤锅炉小于等于折算系数为; 燃煤锅炉大于折算系数为; 燃气、燃油锅炉折算系数为 3粉尘排放率 DustP = DustG * Qs / 1000000 其中 DustP 为粉尘排放率 Dust 为粉尘干基值 Qs 为湿烟气流量，它的计算方式如下： Qs = 3600 * F * Vs 其中 Qs 为湿烟气流量 F 为测量断面面积 Vs 为折算流速 SO2 1 SO2干基值 SO2G = SO2 / ( 1 – Xsw / 100 ) 其中 SO2 为实测SO2浓度值 Xsw 为湿度 2 SO2折算 SO2Z = SO2G * Coef 其中 SO2Z 为 SO2折算率 SO2G 为SO2干基值 Coef 为折算系数，具体见粉尘折算 3 SO2排放率 SO2P = SO2G * Qsn / 1000000 其中 SO2P 为SO2排放率 SO2G 为SO2干基值 Qsn 为干烟气流量，它的计算方式如下： Qsn = Qs * 273 / ( 273 + Ts ) * ( Ba + Ps ) / 101325 * ( 1 – Xsw / 100 )其中 Qs 为湿烟气流量 Ts 为实测温度 Ba 为大气压力 Ps 为烟气压力 Xsw 为湿度 NO 1 NO干基值 NOG = NO / ( 1 – Xsw / 100 ) 其中 NOG 为NO干基值 NO 为实测NO浓度值 Xsw 为湿度 2 NO折算 NOZ = NOG * Coef 其中 NOZ 为 NO折算率 NOG 为NO干基值 Coef 为折算系数，具体见粉尘折算 3 NO排放率 NOP = NOG * Qsn / 1000000 其中 NOP 为NO排放率 数据结构课程设计报告 实验一：计算器 设计要求 1、问题描述：设计一个计算器，可以实现计算器的简单运算，输出并检验结果的正确性，以及检验运算表达式的正确性。 2、输入：不含变量的数学表达式的中缀形式，可以接受的操作符包括+、-、*、/、%、(、)。 具体事例如下： 3、输出：如果表达式正确，则输出表达式的正确结果；如果表达式非法，则输出错误信息。 具体事例如下： 知识点：堆栈、队列 实际输入输出情况： 正确的表达式 对负数的处理 表达式括号不匹配 表达式出现非法字符 表达式中操作符位置错误 求余操作符左右出现非整数 其他输入错误 数据结构与算法描述 解决问题的整体思路： 将用户输入的中缀表达式转换成后缀表达式，再利用转换后的后缀表达式进行计算得出结果。 解决本问题所需要的数据结构与算法： 用到的数据结构是堆栈。主要算法描述如下： A．将中缀表达式转换为后缀表达式： 1. 将中缀表达式从头逐个字符扫描，在此过程中，遇到的字符有以下几种情况： 1）数字 2）小数点 3）合法操作符+ - * / % 4）左括号 5）右括号 6）非法字符 2. 首先为操作符初始化一个map 《数据结构》 课程设计报告书 题目：数制转换 系别：计算机科学与应用系学号： 学生姓名： 指导教师： 完成日期：2013—6—1 数制转换 1.需求分析 任意给定一个M进制的数x ，实现如下要求 1)求出此数x的10进制值（用MD表示） 2)实现对x向任意的一个非M进制的数的转换。 3)至少用两种或两种以上的方法实现上述要求（用栈解决，用数组解决，其它方法解决）。 2.概要设计 程序流程可以用以下流程图来刻画： A用数组实现 B用栈实现 3.详细设计 A．用数组实现该问题 D2M()函数和M2D()函数是实现该问题的主要函数。D2M()函数是实现十进制转换为其他进制的函数，它是将输入的十进制数x首先对需要转换的进制M取余，然后在对其取整，接着通过递归调用D2M()函数一次将得到的整数部分一次先取余后取整，并将所得的余数依次存入下一数组，然后逆向去除数组中的元素，即得到转换后的结果。而M2D()函数是实现其他进制M转换为十进制，并将其转换为非M进制。M进制转十进制则是从该M 进制数的 最后一位开始运算，依次列为第0、1、2、……..N位并分别乘以M的0、1、2、…..N次方，将得到的次方相加便得到对应的十进制数，再调用D2M()函数将其转换为非M进制的数。 B.用栈实现 栈具有后进先出的性质，具体实现方法和数组的方法有很大联系，不再过多解释。 4.调试分析 （1）构造栈的方法通过查阅书籍知道了。 （2）数组的递归调用查阅相关书籍了解了。 （3）为了让界面表达更清晰，多次调试完善了界面。 5.测试结果 下面是我的测试函数及运行结果： A.数组测试结果 《数字逻辑电路分析与设计》课程 项目 实施报告 题目(A)：基本模数转换器（ADC）的设计 组号： 8 任课教师：。。。 组长：。。。。 成员：。。。。 成员：。。。 成员：。。。 成员：。。。 联系方式：。。。 二零一四年十月二十五日 基本模数转换器（ADC ）的设计 一．设计要求 （1） 设计一个每单次按下按钮，就能够实现数模转换的电路，并用LED 显示对应输入模拟电压（0—3V ）的等级，当输入电压>3V 后，有“溢出”显示。 （2） 功能模块如图： （3） 图中的“模数转换”为本教材第六章的并行ADC 转换电路。在此基础上自行设计按键、LED 显示、模拟电压调节等模块，实现单次模数转换的功能。 模拟电压 调节模数转换LED 显示 按键 5V 电源 自行设计溢出标记的显示。 （4） 本电路的测试方法是，通过一个电位器对电源电压连续分压，作为ADC 的输入电压，每按下一次按键时，ADC 电路进行一次ADC 转换，并将转换的结果用数码管显示出来。注意不要求显示实际的电压值，仅显示模拟电压的量化等级。 二．电路原理图 LED 显示 三．设计思路 根据题目要求，我们的电路本应分五个个模块，但实验室缺少8-3编码器不能实现转化，所以只能有四个一下模块：模拟电压调节；比较电路；记忆模块；LED显示。模拟电压的调节可以用划变电阻来调节电压，理想中数模转化模块应由比较器，D触发器和编码器来实现，在我们的实际电路中我们只用了前两者。最终我们用LED的亮灭来显示结果。 具体原理叙述如下： 在比较电压时，将参考电压V ref经电阻分压器产生一组不同的量化电平V i：v1=1/16V ref，v2=3/16V ref，v3=5/16V ref ，v4=7/16V ref ，v5=9/16V ref ，v6=11/16V ref ，v7=13/16V ref ，v8=15/16V ref ，这些量化电平分别送到相应lm339比较器的反相输入端，而输入电压V同时作用于lm339比较器的同相输入端。 当V大于V i时，第i个比较器输出状态1，即高电平；反之，比较器输出状态0，即低电平。比较器的输出加到D触发器的输入端，在时钟脉冲CP的作用下，把比较器的输出存入触发器，得到稳定的状态输出Q，再由LED的亮暗状态显示，高电平则亮，低电平就暗。 当V≥15/16 V ref的时候，即Ｖ超过该转换器的最大允许的输入电压的时候产生“溢出”，我们使用了一个红色的报警LED亮作为显示。 此外，鉴于会因为按键时间的长短不一而造成的脉冲不整齐的问题，需要 折算标准煤的计算方法如下（以电耗为例）： （折算标准煤系数）×（电耗用数）＝（耗用标准煤数量） 对于电耗，折算标准煤系数为0.429 即270万度，折合成标准煤量115.83万公斤，即1158.3吨 各类能源折算标准煤的参考系数 品种折标准煤系数 原煤0.7143千克标准煤／千克 洗精煤0.9000千克标准煤／千克 洗中煤0.2857千克标准煤／千克 煤泥0.2857-0.4286千克标准煤／千克 焦炭0.9714千克标准煤／千克 原油 1.4286千克标准煤／千克 汽油 1.4714千克标准煤／千克 煤油 1.4714千克标准煤／千克 柴油 1.4571千克标准煤／千克 燃料油 1.4286千克标准煤／千克 液化石油气油 1.7143千克标准煤／千克 炼厂干气 1.5714千克标准煤／立方米 油田天然气 1.3300千克标准煤／立方米 气田天然气 1.2143千克标准煤／立方米 煤田天然气(即煤矿瓦斯气) 0.5000-0.5174千克标准煤／立方米 焦炉煤气0.5714-0.6143千克标准煤／立方米 其他煤气 (1)发生炉煤气0.1786千克标准煤／立方米 (2)重油催化裂解煤气0.6571千克标准煤／立方米 (3)重油热裂煤气 1.2143千克标准煤／立方米 (4)焦炭制气0.5571千克标准煤／立方米 (5)压力气化煤气0.5143千克标准煤／立方米 (6)水煤气0.3571千克标准煤／立方米) 电力(等价0.4040千克标准煤／千瓦小时(用于计算最终消费) 电力(当量) 0.1229千克标准煤／千瓦小时(用于计算火力发电) 热力(当量) 0.03412千克标准煤／百万焦耳 (0.14286千克标准煤／1000千卡) 能源折标准煤系数＝某种能源实际热值(千卡/千克)/7000(千卡/千克) 在各种能源折算标准煤之前，首先直测算各种能源的实际平均热值，再折算标准煤。平均热值也称平均发热量.是指不同种类或品种的能源实测发热量的加权平均值。计算公式为：平均热值(千卡／千克)＝[∑(某种能源实测低发热量)×该能源数量]/能源总量(吨) 一.两个20以内数的乘法 两个20以内数相乘,将一数的个位数与另一个数相加乘以10,然后再加两个尾数的积,就是应求的得数。如12×13＝156,计算程序是将12的尾数2,加至13里,13加2等于15,15×10＝150,然后加各个尾数的积得156,就是应求的积数。 二.首同尾互补的乘法 两个十位数相乘,首尾数相同,而尾十互补,其计算方法是:头加1,然后头乘为前积,尾乘尾为后积,两积连接起来,就是应求的得数。如26×24＝624。计算程序是:被乘数26的头加1等于3,然后头乘头,就是3×2＝6,尾乘尾6×4＝24,相连为624。 三.乘数加倍,加半或减半的乘法 在首同尾互补的计算上,可以引深一步就是乘数可加倍,加半倍,也可减半计算,但是:加倍、加半或减半都不能有进位数或出现小数,如48×42是规定的算法,然而,可以将乘数42加倍位84,也可以减半位21,也可加半倍位63,都可以按规定方法计算。48×21＝1008,48×63＝3024，48×84=4032。有进位数的不能算。如87×83＝7221,将83加倍166,或减半41.5,这都不能按规定的方法计算。 四.首尾互补与首尾相同的乘法 一个数首尾互补,而另一个数首尾相同,其计算方法是:头加1,然后头乘头为前积,尾乘尾为后积,两积相连为乘积。如37×33＝1221,计算程序是(3＋1)×3×100＋7×3＝1221。 五.两个头互补尾相同的乘法 两个十位数互补,两个尾数相同,其计算方法是:头乘头后加尾数为前积,尾自乘为后积。如48×68＝3264。计算程序是4×6＝24 24＋8＝32 32为前积,8×8＝64为后积,两积相连就得3264。 六.首同尾非互补的乘法 两个十位数相乘,首位数相同,而两个尾数非互补,计算方法:头加1,头乘头,尾乘尾,把两个积连接起来。再看尾和尾的和比10大几还是小几,大几就加几个首位数,小几就减掉几个首位数。加减的位置是:一位在十位加减,两位在百位加减。如36×35＝1260,计算时(3＋1)×3＝12 6×5＝30 相连为1230 6＋5＝11,比10大1,就加一个首位3,一位在十位加，1230＋30＝1260 36×35就得1260。再如36×32＝1152,程序是(3＋1)×3＝12,6×2＝12,12与12相连为1212,6＋2＝8,比10小2减两个3,3×2＝6,一位在十位减,1212－60就得1152。 七.一数相同一数非互补的乘法 两位数相乘,一数的和非互补,另一数相同,方法是:头加1,头乘头,尾乘尾,将两积连接起来后,再看被乘数横加之和比10大几就加几个乘数首。比10小几就减几个乘数首,加减位置:一位数十位加减,两位数百位加减,如65×77＝5005,计算程序是(6＋1)×7＝49，5×7＝35,相连为4935,6＋5＝11,比10大1,加一个7,一位数十位加。4935＋70＝5005 八.两头非互补两尾相同的乘法 两个头非互补,两个尾相同,其计算方法是:头乘头加尾数,尾自乘。两积连接起来后,再看两个头的和比10大几或小几,比10大几就加几个尾数,小几就减几个尾数,加减位置:一位数十位加减,两位数百位加减。如67×87＝5829,计算程序是:6×8＋7＝55,7×7＝49,相连为5549,6＋8＝14,比10大4,就加四个7,4×7＝28,两位数百位加,5549＋280＝5829 单片机十进制加法计算器设计 摘要 本设计是基于51系列的单片机进行的十进制计算器系统设计，可以完成计 算器的键盘输入，进行加、减、乘、除3位无符号数字的简单四则运算，并在LED上相应的显示结果。 设计过程在硬件与软件方面进行同步设计。硬件方面从功能考虑，首先选择内部存储资源丰富的AT89C51单片机，输入采用4×4矩阵键盘。显示采用3位7段共阴极LED动态显示。软件方面从分析计算器功能、流程图设计，再到程序的编写进行系统设计。编程语言方面从程序总体设计以及高效性和功能性对C 语言和汇编语言进行比较分析，针对计算器四则运算算法特别是乘法和除法运算的实现，最终选用全球编译效率最高的KEIL公司的μVision3软件，采用汇编语言进行编程，并用proteus仿真。 引言 十进制加法计算器的原理与设计是单片机课程设计课题中的一个。在完成理论学习和必要的实验后，我们掌握了单片机的基本原理以及编程和各种基本功能的应用，但对单片机的硬件实际应用设计和单片机完整的用户程序设计还不清楚，实际动手能力不够，因此对该课程进行一次课程设计是有必要的。 单片机课程设计既要让学生巩固课本学到的理论，还要让学生学习单片机硬件电路设计和用户程序设计，使所学的知识更深一层的理解，十进制加法计算器原理与硬软件的课程设计主要是通过学生独立设计方案并自己动手用计算机电路设计软件，编写和调试，最后仿真用户程序，来加深对单片机的认识，充分发挥学生的个人创新能力，并提高学生对单片机的兴趣，同时学习查阅资料、参考资料的方法。 关键词：单片机、计算器、AT89C51芯片、汇编语言、数码管、加减乘除 目录 摘要 (01) 引言 (01) 一、设计任务和要求............................. 1、1 设计要求 1、2 性能指标 1、3 设计方案的确定 二、单片机简要原理............................. 2、1 AT89C51的介绍 2、2 单片机最小系统 2、3 七段共阳极数码管 三、硬件设计................................... 3、1 键盘电路的设计 3、2 显示电路的设计 四、软件设计................................... 4、1 系统设计 4、2 显示电路的设计 五、调试与仿真................................. 5、1 Keil C51单片机软件开发系统 5、2 proteus的操作 六、心得体会.................................... 参考文献......................................... 附录1 系统硬件电路图............................ 附录2 程序清单.................................. 进制转换编程报告 一．引言： 进制转换是人们利用符号来计数的方法，包含很多种数字转换。进制转换由一组数码符号和两个基本因素（“基”与“权”）构成。 二．方法原理介绍： 十进制整数转换为二进制整数 十进制整数转换为二进制整数采用"除2取余，逆序排列"法。具体做法是：用2整除十进制整数，可以得到一个商和余数；再用2去除商，又会得到一个商和余数，如此进行，直到商为0时为止，然后把先得到的余数作为二进制数的低位有效位，后得到的余数作为二进制数的高位有效位，依次排列起来。 十进制整数转二进制 如：255=（11111111）B 255/2=127=====余1 127/2=63======余1 63/2=31=======余1 31/2=15=======余1 15/2=7========余1 7/2=3=========余1 3/2=1=========余1 1/2=0=========余1 789=1100010101 789/2=394.5 =1 第10位 394/2=197 =0 第9位 197/2=98.5 =1 第8位 98/2=49 =0 第7位 49/2=24.5 =1 第6位 24/2=12 =0 第5位 12/2=6 =0 第4位 6/2=3 =0 第3位 3/2=1.5 =1 第2位 1/2=0.5 =1 第1位 原理： 众所周知，二进制的基数为2，我们十进制化二进制时所除的2就是它的基数。谈到他的原理，就不得不说说关于位权的概念。某进制计数制中各位数字符号所表示的数值表示该数字符号值乘以一个与数字符号有关的常数，该常数称为“位权” 。位权的大小是以基数为底，数字符号所处的位置的序号为指数的整数 模数(A/D)转换器工作原理A/D转换器(Analog-to-Digital Converter)又叫模/数转换器,即是将模拟信号(电压或是电流的形式)转换成数字信号。这种数字信号可让仪表,计算机外设接口或是微处理机来加以操作或胜作使用。 A/D 转换器 (ADC)的型式有很多种，方式的不同会影响测量后的精准度。 A/D 转换器的功能是把模拟量变换成数字量。由于实现这种转换的工作原理和采用工艺技术不同，因此生产出种类繁多的A/D 转换芯片。 A/D 转换器按分辨率分为4 位、6 位、8 位、10 位、14 位、16 位和BCD码的31/2 位、51/2 位等。按照转换速度可分为超高速（转换时间=330ns），次超高速（330~3.3μS），高速（转换时间3.3~333μS），低速（转换时间＞330μS）等。 A/D 转换器按照转换原理可分为直接A/D 转换器和间接A/D 转换器。所谓直接A/D 转换器，是把模拟信号直接转换成数字信号，如逐次逼近型，并联比较型等。其中逐次逼近型A/D 转换器，易于用集成工艺实现，且能达到较高的分辨率和速度，故目前集成化A/D 芯片采用逐次逼近型者多；间接A/D 转换器是先把模拟量转换成中间量，然后再转换成数字量，如电压/时间转换型（积分型），电压/频率转换型，电压/脉宽转换型等。其中积分型A/D 转换器电路简单，抗干扰能力强，切能作到高分辨率，但转换速度较慢。有些转换器还将多路开关、基准电压源、时钟电路、译码器和转换电路集成在一个芯片内，已超出了单纯A/D 转换功能，使用十分方便。 ADC 经常用于通讯、数字相机、仪器和测量以及计算机系统中，可方便数字讯号处理和信息的储存。大多数情况下，ADC 的功能会与数字电路整合在同一芯片上，但部份设备仍需使用独立的ADC。行动电话是数字芯片中整合ADC 功能的例子，而具有更高要求的蜂巢式基地台则需依赖独立的ADC 以提供最佳性能。 ADC 具备一些特性，包括： 1. 模拟输入，可以是单信道或多信道模拟输入； 2. 参考输入电压，该电压可由外部提供，也可以在ADC 内部产生； 3. 频率输入，通常由外部提供，用于确定ADC 的转换速率； 4. 电源输入，通常有模拟和数字电源接脚； 5. 数字输出，ADC 可以提供平行或串行的数字输出。在输出位数越多(分辨率越好)以及转换时间越快的要求下，其制造成本与单价就越贵。 一个完整的A/D转换过程中，必须包括取样、保持、量化与编码等几部分电路。 AD转换器需注意的项目： 取样与保持 量化与编码 课程设计 题目不同数制的数据相互转换程序的 设计 学院计算机科学与技术 专业计算机科学与技术 班级计算机0605班 姓名余欢欢 指导教师刘传文 2009 年 1 月15 日 附件2： 课程设计任务书 学生姓名：余欢欢专业班级：计算机0605班 指导教师：刘传文工作单位：计算机科学与技术学院 题目: 初始条件： 理论：学完“汇编语言程序设计”、“课程计算机概论”、“高级语言程序设计”和“数字逻辑”。 实践：计算机学院科学系实验中心提供计算机和软件平台。如果自己有计算机可以在其上进行设计。 要求完成的主要任务:（包括课程设计工作量及其技术要求，以及说明书撰写等具体要求） （1）输入二进制，十六进制，十进制的无符号数，将它们转换成不同进制的形式，并且输出出来。 （2）程序应有操作提示、输入和输出，界面追求友好，最好是菜单式的界面。 （3）设计若干用例（测试数据），上机测试程序并分析（评价）所设计的程序。 （4）设计报告格式按附件要求书写。课程设计报告书正文的内容应包括： 在正文第一行写课程设计题目； 1.需求说明（要求、功能简述）或问题描述； 2.设计说明（简要的分析与概要设计）； 3.详细的算法描述； 4.源程序与执行结果（含测试方法和测试结果）； 5.使用说明； 6.总结，包括设计心得（设计的特点、不足、收获与体会）和展望（该 程序进一步改进扩展的设想）。 时间安排： 设计时间一周：周1：查阅相关资料。 周2：系统分析,设计。 周3~4：编程并上机调试。 周5：撰写课程设计报告。 设计验收安排：20周星期五8:00起到计算机学院科学系实验中心进行上机验收。 设计报告书收取时间：20周的星期五下午5:00之前。 指导教师签名： 2009年1月9日 系主任（或责任教师）签名： 2009年1月 9日 AD0809应用原理－－很全面的资料 1. 0809的芯片说明： ADC0809是带有8位A/D转换器、8路多路开关以及微处理机兼容的控制逻辑的C MOS组件。它是逐次逼近式A/D转换器，可以和单片机直接接口。 （1）ADC0809的内部逻辑结构 由上图可知，ADC0809由一个8路模拟开关、一个地址锁存与译码器、一个A/D转换器和一个三态输出锁存器组成。多路开关可选通8个模拟通道，允许8路模拟量分时输入，共用A/D转换器进行转换。三态输出锁器用于锁存A/D转换完的数字量，当OE端为高电平时，才可以从三态输出锁存器取走转换完的数据。 （2）．引脚结构 IN0－IN7：8条模拟量输入通道 ADC0809对输入模拟量要求：信号单极性，电压范围是0－5V，若信号太小，必须进行放大；输入的模拟量在转换过程中应该保持不变，如若模拟量变化太快，则需在输入前增加采样保持电路。 地址输入和控制线：4条 ALE为地址锁存允许输入线，高电平有效。当ALE线为高电平时，地址锁存与译码器将A，B，C三条地址线的地址信号进行锁存，经译码后被选中的通道的模拟量进转换器进行转换。A，B和C为地址输入线，用于选通IN0－IN7上的一路模拟量输入。通道选择表如下表所示。 C B A 选择的通道 000IN0 001IN1 010IN2 011IN3 100IN4 101IN5 110IN6 111IN7 数字量输出及控制线：11条 ST为转换启动信号。当ST上跳沿时，所有内部寄存器清零；下跳沿时，开始进行A /D转换；在转换期间，ST应保持低电平。EOC为转换结束信号。当EOC为高电平时，表明转换结束；否则，表明正在进行A/D转换。OE为输出允许信号，用于控制三条输出锁存器向单片机输出转换得到的数据。OE＝1，输出转换得到的数据；OE ＝0，输出数据线呈高阻状态。D7－D0为数字量输出线。 CLK为时钟输入信号线。因ADC0809的内部没有时钟电路，所需时钟信号必须由外界提供，通常使用频率为500KHZ， VREF（＋），VREF（－）为参考电压输入。 2．ADC0809应用说明 （1）．ADC0809内部带有输出锁存器，可以与AT89S51单片机直接相连。（2）．初始化时，使ST和OE信号全为低电平。 （3）．送要转换的哪一通道的地址到A，B，C端口上。 （4）．在ST端给出一个至少有100ns宽的正脉冲信号。 （5）．是否转换完毕，我们根据EOC信号来判断。 （6）．当EOC变为高电平时，这时给OE为高电平，转换的数据就输出给单片机了。 3．实验任务 天津职业技术师范大学Tianjin University of Technology and Education 《面向对象程序设计》 课程设计报告 设计进制转换计算器 学院：信息技术工程学院 专业：计算机科学与技术 班级学号：14 学生姓名：** 指导教师：*** 2012年12月 一．课程设计名称：采用面向对象的程序设计方法设计实现二进制、八进制、十进制、十六进制之间的进制转换计算器。 二．实用工具软件：Microsoft Visual C++ 三．课程设计内容简介： #include 学生毕业论文（设计）题目基于ARM的模数转换器的设计 姓名 XX 学号 XX 系部 XXXX系 专业 XXXXXXX技术 指导教师 XXXX 职称 XXXX（XXXX） XXXX年 1 月 XX 日 XXXXXXXXXXX教务处制 目录 摘要 (3) 关键词 (3) Abstract (3) Keywords (3) 1 绪论 (4) 1.1 技术背景 (4) 1.2 选题意义 (4) 2 A/D转换器基本原理 (4) 2.1 A/D转换器的基本原理 (4) 2.2 A/D转换器的基本功能 (5) 2.3 A/D转换模块 (5) 2.3.1 A/D转换模块概述 (5) 2.3.2 A/D转换的技术特性 (5) 2.3.3 A/D转换的功能寄存器框图 (5) 2.3.4 A/D转换初始化 (6) 2.3.5 A/D转换的操作 (6) 3 A/D转换器的设计 (7) 3.1 A/D转换器的工作原理 (7) 3.2 A/D转换电路 (8) 3.3 A/D转换器的原理图 (8) 4 A/D转换仿真结果 (9) 4.1 仿真设备 (9) 4.2 仿真设备简介 (9) 4.2.1 ADS1.2仿真软件 (9) 4.2.2 MagicARM2200 实验箱 (9) 4.3 仿真步骤 (12) 4.4 ADS1.2软件仿真 (12) 4.4.1 仿真软件 (12) 4.4.2 仿真硬件 (14) 4.5 仿真结果 (15) 结束语 (16) 致谢 (16) 参考文献 (16) 附录参考源程序 (16) 基于ARM的模数转换器的设计 XXXXXXX技术专业学生 XX 指导老师 XXXX 摘要：随着数字技术，特别是信息技术的飞速发展及普及，在现代控制通信及检测等领域，为了提高系统的性能指标，对信号的处理广泛采用了数字计算机技术。由于系统的实际对象往往都是一些模拟量（如温度、压力、位移、图像等），要使计算机或数字仪表能识别，处理这些信号，必须首先将这些模拟信号转换成数字信号；而经计算机分析，处理后输出的数字量也往往需要将其转换为相应模拟信号才能执行机构所接受。这样就需要一种能在模拟信号与数字信号之间起桥梁作用的电路——模数转换器。A/D转换器已成为信息系统中不可缺少的接口电路。为确保系统处理结果的精度，A/D转换器必须具有足够的转换精度，如果要实现快速变化信号的实时控制与检测，A/D转换器还要求具有较高的转换速度。转换精度与转换速度是衡量A/D的重要指标。随着集成技术的发展，现已研制和生产出许多单片和混合集成型的A/D转换器，它们具有愈来愈先进的技术指标。本文主要介绍了在ARM系统下，通过对A/D转换模块的设计。学习A/D接口原理及硬件电路，了解ARM的A/D 相关寄存器，利用外部模拟信号编程，实现ARM系统的A/D功能，掌握带有A/D的ARM编程实现A/D 功能的主要方法。 关键词：模数转换器；ADC模块；系统设计；仿真 ARM-based analog-to-digital converter design Student majoring in Computer-controlled technology professional XXX Ting Tutor XXX Abstract:The advent of digital technology, especially the rapid development of the information technology and the popularity of the field of modern control communication and detection, in order to improve system performance, signal processing widespread adoption of digital computer technology. Since the actual object of the system are often some analog quantity (such as temperature, pressure, displacement, image, etc.), make the computer or digital instrument can recognize, process these signals, you must first convert these analog signals into digital signals; while via computer analysis, the digital output after the processing is also often need to be converted to the corresponding analog signals in order to perform bodies accepted. Need a between the analog and digital signals from the bridge circuit - ADC .A / D converter the interface circuit has become indispensable in the information system. To ensure the accuracy of the system processing the results of the A / D converter must have a sufficient accuracy of the conversion, A / D converter is also required to have a higher conversion speed; if you want to achieve the real-time control and detection of rapidly changing signal. Conversion accuracy and conversion speed is an important indicator to measure the A / D. With the development of integration technology, has been developed and produced many monolithic and hybrid integration of A / D converter, they have more and more state-of-the-art technical indicators. This paper describes the ARM system, through the design of the A / D converter module. Learning A / D interface principle and the hardware circuit, ARM's A / D register, the use of external analog signals programmed to achieve a the ARM system of A / D function, master ARM programming with an A / D A / D function method. Keywords: analog-to-digital converter; ADC module; system design;simulation大数据结构课程设计——进制转换
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