EPM7032SLC44
?
MAX 7000 Programmable Logic
Device Family
November 2001, ver. 6.3Data Sheet
Features...■High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX? architecture
■ 5.0-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX7000S devices
–ISP circuitry compatible with IEEE Std. 1532
■Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S
devices
■Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S
devices with 128 or more macrocells
■Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates (see Tables1 and 2)
■5-ns pin-to-pin logic delays with up to 175.4-MHz counter
frequencies (including interconnect)
■PCI-compliant devices available
f For information on in-system programmable 3.3-V MAX 7000A or 2.5-V
MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data
Sheet.
Table 1.MAX 7000 Device Features
Feature EPM7032EPM7064EPM7096EPM7128E EPM7160E EPM7192E EPM7256E Usable
gates
6001,2501,8002,5003,2003,7505,000
Macrocells326496128160192256 Logic array
blocks
2468101216
Maximum
user I/O pins
366876100104124164
t PD (ns)667.57.5101212
t SU(ns)5566777
t FSU(ns) 2.5 2.533333
t CO1 (ns)44 4.5 4.5566
f CNT (MHz)151.5151.5125.0125.0100.090.990.9
MAX 7000 Programmable Logic Device Family Data Sheet
...and More Features I Open-drain output option in MAX 7000S devices
I Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
I Programmable power-saving mode for a reduction of over 50% in
each macrocell
I Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
I44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
I Programmable security bit for protection of proprietary designs
I 3.3-V or 5.0-V operation
–MultiVolt TM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
–Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
I Enhanced features available in MAX 7000E and MAX 7000S devices
–Six pin- or logic-driven output enable signals
–Two global clock signals with optional inversion
–Enhanced interconnect resources for improved routability
–Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
–Programmable output slew-rate control
I Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Table 2. MAX 7000S Device Features
Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S Usable gates6001,2502,5003,2003,7505,000 Macrocells3264128160192256 Logic array
blocks
248101216
Maximum
user I/O pins
3668100104124164
t PD (ns)55667.57.5
t SU(ns) 2.9 2.9 3.4 3.4 4.1 3.9
t FSU (ns) 2.5 2.5 2.5 2.533
t CO1 (ns) 3.2 3.24 3.9 4.7 4.7
f CNT (MHz)175.4175.4147.1149.3125.0128.2
MAX 7000 Programmable Logic Device Family Data Sheet
I Additional design entry and simulation support provided by EDIF
2 0 0 and
3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest
I Programming support
–Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all
MAX 7000 devices
–The BitBlaster TM serial download cable, ByteBlasterMV TM parallel port download cable, and MasterBlaster TM
serial/universal serial bus (USB) download cable program MAX
7000S devices
General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.
Table 3. MAX 7000 Speed Grades
Device Speed Grade
-5-6-7-10P-10-12P-12-15-15T-20 EPM7032v v v v v v
EPM7032S v v v v
EPM7064v v v v v
EPM7064S v v v v
EPM7096v v v v
EPM7128E v v v v v v EPM7128S v v v v
EPM7160E v v v v v EPM7160S v v v v
EPM7192E v v v v EPM7192S v v v
EPM7256E v v v v EPM7256S v v v
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000E devices—including the EPM7128E, EPM7160E,
EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.
In-system programmable MAX 7000 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the
enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.
Notes:
(1)Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only.(2)
The MultiVolt I/O interface is not available in 44-pin packages.
Table 4. MAX 7000 Device Features
Feature
EPM7032EPM7064EPM7096
All MAX 7000E Devices
All MAX 7000S Devices
ISP via JTAG interface v JTAG BST circuitry v (1)Open-drain output option v
Fast input registers v v Six global output enables v v Two global clocks v v Slew-rate control v
v MultiVolt interface (2)v v v Programmable register v v v Parallel expanders v v v Shared expanders v v v Power-saving mode v v v Security bit
v v v PCI-compliant devices available v
v
v
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices are available in a wide range of packages, including PLCC, PGA, PQFP, RQFP, and TQFP packages. See Table 5.
Notes:
(1)When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins become JTAG pins.
(2)
Perform a complete thermal analysis before committing a design to this device package. For more information, see the Operating Requirements for Altera Devices Data Sheet .
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times.
Table 5. MAX 7000 Maximum User I/O Pins Note (1)Device
44-Pin PLCC 44-Pin PQFP 44-Pin TQFP 68-Pin PLCC 84-Pin PLCC 100-Pin PQFP 100-Pin TQFP
160-Pin PQFP 160-Pin PGA 192-Pin PGA 208-Pin PQFP 208-Pin RQFP
EPM70323636
36EPM7032S 3636EPM7064363652
6868
EPM7064S 36
36
6868
EPM7096526476EPM7128E 6884100EPM7128S 688484 (2)
100EPM7160E 6484
104EPM7160S 64
84 (2)104EPM7192E 124124
EPM7192S 124EPM7256E 132 (2)
164
164EPM7256S 164 (2)
164
MAX 7000 Programmable Logic Device Family Data Sheet
MAX 7000 devices contain from 32 to 256 macrocells that are combined
into groups of 16 macrocells, called logic array blocks (LABs). Each
macrocell has a programmable-AND/fixed-OR array and a configurable
register with independently programmable clock, clock enable, clear, and
preset functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
The MAX 7000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
designer to configure one or more macrocells to operate at 50% or lower
power while adding only a nominal timing delay. MAX 7000E and
MAX 7000S devices also provide an option that reduces the slew rate of
the output buffers, minimizing noise transients when non-speed-critical
signals are switching. The output drivers of all MAX 7000 devices (except
44-pin devices) can be set for either 3.3-V or 5.0-V operation, allowing
MAX 7000 devices to be used in mixed-voltage systems.
The MAX 7000 family is supported byAltera development systems, which
are integrated packages that offer schematic, text—including VHDL,
Verilog HDL, and the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. The software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The software runs
on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series
700/800 workstations.
f For more information on development tools, see the MAX+PLUS II
Programmable Logic Development System & Software Data Sheet and the
Quartus Programmable Logic Development System & Software Data Sheet.
Functional Description The MAX 7000 architecture includes the following elements: I Logic array blocks
I Macrocells
I Expander product terms (shareable and parallel)
I Programmable interconnect array
I I/O control blocks
MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture includes four dedicated inputs that can
be used as general-purpose inputs or as high-speed, global control
signals (clock, clear, and two output enable signals) for each
macrocell and I/O pin. Figure 1 shows the architecture of EPM7032,
EPM7064, and EPM7096 devices.
Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices. Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macrocell arrays, as shown in Figures 1 and 2.
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
MAX 7000 Programmable Logic Device Family Data Sheet
Each LAB is fed by the following signals:
I36 signals from the PIA that are used for general logic inputs
I Global controls that are used for secondary register functions
I Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Macrocells
The MAX 7000 macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devices is shown in Figure 3.
Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 4 shows a MAX 7000E and MAX 7000S device macrocell.
Figure 4. MAX 7000E & MAX 7000S Device Macrocell
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the OR and
XOR gates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, preset, clock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
I Shareable expanders, which are inverted product terms that are fed
back into the logic array
I Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.
MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes: I By a global clock signal. This mode achieves the fastest clock-to-
output performance.
I By a global clock signal and enabled by an active-high clock
enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global
clock.
I By an array clock implemented with a product term. In this
mode, the flipflop can be clocked by signals from buried
macrocells or I/O pins.
In EPM7032, EPM7064, and EPM7096 devices, the global clock signal is available from a dedicated clock pin, GCLK1, as shown in Figure 1. In MAX 7000E and MAX 7000S devices, two global clock signals are available. As shown in Figure 2, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As shown in Figures 3 and 4, the product-term select matrix allocates product terms to control these operations. Although the
product-term-driven preset and clear of the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in the device will be set to a low state.
All MAX 7000E and MAX 7000S I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be driven to an input D flipflop with an extremely fast (2.5 ns) input setup time.
Expander Product Terms
Although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel expander product terms (“expanders”) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.
MAX 7000 Programmable Logic Device Family Data Sheet
Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of
uncommitted single product terms (one from each macrocell) with
inverted outputs that feed back into the logic array. Each shareable
expander can be used and shared by any or all macrocells in the LAB to
build complex logic functions. A small delay (t SEXP) is incurred when
shareable expanders are used. Figure 5 shows how shareable expanders
can feed multiple macrocells.
Figure 5. Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 20 product terms to directly feed the
macrocell OR logic, with five product terms provided by the macrocell and
15 parallel expanders provided by neighboring macrocells in the LAB.
MAX 7000 Programmable Logic Device Family Data Sheet
The compiler can allocate up to three sets of up to five parallel expanders
automatically to the macrocells that require additional product terms.
Each set of five parallel expanders incurs a small, incremental timing
delay (t PEXP). For example, if a macrocell requires 14 product terms, the
Compiler uses the five dedicated product terms within the macrocell and
allocates two sets of parallel expanders; the first set includes five product
terms and the second set includes four product terms, increasing the total
delay by 2 ×t PEXP.
Two groups of 8 macrocells within each LAB (e.g., macrocells
1 through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them. Figure 6 shows how parallel expanders can be
borrowed from a neighboring macrocell.
Figure 6. Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
MAX 7000 Programmable Logic Device Family Data Sheet
Programmable Interconnect Array
Logic is routed between LABs via the programmable interconnect array
(PIA). This global bus is a programmable path that connects any signal
source to any destination on the device. All MAX 7000 dedicated inputs,
I/O pins, and macrocell outputs feed the PIA, which makes the signals
available throughout the entire device. Only the signals required by each
LAB are actually routed from the PIA into the LAB. Figure 7 shows how
the PIA signals are routed into the LAB. An EEPROM cell controls one
input to a 2-input AND gate, which selects a PIA signal to drive into the
LAB.
Figure 7. PIA Routing
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000 PIA
has a fixed delay. The PIA thus eliminates skew between signals and
makes timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V CC. Figure 8 shows the I/O
control block for the MAX 7000 family. The I/O control block of EPM7032,
EPM7064, and EPM7096 devices has two global output enable signals that
are driven by two dedicated active-low output enable pins (OE1 and OE2).
The I/O control block of MAX 7000E and MAX 7000S devices has six
global output enable signals that are driven by the true or complement of
two output enable signals, a subset of the I/O pins, or a subset of the I/O
macrocells.
MAX 7000 Programmable Logic Device Family Data Sheet Figure 8. I/O Control Block of MAX 7000 Devices
EPM7032, EPM7064 & EPM7096 Devices
MAX 7000E & MAX 7000S Devices
Note:
(1)The open-drain output option is available only in MAX 7000S devices.
MAX 7000 Programmable Logic Device Family Data Sheet
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to V CC, the output is
enabled.
The MAX 7000 architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
In-System Programma-bility (ISP)MAX 7000S devices are in-system programmable via an
industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE Std. 1149.1-1990). ISP allows quick, efficient iterations during design development and debugging cycles. The MAX 7000S architecture internally generates the high programming voltage required to program EEPROM cells, allowing in-system programming with only a single 5.0 V power supply. During in-system programming, the I/O pins are tri-stated and pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k?.
ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in-circuit test equipment before they are programmed. MAX 7000S devices can be programmed by downloading the information via in-circuit testers (ICT), embedded processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster, BitBlaster download cables. (The ByteBlaster cable is obsolete and is replaced by the ByteBlasterMV cable, which can program and configure 2.5-V, 3.3-V, and 5.0-V devices.) Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling and allows devices to be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem.
In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm are marked with an “F” suffix in the ordering code.
The Jam TM Standard Test and Programming Language (STAPL) can be used to program MAX 7000S devices with in-circuit testers, PCs, or embedded processor.
MAX 7000 Programmable Logic Device Family Data Sheet f For more information on using the Jam language, see Application Note 88
(Using the Jam Language for ISP & ICR via an Embedded Processor).
The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programmable Speed/Power Control MAX 7000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000 device for either high-speed (i.e., with the Turbo Bit TM option turned on) or low-power (i.e., with the Turbo Bit option turned off) operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (t LPA) for the t LAD, t LAC, t IC, t EN, and t SEXP, t ACL, and t CPPW parameters.
Output
Con?guration MAX 7000 device outputs can be programmed to meet a variety of system-level requirements.
MultiVolt I/O Interface
MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O interface feature, which allows MAX 7000 devices to interface with systems that have differing supply voltages. The 5.0-V devices in all packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V V CCINT level, input voltage thresholds are at TTL levels, and are therefore compatible with both 3.3-V and 5.0-V inputs.
The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V supply, the output levels are compatible with 5.0-V systems. When V CCIO is connected to a 3.3-V supply, the output high is 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with V CCIO levels lower than 4.75 V incur a nominally greater timing delay of t OD2instead of t OD1.
MAX 7000 Programmable Logic Device Family Data Sheet
Open-Drain Output Option (MAX 7000S Devices Only)
MAX 7000S devices provide an optional open-drain (functionally
equivalent to open-collector) output for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
By using an external 5.0-V pull-up resistor, output pins on MAX 7000S
devices can be set to meet 5.0-V CMOS input voltages. When V CCIO is
3.3V, setting the open drain option will turn off the output pull-up
transistor, allowing the external pull-up resistor to pull the output high
enough to meet 5.0-V CMOS input voltages. When V CCIO is 5.0V, setting
the output drain option is not necessary because the pull-up transistor will
already turn off when the pin exceeds approximately 3.8 V, allowing the
external pull-up resistor to pull the output high enough to meet 5.0-V
CMOS input voltages.
Slew-Rate Control
The output buffer for each MAX 7000E and MAX 7000S I/O pin has an
adjustable output slew rate that can be configured for low-noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay of 4 to 5 ns. In MAX7000E devices, when the
Turbo Bit is turned off, the slew rate is set for low noise performance. For
MAX7000S devices, each I/O pin has an individual EEPROM bit that
controls the slew rate, allowing designers to specify the slew rate on a
pin-by-pin basis.
Programming with External Hardware MAX 7000 devices can be programmed on Windows-based PCs with the Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs a continuity check to ensure adequate electrical contact between the adapter and the device.
f For more information, see the Altera Programmin
g Hardware Data Sheet.
The Altera development system can use text- or waveform-format test
vectors created with the Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional behavior of a
MAX7000 device with the results of simulation. Moreover, Data I/O, BP
Microsystems, and other programming hardware manufacturers also
provide programming support for Altera devices.
f For more information, see the Programmin
g Hardware Manufacturers.
MAX 7000 Programmable Logic Device Family Data Sheet
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std. 1149.1-1990. Table 6 describes the JTAG instructions supported by the MAX 7000 family. The pin-out tables (see the Altera web site
(https://www.wendangku.net/doc/2a2744933.html,) or the Altera Digital Library for pin-out information) show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins.
Table 6. MAX 7000 JTAG Instructions
JTAG Instruction Devices Description
SAMPLE/PRELOAD EPM7128S
EPM7160S
EPM7192S
EPM7256S Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins.
EXTEST EPM7128S
EPM7160S
EPM7192S
EPM7256S Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins.
BYP ASS EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation.
IDCODE EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO.
ISP Instructions EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S These instructions are used when programming MAX 7000S devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc), or Serial Vector Format file (.svf) via an embedded processor or test equipment.
MAX 7000 Programmable Logic Device Family Data Sheet
The instruction register length of MAX 7000S devices is 10 bits. Tables 7 and 8 show the boundary-scan register length and device IDCODE information for MAX 7000S devices.
Note:
(1)
This device does not support JTAG boundary-scan testing. Selecting either the EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register.
Notes:
(1)The most significant bit (MSB) is on the left.
(2)
The least significant bit (LSB) for all JTAG IDCODEs is 1.
Table 7. MAX 7000S Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EPM7032S 1 (1)EPM7064S 1 (1)EPM7128S 288EPM7160S 312EPM7192S 360EPM7256S
480
Table 8. 32-Bit MAX 7000 Device IDCODE Note (1)Device
IDCODE (32 Bits)
Version (4 Bits)
Part Number (16 Bits)
Manufacturer’s Identity (11 Bits) 1 (1 Bit) (2)
EPM7032S 00000111 0000 0011 0010000011011101EPM7064S 00000111 0000 0110 0100000011011101EPM7128S 00000111 0001 0010 1000000011011101EPM7160S 00000111 0001 0110 0000000011011101EPM7192S 00000111 0001 1001 0010000011011101EPM7256S 0000
0111 0010 0101 0110
00001101110
1