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BS62LV1600FI55中文资料

BS62LV1600FI55中文资料
BS62LV1600FI55中文资料

Very Low Power CMOS SRAM 2M X 8 bit

BS62LV1600

Pb-Free and Green package materials are compliant to RoHS

n FEATURES

? Wide V CC operation voltage : 2.4V ~ 5.5V ? Very low power consumption : V CC = 3.0V Operation current : 46mA (Max.) a t 55ns 2mA (Max.) at 1MHz Standby current : 1.5uA (Typ.) at 25 O C V CC = 5.0V Operation current : 115mA (Max.) a t 55ns 10mA (Max.) a t 1MHz Standby current : 6.0uA (Typ.) at 25O C ? High speed access time : -55 55ns (Max.) at V CC : 3.0~5.5V -70 70ns (Max.) at V CC : 2.7~5.5V ? Automatic power down when chip is deselected ? Easy expansion with CE1, CE2 and OE options ? Three state outputs and TTL compatible ? Fully static operation ? Data retention supply voltage as low as 1.5V n DESCRIPTION

The BS62LV1600 is a high performance, very low power CMOS Static Random Access Memory organized as 2048K by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 1.5uA at 3.0V/25O C and maximum access time of 55ns at 3.0V/85O C.

Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers.

The BS62LV1600 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1600 is available in JEDEC standard 44-pin TSOP II and 48-ball BGA package.

n POWER CONSUMPTION

POWER DISSIPATION

STANDBY

(I CCSB1, Max)

Operating

(I CC , Max)

V CC =5.0V V CC =3.0V PRODUCT FAMILY

OPERATING TEMPERATURE

V CC =5.0V V CC =3.0V

1MHz

10MHz

f Max. 1MHz

10MHz

f Max.

PKG TYPE

BS62LV1600EC TSOP II-44 BS62LV1600FC Commercial +0O C to +70O C 50uA 8.0uA 9mA 48mA 113mA 1.5mA 19mA 45mA

BGA-48-0912 BS62LV1600EI

TSOP II-44 BS62LV1600FI

Industrial -40O C to +85O C

100uA 16uA 10mA 50mA 115mA 2mA 20mA 46mA

BGA-48-0912

n PIN CONFIGURATIONS

n BLOCK DIAGRAM

Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.

G H F E D C B A 1 2 3 4 5 6 A9 A11 A10 A19

A12 A14 A13 A15 WE NC NC NC DQ7 A17 A16 A7 VSS VCC DQ2 DQ1 DQ6 DQ5 NC A5 OE A3 A0 A6 A4 A1

A2

CE2 NC NC NC

CE1 DQ4 NC 48-ball BGA top view NC NC DQ0 VSS VCC DQ3 NC A18 A20 A8

n TRUTH TABLE

n ABSOLUTE MAXIMUM RATINGS (1)

SYMBOL PARAMETER RATING UNITS

V TERM Terminal Voltage with

Respect to GND

-0.5(2) to 7.0 V

T BIAS Temperature Under

Bias

-40 to +125 O C

T STG Storage Temperature -60 to +150 O C

P T Power Dissipation 1.0 W

I OUT DC Output Current 20 mA

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. –2.0V in case of AC pulse width less than 30 ns. n OPERATING RANGE

RANG

AMBIENT

TEMPERATURE

V CC Commercial 0O C to + 70O C 2.4V ~ 5.5V

Industrial -40O C to + 85O C 2.4V ~ 5.5V

n CAPACITANCE (1) (T A = 25O C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS

C IN

Input

Capacitance

V IN = 0V 10 pF

C IO

Input/Output

Capacitance

V I/O = 0V 12 pF

1. This parameter is guaranteed and not 100% tested.

n DC ELECTRICAL CHARACTERISTICS (T A =-40O C to +85O

C)

1. Typical characteristics are at T A =25O C and not 100% tested.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.

3. Overshoot: V CC +1.0V in case of pulse width less than 20 ns.

4. F MAX =1/t RC.

5. I CC(MAX.) is 45mA/113mA at V CC =3.0V/5.0V and T A =70O C.

6. I CCSB1(MAX.) is 8.0uA/50uA at V CC =3.0V/5.0V and T A =70O C.

n DATA RETENTION CHARACTERISTICS (T A = -40O C to +85O

C)

1. V CC =1.5V, T A =25O C and not 100% tested.

2. t RC = Read Cycle Time.

3. I CCRD(Max.) is

4.0uA at T A =70O C.

n LOW V CC DATA RETENTION WAVEFORM (1) (CE1 Controlled)

Data Retention Mode V CC

t CDR

V CC t R

V IH

V IH

CE1≧V CC - 0.2V V DR ≧1.5V CE1

V CC

n LOW V CC DATA RETENTION WAVEFORM (2) (CE2 Controlled)

n AC TEST CONDITIONS (Test Load and Input/Output Reference)

Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc t CLZ , t OLZ , t CHZ , t OHZ , t WHZ C L = 5pF+1TTL Output Load

Others

C L = 30pF+1TTL

1. Including jig and scope capacitance.

n KEY TO SWITCHING WAVEFORMS

n AC ELECTRICAL CHARACTERISTICS (T A = -40O C to +85O

C)

READ CYCLE

CE2 Data Retention Mode V CC t CDR V CC t R V IL

V IL V CC

V DR ≧1.5V CE2≦0.2V 1 TTL ALL INPUT PULSES

→ ← 90%

V CC GND Rise Time : 1V/ns Fall Time : 1V/ns

90%

→ ← 10%

10%

n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1 (1,2,4)

READ CYCLE 2 (1,3,4)

READ CYCLE 3 (1, 4)

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V IL and CE2= V IH .

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = V IL .

5. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested.

t RC t OH

t AA D OUT ADDRESS t OH

D OUT

CE2 CE1

D OUT

CE2 CE1 OE ADDRESS

n AC ELECTRICAL CHARACTERISTICS (T A = -40O

C to +85O

C)

WRITE CYCLE

n SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1 (1)

t WC

t WR1

(3)

t CW

(11)

t CW

(11)

t WP

(2)

t AW

t OHZ

(4,10)

t AS t WR2(3)

t DH

t DW

D IN

D OUT

WE

CE2

CE1

OE

ADDRESS

(5)

(5)

WRITE CYCLE 2 (1,6)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.

3. t WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V IL ).

7. D OUT is the same phase of write data of this write cycle. 8. D OUT is the read data of next address.

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. T ransition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. 11. t CW is measured from the later of CE1 going low or CE2 going high to the end of write.

D IN

D OUT

WE CE2 CE1

ADDRESS

n ORDERING INFORMATION

BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.

n PACKAGE DIMENSIONS

TSOP II-44

n PACKAGE DIMENSIONS (continued)

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

N E

D

NOTES:

4812.09.0

E1

D1e

3.75

5.250.75 48 mini-BGA (9mm x 12mm)

n Revision History

Revision No. History Draft Date Remark

2.2 Add Icc1 characteristic parameter Jan. 13, 2006

Improve Iccsb1 spec.

I-grade from 220uA to 100uA at 5.0V

20uA to 16uA at 3.0V

C-grade from 110uA to 50uA at 5.0V

10uA to 8.0uA at 3.0V

2.3 Change I-grade operation temperature range May. 25, 2006

- from –25O C to –40O C

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