74ALVCH162240TX中文资料

? 2001 Fairchild Semiconductor Corporation DS500700

https://www.wendangku.net/doc/2b10528138.html,

November 2001Revised November 2001

74ALVCH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver

74ALVCH162240

Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold and 26? Series Resistors in Outputs

General Description

The ALVCH162240 contains sixteen inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.

The ALVCH162240 data inputs include active bushold cir-cuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.The 74ALVCH162240 is also designed with 26? series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock driv-ers, and bus transceivers/transmitters.

The 74ALVCH162240 is designed for low voltage (1.65V to 3.6V) V CC applications with output capability up to 3.6V.The 74ALVCH162240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.Features

s 1.65V to 3.6V V CC supply operation s 3.6V tolerant control inputs and outputs

s Bushold on data inputs eliminating the need for external pull-up/pull-down resistors s 26? series resistors in outputs s t PD

3.8 ns max for 3.0V to 3.6V V CC

4.3 ns max for 2.3V to 2.7V V CC 7.6 ns max for 1.65V to 1.95V V CC s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78s ESD performance:

Human body model > 2000V Machine model > 200V

Ordering Code:

Devices also available in T ape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol Pin Descriptions

Order Number Package Number

Package Descriptions

74ALVCH162240T

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names

Description

OE n Output Enable Input (Active LOW)

I 0–I 15Bushold Inputs

O 0–O 15

Outputs

https://www.wendangku.net/doc/2b10528138.html, 2

74A L V C H 162240

Connection Diagram

Truth Tables

H = HIGH Voltage Level L = LOW Voltage Level

X = Immaterial (HIGH or LOW, inputs may not float)Z = High Impedance

Functional Description

The 74ALVCH162240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) con-trolled with each nibble functioning identically, but indepen-dent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE out-puts are controlled by an Output Enable (OE n ) input. When OE n is LOW, the outputs are in the 2-state mode. When OE n is HIGH, the standard outputs are in the high imped-ance mode but this does not interfere with entering new data into the inputs.

Logic Diagram

Inputs

Outputs OE 1I 0–I 3O 0–O 3L L H L H L H

X

Z Inputs

Outputs OE 2I 4–I 7O 4–O 7L L H L H L H

X Z Inputs

Outputs OE 3I 8–I 11O 8–O 11

L L H L H L H

X Z Inputs

Outputs OE 4I 12–I 15O 12–O 15

L L H L H L H

X Z

https://www.wendangku.net/doc/2b10528138.html,

74ALVCH162240

Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions (Note 3)

Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat-ings. The “Recommended Operating Conditions ” table will define the condi-tions for actual device operation.

Note 2: I O Absolute Maximum Rating must be observed.

Note 3: Floating or unused control inputs must be held HIGH or LOW.

DC Electrical Characteristics

Supply Voltage (V CC )?0.5V to +4.6V DC Input Voltage (V I )?0.5V to 4.6V Output Voltage (V O ) (Note 2)?0.5V to V CC +0.5V

DC Input Diode Current (I IK ) V I < 0V

?50 mA DC Output Diode Current (I OK )V O < 0V

?50 mA DC Output Source/Sink Current (I OH /I OL )

±50 mA DC V CC or GND Current per Supply Pin (I CC or GND)

±100 mA

Storage Temperature Range (T STG )

?65°C to +150°C

Power Supply Operating 1.65V to 3.6V

Input Voltage 0V to V CC Output Voltage (V O )

0V to V CC

Free Air Operating Temperature (T A )?40°C to +85°C

Minimum Input Edge Rate (?t/?V)V IN = 0.8V to 2.0V, V CC = 3.0V

10 ns/V

Symbol Parameter

Conditions

V CC Min Max

Units

(V)V IH

HIGH Level Input Voltage

1.65 - 1.950.65 x V CC

V

2.3 - 2.7 1.72.7 -

3.6

2.0

V IL

LOW Level Input Voltage

1.65 - 1.950.35 x V CC

V 2.3 - 2.70.72.7 - 3.6

0.8

V OH

HIGH Level Output Voltage

I OH = ?100 μA 1.65 - 3.6V CC - 0.2V

I OH = ?2 mA 1.65 1.2I OH = ?4 mA 2.3 1.9

I OH = ?6 mA 2.3 1.73 2.4I OH = ?8 mA 2.72I OH = ?12 mA

3.02

V OL

LOW Level Output Voltage

I OL = 100 μA 1.65 - 3.60.2V I OL = 2 mA 1.650.45I OL = 4 mA 2.30.4I OL = 6 mA 2.30.5530.55I OL = 8 mA 2.70.6I OL = 12 mA

30.8I I Input Leakage Current 0 ≤ V I ≤ 3.6V 3.6±5.0

μA I I(HOLD)

Bushold Input Minimum V IN = 0.58V 1.6525μA

Drive Hold Current

V IN = 1.07V 1.65?25V IN = 0.7V 2.345V IN = 1.7V 2.3?45V IN = 0.8V 3.075V IN = 2.0V 3.0?75

0 < V O ≤ 3.6V

3.6±500I OZ 3-STATE Output Leakage 0 ≤ V O ≤ 3.6V

3.6±10μA I CC Quiescent Supply Current V I = V CC or GND, I O = 0 3.640μA ?I CC

Increase in I CC per Input

V IH = V CC ? 0.6V

3 - 3.6

750

μA

https://www.wendangku.net/doc/2b10528138.html, 4

74A L V C H 162240

AC Electrical Characteristics

Capacitance

Symbol

Parameter

T A = ?40°C to +85°C, R L = 500?

Units

C L = 50 pF

C L = 30 pF

V CC = 3.3V ± 0.3V V CC = 2.7V V CC = 2.5V ± 0.2V

V CC = 1.8V ± 0.15V Min

Max Min Max Min Max Min Max t PHL , t PLH Propagation Delay 1.3 3.8 1.5 4.3 1.0 3.8 1.57.6ns t PZL , t PZH Output Enable Time 1.3 4.3 1.5 5.6 1.0 5.1 1.59.8ns t PLZ , t PHZ

Output Disable Time

1.3

4.1

1.5

4.5

1.0

4.0

1.5

7.2

ns Symbol Parameter

Conditions

T A = +25°C Units V CC Typical C IN Input Capacitance V I = 0V or V CC 3.36pF C OUT Output Capacitance

V I = 0V or V CC

3.37pF C PD

Power Dissipation Capacitance

Outputs Enabled f = 10 MHz, C L = 50 pF

3.320pF

2.5

20

https://www.wendangku.net/doc/2b10528138.html,

74ALVCH162240

AC Loading and Waveforms

FIGURE 1. AC Test Circuit

TABLE 1. Values for Figure 1 TABLE 2. Variable Matrix

(Input Characteristics: f = 1MHz; t r = t f = 2ns; Z 0 = 50?

FIGURE 2. Waveform for Inverting and Non-Inverting Functions

FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic

TEST SWITCH t PLH , t PHL Open t PZL , t PLZ V L t PZH , t PHZ

GND

Symbol V CC

3.3V ± 0.3V

2.7V 2.5V ± 0.2V 1.8V ± 0.15V

V mi 1.5V 1.5V V CC /2V CC /2V mo 1.5V 1.5V V CC /2V CC /2V X V OL + 0.3V V OL + 0.3V V OL + 0.15V V OL + 0.15V V Y V OH ? 0.3V

V OH ? 0.3V

V OH ? 0.15V V OH ? 0.15V V L

6V

6V

V CC *2

V CC *2

https://www.wendangku.net/doc/2b10528138.html,

6

74A L V C H 162240 L o w V o l t a g e 16-B i t I n v e r t i n g B u f f e r /L i n e D r i v e r

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

https://www.wendangku.net/doc/2b10528138.html,