ADM1232ARNZ中文资料

REV.B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

a

ADM1232

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: https://www.wendangku.net/doc/2f10633173.html, Fax: 781/326-8703? Analog Devices, Inc., 1997

Microprocessor Supervisory Circuit

FUNCTIONAL BLOCK DIAGRAM

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ADM1232–SPECIFICATIONS (V CC

= Full Operating Range, T A

= T

MIN to T MAX unless otherwise noted)

P arameter

Min Typ Max Units Test Conditions/Comments TEMPERATURE –40+85

°C T A = T MIN to T MAX

POWER SUPPLY Voltage 4.5

5.0 5.5V Current

2050μA V IL , V IH = CMOS Levels 200500μA V IL , V IH = TTL Levels

STROBE AND PB RESET INPUTS Input High Level 2.0V CC + 0.3V Input Low Level –0.3+0.8V INPUT LEAKAGE CURRENT (STROBE , TOLERANCE)–1.0

+1.0

μA TD 1.6

μA OUTPUT CURRENT RESET

810mA When V CC Is at 4.5 V–5.5 V RESET , RESET

–8

–12

mA

When V CC Is at 4.5 V–5.5 V

OUTPUT VOLTAGE RESET /RESET

V CC – 0.5V CC – 0.1

V

While sourcing less than 500 μA, RESET remains within 0.5 V of V CC on power-down until V CC drops below 2.0 V. While sinking less than 500 μA, RESET remains within 0.5 V of GND on power-down until V CC drops below 2.0 V.

RESET /RESET High Level 0.4

V RESET /RESET Low Level

2.4

V

1 V OPERATION

RESET Output Voltage V CC – 0.1V While Sourcing Less than 50 μA RESET Output Voltage

0.1

V

While Sinking Less than 50 μA

V CC TRIP POINT 5% 4.5 4.62 4.74V TOLERANCE = GND 10%

4.25

4.37

4.49V

TOLERANCE = V CC CAPACITANCE

Input (STROBE , TOLERANCE)5pF T A = +25°C Output (RESET, RESET )7

pF

T A = +25°C

PB RESET Time 20ms PB RESET Must Be Held Low for a Minimum Delay

1

4

20

ms

of 20 ms to Guarantee a Reset

RESET ACTIVE TIME 2506101000ms STROBE

Pulse Width 70ns Timeout Period

62.5150250ms TD = 0 V

2506001000ms TD = Floating 50012002000ms TD = V CC

V CC

Fall Time 10μS Guaranteed by Design Rise Time

μS Guaranteed by Design

V CC FAIL DETECT TO RESET OUTPUT DELAY RESET AND RESET Are Logically Correct

50

μs After V CC Falls Below the Set Tolerance Voltage (Figure 5)

250

6101000

ms

After V CC Rises Above the Set Tolerance Voltage

Specifications subject to change without notice.

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ADM1232

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ORDERING GUIDE

Temperature Package Model

Range Options*ADM1232ARM –40°C to +85°C RM-8ADM1232AN –40°C to +85°C N-8ADM1232ARW –40°C to +85°C R-16ADM1232ARN –40°C to +85°C

R-8

*N= Plastic DIP; R = Small Outline; RM = microSOIC.

ABSOLUTE MAXIMUM RATINGS*

(T A = +25°C unless otherwise noted)

V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . .–0.3 V to V CC + 0.3 V Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C N-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW Derate by 13.5 mW/°C above 25°C

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .100°C/W R-16

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .900 mW Derate by 12 mW/°C above 25°C

θJA Thermal Impedance (Still Air) . . . . . . . . . . . . . .73°C/W

RM-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .900 mW Derate by 12 mW/°C above 25°C

θJA Thermal Impedance (Still Air) . . . . . . . . . . . . .206°C/W R-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .900 μW Derate by 12 mW/°C above 25°C

θJA Thermal Impedance (Still Air) . . . . . . . . . . . . .153°C/W

*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.Although the ADM1232 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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ADM1232

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PIN FUNCTION DESCRIPTIONS

Mnemonic Function

PB RESET Push Button Reset Input. This debounced input will ignore pulses of less than 1 ms and is guaranteed to re-spond to pulses greater than 20 ms.

TD

Time Delay Set allows the user to select the maximum amount of time the ADM1232 will allow the STROBE input to remain inactive (i.e., STROBE is not receiving any high-to-low transitions), without forcing the ADM1232 to generate a RESET pulse. (See STROBE specifications, Figure 4 and the note on STROBE timeout selection.)

TOLERANCE Tolerance Input. This input will determine how much the supply voltage will be allowed to decrease (as a per-centage tolerance) before a RESET is asserted. Connect to V CC for 10% and GND for 5%.GND

0 V ground reference for all signals.

RESET Active high logic output. Will be asserted when:

1.V CC decreases below the amount specified by the TOLERANCE input or,

2.PB RESET is forced low or,

3.If there are no high-to-low transitions within the limits set by TD at STROBE or,

4.During power-up.

RESET Inverse of RESET, with an open drain output.

STROBE The STROBE input is used to monitor the activity of a microprocessor. If there are no high-to-low transi-tions within the time specified by TD, a reset will be asserted.V CC

Power supply input +5 V.

PIN CONFIGURATIONS

R-16

N-8 and R-8

RM-8

NC = NO CONNECT

NC NC TD NC TOLERANCE GND PB RESET NC PB RESET TD TOLERANCE GND PB RESET TD TOLERANCE GND O B S

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ADM1232

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STROBE Timeout Selection

TD or time delay set is used to set the Strobe Timeout Period.The Strobe Timeout Period is defined as being the maximum time between high-to-low transitions (Figure 4) that STROBE will accept before a reset will be asserted. The Strobe timeout settings are listed in Table I.

Table I.

Condition Min Typ Max Units TD = 0 V 62.5150250ms TD = Floating 2506001000ms TD = V CC

500

1200

2000

ms

STROBE Figure 4.STROBE Parameters

V CC

RESET

+5V

RESET

+4.5V (5% TRIP POINT)

RESET OUTPUT DELAY WHEN IS V CC FALLING

RESET OUTPUT DELAY WHEN IS V CC RISING

+5V

+4.25V (10% TRIP POINT)

Figure 5.Reset Output Delay

TOLERANCE

The TOLERANCE input is used to determine the level V CC can vary below 5 V without the ADM1232 asserting a reset. Con-necting TOLERANCE to ground will select a –5% tolerance level and will cause the ADM1232 to generate a reset if V CC falls below 4.75 V (typical). If TOLERANCE is connected to V CC a –10% tolerance level is selected and will cause the

ADM1232 to generate a reset if V CC falls below 4.5 V (typical).Check the parameters for the V CC trip point in the ADM1232Specifications for more information.

RESET AND RESET OUTPUTS

While RESET is capable of sourcing and sinking current,RESET is an open drain MOSFET which sinks current only.Therefore, it is necessary to pull this output high.

CIRCUIT INFORMATION PB RESET

The PB RESET input makes it possible to manually reset a system using either a standard push-button switch or a logic low input. An internal debounce circuit provides glitch immunity when used with a switch, reducing the effects of glitches on the line. The debounce circuit is guaranteed to cause the ADM1232to assert a reset if PB RESET is brought low for more than 20 ms and is guaranteed to ignore low inputs of less than 1 ms.

V Figure 2.Typical Push Button Reset Application

RESET

RESET

PB RESET

Figure 3.PB RESET

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C 3053b –1–12/97

P R I N T E D I N U .S .A .ADM1232

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OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Wide SOIC

(R-16)PLANE

0.0138 (0.35)(1.27)BSC

8-Lead microSOIC

(RM-8)

8-Lead PDIP

(N-8)

PLANE

0.014 (0.356)0.045 (1.15)

(2.54)BSC

0.325 (8.25)

0.008 (0.204)

8-Lead Narrow SOIC

(R-8)

PLANE 0.0138 (0.35)(1.27)BSC °

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