S29GL064N90TAI010中文资料
S29GL-N MirrorBit? Flash Family
S29GL064N, S29GL032N
64 Megabit, 32 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 110 nm MirrorBit Process Technology
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29GL-N_01Revision09Issue Date November16,2007
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V IO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007
Distinctive Characteristics
Architectural Advantages
Single power supply operation
Manufactured on 110 nm MirrorBit process technology
Secured Silicon Sector region
–128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number,
accessible through a command sequence
–Programmed and locked at the factory or by the customer
Flexible sector architecture
–64Mb (uniform sector models): One hundred twenty-eight 32 Kword (64KB) sectors
–64Mb (boot sector models): One hundred twenty-seven 32 Kword (64KB) sectors + eight 4Kword (8KB) boot sectors
–32Mb (uniform sector models): Sixty-four 32Kword (64KB) sectors –32Mb (boot sector models): Sixty-three 32Kword (64KB) sectors + eight 4Kword (8KB) boot sectors
Enhanced VersatileI/O? Control
–All input levels (address, control, and DQ input levels) and outputs are determined by voltage on V IO input. V IO range is 1.65 to V CC
Compatibility with JEDEC standards
–Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection
100,000 erase cycles typical per sector
20-year data retention typical
Performance Characteristics
High performance
–90 ns access time
–8-word/16-byte page read buffer
–25 ns page read time
–16-word/32-byte write buffer which reduces overall programming
time for multiple-word updates Low power consumption
–25 mA typical active read current
–50 mA typical erase/program current
–10 μA typical standby mode current
Package options
–48-pin TSOP
–56-pin TSOP
–64-ball Fortified BGA
–48-ball fine-pitch BGA
Software & Hardware Features
Software features
–Advanced Sector Protection: offers Persistent Sector Protection and Password Sector Protection
–Program Suspend & Resume: read other sectors before
programming operation is completed
–Erase Suspend & Resume: read/program other sectors before an erase operation is completed
–Data# polling & toggle bits provide status
–CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
–Unlock Bypass Program command reduces overall multiple-word
programming time
Hardware features
–WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings on uniform sector models
–Hardware reset input (RESET#) resets device
–Ready/Busy# output (RY/BY#) detects program or erase cycle
completion
S29GL-N MirrorBit? Flash Family
S29GL064N, S29GL032N
64 Megabit, 32 Megabit
3.0 Volt-only Page Mode Flash Memory
Featuring 110 nm MirrorBit Process Technology
Data Sheet
Publication Number S29GL-N_01Revision09Issue Date November16,2007
D a t a S h e e t
General Description
The S29GL-N family of devices are 3.0-Volt single-power Flash memory manufactured using 110nm
MirrorBit technology. The S29GL064N is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes.
The S29GL032N is a 32-Mb device organized as 2,097,152 words or 4,194,304 bytes. Depending on the
model number, the devices have 16-bit wide data bus only, or a 16-bit wide data bus that can also function as
an 8-bit wide data bus by using the BYTE# input. The devices can be programmed either in the host system
or in standard EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a specific operating voltage
range (V CC) as specified in the Product Selector Guide and the Ordering Information–S29GL032N, and
Ordering Information–S29GL064N. Package offerings include 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch
BGA and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0-Volt power supply for both read and write functions. In addition to a
V CC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through
increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during
system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard microprocessor write timing. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
The Advanced Sector Protection features several levels of sector protection, which can disable both the
program and erase operations in certain sectors. Persistent Sector Protection is a method that replaces the
previous 12-volt controlled protection method. Password Sector Protection is a highly sophisticated protection
method that requires a password before changes to certain sectors are permitted.
Device programming and erasure are initiated through command sequences. Once a program or erase
operation begins, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write
cycles to program data instead of four.
Hardware data protection measures include a low V CC detector that automatically inhibits write operations
during power transitions. The hardware sector protection feature disables both program and erase operations
in any combination of sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given
sector to read or program any other sector and then complete the erase operation. The Program Suspend/
Program Resume feature enables the host system to pause a program operation in a given sector to read
any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels on CE#
and RESET#, or when addresses are stable for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin
or WP# pin, depending on model number. The protected sector is still protected even during accelerated
programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently
protected. Once this sector is protected, no further changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
4S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007
D a t a S h e e t
Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.Ordering Information–S29GL032N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.Ordering Information–S29GL064N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.2Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.3Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.4Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.5Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.6RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.7Output Disable Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.8Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.9Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.10Advanced Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.11Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.12Persistent Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.13Persistent Protection Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.14Password Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.15Password and Password Protection Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1664-bit Password. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.17Persistent Protection Bit Lock (PPB Lock Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.18Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.19Write Protect (WP/ACC#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.20Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
https://www.wendangku.net/doc/2411853178.html,mon Flash Memory Interface (CFI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
https://www.wendangku.net/doc/2411853178.html,mand Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.1Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.3Autoselect Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.4Enter/Exit Secured Silicon Sector Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.5Program Suspend/Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.7Sector Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.8Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.9Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.10Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.11DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.12RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.13DQ6: Toggle Bit I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.14DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.15Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.16DQ5: Exceeded Timing Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.17DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.18DQ1: Write-to-Buffer Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 November16,2007S29GL-N_01_09S29GL-N MirrorBit? Flash Family5
D a t a S h e e t
13.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
14.Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.1Key to Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
15.AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
16.Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
17.Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
17.1TS048—48-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 74
17.2TS056—56-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 75
17.3VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package . . . . . . . . . . . . . . 76
17.4LAA064—64-Ball Fortified Ball Grid Array (BGA) 13 x 11 mm Package. . . . . . . . . . . . . . . . 77
18.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007
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Figures
Figure 3.148-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3.256-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3.364-ball Fortified BGA (LAA 064) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3.448-ball Fine-pitch BGA (VBK 048). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5.1S29GL064N Logic Symbol
(Models01,02, V1, V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.2S29GL064N Logic Symbol
(Models03,04). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.3S29GL064N Logic Symbol
(Models06,07, V6, V7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.4S29GL032N Logic Symbol
(Models01,02, V1, V2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.5S29GL032N Logic Symbol
(Models03,04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.1Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 10.2Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10.3Program Suspend/Program Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 10.4Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10.5Data# Polling Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 10.6Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 11.1Maximum Negative Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 11.2Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 14.1Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 14.2Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 15.1V CC Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 15.2Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 15.3Page Read Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 15.4Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 15.5Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 15.6Accelerated Program Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 15.7Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 15.8Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 15.9Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 15.10DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 15.11Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . .72 November16,2007S29GL-N_01_09S29GL-N MirrorBit? Flash Family7
D a t a S h e e t
Tables
Table 6.1S29GL032N Ordering Options (Note4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 7.1S29GL064N Valid Combinations (Note4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8.1Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 8.2S29GL032N (Models 01, 02, V1, V2) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 8.3S29GL032N (Model 03) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 8.4S29GL032N (Model 04) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 8.5S29GL064N (Models 01, 02, V1, V2) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 8.6S29GL064N (Model 03) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 8.7S29GL064N (Model 04) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 8.8S29GL064N (Models 06, 07, V6, V7) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 8.9Autoselect Codes, (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 8.10Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 8.11Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 9.1CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 9.2System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 9.3Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 9.4Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 10.1Command Definitions (x16 Mode, BYTE# = V IH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 10.2Sector Protection Commands (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 10.3Command Definitions (x8 Mode, BYTE# = V IL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 10.4Sector Protection Commands (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 10.5Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 13.1DC Characteristics, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 14.1Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 15.1Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 15.2Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 15.3Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 15.4Alternate CE# Controlled Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 16.1TSOP Pin and BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 8S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007
November 16,2007S29GL-N_01_09
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D a t a S h e e t
1.Product Selector Guide
2.Block Diagram
Note
**A MAX GL064N = A21, GL032N = A20.
Part Number S29GL064N S29GL032N Speed Option V CC = 2.7–3.6 V
V IO = 2.7–3.6 V 90
90
V IO = 1.65–3.6 V
110110Max. Access Time (ns)9011090110Max. CE# Access Time (ns)9011090110Max. Page Access Time (ns)25302530Max. OE# Access Time (ns)
25
30
25
30
Input/Output Buffers
X-Decoder
Y-Decoder Chip Enable Output Enable
Logic
Erase Voltage Generator
PGM Voltage Generator
Timer
V CC Detector
State Control Command Register
V CC V SS
WE#WP#/ACC BYTE#
CE#OE#
STB
STB
DQ15–DQ0 (A-1)
Sector Switches
RY/BY#
RESET#
Data Latch
Y-Gating
Cell Matrix
A d d r e s s L a t c h
A Max **–A0
D a t a S h e e t
3.Connection Diagrams
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package
and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for
prolonged periods of time.
Figure 3.1 48-Pin Standard TSOP
Figure 3.2 56-Pin Standard TSOP
10S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007
D a t a S h e e t
Figure 3.3 64-ball Fortified BGA (LAA 064)
November16,2007S29GL-N_01_09S29GL-N MirrorBit? Flash Family11
D a t a S h e e t
Figure 3.4 48-ball Fine-pitch BGA (VBK 048)
12S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007
D a t a S h e e t
4.Pin Descriptions
Pin Description
A21–A022 Address inputs (S29GL064N)
A20–A021 Address inputs (S29GL032N)
DQ7–DQ08 Data inputs/outputs
DQ14–DQ015 Data inputs/outputs
DQ15/A-1DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode)
CE#Chip Enable input
OE#Output Enable input
WE#Write Enable input
WP#/ACC Hardware Write Protect input/Programming Acceleration input
ACC Acceleration input
WP#Hardware Write Protect input
RESET#Hardware Reset Pin input
RY/BY#Ready/Busy output
BYTE#Selects 8-bit or 16-bit mode
V CC 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances)
V IO Output Buffer Power
V SS Device Ground
NC Pin Not Connected Internally
November16,2007S29GL-N_01_09S29GL-N MirrorBit? Flash Family13
14
S29GL-N MirrorBit ? Flash Family
S29GL-N_01_09November 16,2007
D a t a S h e e t
5.Logic Symbols
Figure 5.1 S29GL064N Logic Symbol
(Models 01,02, V1, V2)
Figure 5.2 S29GL064N Logic Symbol
(Models 03,04)
Figure 5.3 S29GL064N Logic Symbol
(Models 06,07, V6, V7)
Figure 5.4 S29GL032N Logic Symbol
(Models 01,02, V1, V2)
Figure 5.5 S29GL032N Logic Symbol
(Models 03,04)
22
16 or 8
DQ15–DQ0
(A-1)
A21–A0CE# OE#WE#RESET#RY/BY#WP#/ACC V IO BYTE#
22
16 or 8
DQ15–DQ0
(A-1)
A21–A0CE# OE#WE#RESET#RY/BY#WP#/ACC BYTE#
22
16
DQ15–DQ0
A21–A0
CE# OE#WE#RESET#RY/BY#
WP#ACC V IO
21
16 or 8
DQ15–DQ0
(A-1)
A20–A0CE# OE#WE#RESET#RY/BY#WP#/ACC BYTE#
V IO 21
16 or 8
DQ15–DQ0
(A-1)
A20–A0CE# OE#WE#RESET#RY/BY#WP#/ACC BYTE#
November 16,2007S29GL-N_01_09
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D a t a S h e e t
6.Ordering Information–S29GL032N
S29GL032N Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
S29GL032N 90T A I 010
PACKING TYPE 0=
Tray
2= 7-inch Tape and Reel 3 = 13-inch Tape and Reel
MODEL NUMBER
01=x8/x16, V CC = V IO = 2.7 – 3.6V , Uniform sector, WP#/ACC = V IL protects highest addressed sector 02=x8/x16, V CC = V IO = 2.7 – 3.6V , Uniform sector, WP#/ACC = V IL protects lowest addressed sector 03=x8/x16, V CC = 2.7 – 3.6 V , Top boot sector, WP#/ACC = V IL protects top two addressed sectors
04=x8/x16, V CC = 2.7 – 3.6 V , Bottom boot sector, WP#/ACC = V IL protects bottom two addressed sectors V1=x8/x16, V CC = 2.7 – 3.6 V , V IO = 1.65 - 3.6 V , Uniform sector, WP#/ACC = V IL protects highest addressed
sector
V2=x8/x16, V CC = 2.7 – 3.6 V , V IO = 1.65 - 3.6 V , Uniform sector, WP#/ACC = V IL protects lowest addressed sector TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)PACKAGE MATERIAL SET A = Standard (Note 4)F = Pb-Free
PACKAGE TYPE
T =Thin Small Outline Package (TSOP) Standard Pinout B =Fine-pitch Ball-Grid Array Package F =Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations (90 = 90ns, 11 = 110ns)
DEVICE NUMBER/DESCRIPTION S29GL032N
32 Megabit Page-Mode Flash Memory
Manufactured using 110nm MirrorBit ? Process Technology, 3.0 Volt-only Read, Program, and Erase
Table 6.1 S29GL032N Ordering Options (Note 4)
S29GL032N Valid Combinations
Package Description
(Notes)
Device Number
Speed Option Package, Material,& Temperature Range
Model Number Packing Type
S29GL032N
90TFI
01, 020,2,3(Note 1)TS056 (Note 2)
TSOP
11V1, V290
FFI 01, 02LAA064 (Note 3)Fortified BGA 11
V1, V2
90TFI
03, 04
TS048 (Note 2)TSOP
BFI VBK048 (Note 3)Fine-Pitch BGA FFI
LAA064 (Note 3)
Fortified BGA
Notes 1.Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.2.TSOP package marking omits packing type designator from ordering
part number.
3.BGA package marking omits leading S29 and packing type designator
from ordering part number.4.Contact local sales for availability for Leaded lead-frame parts.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this
device. Consult your local sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
16
S29GL-N MirrorBit ? Flash Family
S29GL-N_01_09November 16,2007
D a t a S h e e t
7.Ordering Information–S29GL064N
S29GL064N Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
8.Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to
S29GL064N 90T A I 022
PACKING TYPE 0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
MODEL NUMBER
01=x8/x16, V CC = V IO = 2.7 – 3.6 V , Uniform sector, WP#/ACC = V IL protects highest addressed sector 02=x8/x16, V CC = V IO = 2.7 – 3.6 V , Uniform sector, WP#/ACC = V IL protects lowest addressed sector 03=x8/x16, V CC = 2.7 – 3.6 V , Top boot sector, WP#/ACC = V IL protects top two addressed sectors
04=x8/x16, V CC = 2.7 – 3.6 V , Bottom boot sector, WP#/ACC = V IL protects bottom two addressed sectors 06=x16, V CC = 2.7 – 3.6 V , Uniform sector, WP# = V IL protects highest addressed sector 07=x16, V CC = 2.7 – 3.6 V , Uniform sector, WP# = V IL protects lowest addressed sector
V1=x8/x16, V CC = 2.7 – 3.6 V , V IO = 1.65 - 3.6 V, Uniform sector, WP#/ACC = V IL protects highest addressed sector V2=x8/x16, V CC = 2.7 – 3.6 V , V IO = 1.65 - 3.6 V, Uniform sector, WP#/ACC = V IL protects lowest addressed sector V6=x16, V CC = 2.7 – 3.6 V , V IO = 1.65 - 3.6 V , Uniform sector, WP# = V IL protects highest addressed sector V7=x16, V CC = 2.7 – 3.6 V , V IO = 1.65 - 3.6 V , Uniform sector, WP# = V IL protects lowest addressed sector TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)PACKAGE MATERIAL SET A = Standard (Note 4)F = Pb-Free
PACKAGE TYPE
T =Thin Small Outline Package (TSOP) Standard Pinout B =Fine-pitch Ball-Grid Array Package F =Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations (90 = 90ns, 11 = 110ns)
DEVICE NUMBER/DESCRIPTION
S29GL064N, 64 Megabit Page-Mode Flash Memory
Manufactured using 110 nm MirrorBit ? Process Technology, 3.0 Volt-only Read, Program, and Erase
Table 7.1 S29GL064N Valid Combinations (Note 4)
S29GL064N Valid Combinations
Package Description
Device Number
Speed Option
Package, Material &Temperature Range
Model Number Packing Type
S29GL064N
90TFI
03, 04, 06, 07
0, 2, 3(Note 1)TS048 (Note 2)TSOP
11V6, V790
01, 02TS056 (Note 2)TSOP
11V1, V290BFI 03, 04VBK048 (Note 3)Fine-pitch BGA 90FFI 01, 02, 03, 04
LAA064 (Note 3)
Fortified BGA
11
V1, V2
Notes
1.Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be
packed in Types 0, 2, or 3.2.TSOP package marking omits packing type designator from ordering part number.
3.BGA package marking omits leading S29 and packing type designator from ordering part number.
4.Contact local sales for availability for Leaded lead-frame parts.
Valid Combinations
Valid Combinations list configurations
planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
November 16,2007S29GL-N_01_09
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D a t a S h e e t
execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 8.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Legend
L = Logic Low = V IL H = Logic High = V IH V ID = 11.5–12.5 V V HH = 11.5–12.5 V X = Don’t Care
SA = Sector Address A IN = Address In D IN = Data In D OUT = Data Out
Notes
1.If WP# = V IL , the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot sector devices). If WP#
= VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method described in Write Protect (WP#). All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)2.D IN or D OUT as required by command sequence, data polling, or sector protect algorithm (see Figure 10.5 on page 56).
8.1Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
8.2Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V IL . CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH .
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
See Reading Array Data on page 41 for more information. Refer to the AC Read-Only Operations table for timing specifications and the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data.
Table 8.1 Device Bus Operations
Operation
CE#OE#WE#RESET#
WP#ACC Addresses
DQ0–DQ7DQ8–DQ15
BYTE#= V IH BYTE# = V IL Read
L L H H X X A IN D OUT D OUT DQ8–DQ14= High-Z, DQ15 = A-1Write (Program/Erase)L H L H (Note 1)X A IN (Note 2)(Note 2)Accelerated Program L H L H (Note 1)V HH A IN (Note 2)(Note 2)Standby V CC ± 0.3V
X X V CC ± 0.3V
X H X High-Z High-Z High-Z Output Disable L H H H X X X High-Z High-Z High-Z Reset
X
X
X
L
X
X
X
High-Z
High-Z
High-Z
D a t a S h e e t
8.2.1Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)–A3.
Address bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word within a page. This is
an asynchronous operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to t ACC or t CE and subsequent page read accesses (as long as the
locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is
deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode
accesses are obtained by keeping the read-page addresses constant and changing the intra-read page
addresses.
8.3Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to V IL, and OE# to V IH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The Word
Program Command Sequence on page42 contains details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Tables 8.2 – 8.8 indicate the
address space that each sector occupies.
Refer to the DC Characteristics table for the active current specification for the write mode. The AC
Characteristics section contains timing specification tables and timing diagrams for write operations.
8.3.1Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms.
8.3.2Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts V HH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the
time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V HH from the WP#/ACC or ACC pin, depending on model
number, returns the device to normal operation. Note that the WP#/ACC or ACC pin must not be at V HH for
operations other than accelerated programming, or device damage may result. WP# contains an internal
pullup; when unconnected, WP# is at V IH.
8.3.3Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–
DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page29 and Autoselect
Command Sequence on page42 for more information.
18S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007
D a t a S h e e t
8.4Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V.
(Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within
V IO ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
standard access time (t CE) for read access when the device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Refer to the DC Characteristics on page62 for the standby current specification.
8.5Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t ACC + 30ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC
Characteristics on page62 for the automatic sleep mode current specification.
8.6RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in
progress, Hi-Z all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device
draws CMOS standby current (I CC5). If RESET# is held at V IL but not within V SS±0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure15.4 on page66 for the timing
diagram.
8.7Output Disable Mode
When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high
impedance state.
November16,2007S29GL-N_01_09S29GL-N MirrorBit? Flash Family19
D a t a S h e e t
Table 8.2 S29GL032N (Models 01, 02, V1, V2) Sector Addresses
Sector A20-A15
Sector
Size
(KB/
Kwords)
8-bit
Address
Range
16-bit
Address
Range Sector A20-A15
Sector
Size
(KB/
Kwords)
8-bit
Address
Range
16-bit
Address
Range
SA000000064/32000000h–00FFFFh000000h–007FFFh SA3210000064/32200000h–20FFFFh100000h–107FFFh SA100000164/32010000h–01FFFFh008000h–00FFFFh SA3310000164/32210000h–21FFFFh108000h–10FFFFh SA200001064/32020000h–02FFFFh010000h–017FFFh SA3410001064/32220000h–22FFFFh110000h–117FFFh SA300001164/32030000h–03FFFFh018000h–01FFFFh SA3510001164/32230000h–23FFFFh118000h–11FFFFh SA400010064/32040000h–04FFFFh020000h–027FFFh SA3610010064/32240000h–24FFFFh120000h–127FFFh SA500010164/32050000h–05FFFFh028000h–02FFFFh SA3710010164/32250000h–25FFFFh128000h–12FFFFh SA600011064/32060000h–06FFFFh030000h–037FFFh SA3810011064/32260000h–26FFFFh130000h–137FFFh SA700011164/32070000h–07FFFFh038000h–03FFFFh SA3910011164/32270000h–27FFFFh138000h–13FFFFh SA800100064/32080000h–08FFFFh040000h–047FFFh SA4010100064/32280000h–28FFFFh140000h–147FFFh SA900100164/32090000h–09FFFFh048000h–04FFFFh SA4110100164/32290000h–29FFFFh148000h–14FFFFh SA1000101064/320A0000h–0AFFFFh050000h–057FFFh SA4210101064/322A0000h–2AFFFFh150000h–157FFFh SA1100101164/320B0000h–0BFFFFh058000h–05FFFFh SA4310101164/322B0000h–2BFFFFh158000h–15FFFFh SA1200110064/320C0000h–0CFFFFh060000h–067FFFh SA4410110064/322C0000h–2CFFFFh160000h–167FFFh SA1300110164/320D0000h–0DFFFFh068000h–06FFFFh SA4510110164/322D0000h–2DFFFFh168000h–16FFFFh SA1400111064/320E0000h–0EFFFFh070000h–077FFFh SA4610111064/322E0000h–2EFFFFh170000h–177FFFh SA1500111164/320F0000h–0FFFFFh078000h–07FFFFh SA4710111164/322F0000h–2FFFFFh178000h–17FFFFh SA1601000064/32100000h–10FFFFh080000h–087FFFh SA4811000064/32300000h–30FFFFh180000h–187FFFh SA1701000164/32110000h–11FFFFh088000h–08FFFFh SA4911000164/32310000h–31FFFFh188000h–18FFFFh SA1801001064/32120000h–12FFFFh090000h–097FFFh SA5011001064/32320000h–32FFFFh190000h–197FFFh SA1901001164/32130000h–13FFFFh098000h–09FFFFh SA5111001164/32330000h–33FFFFh198000h–19FFFFh SA2001010064/32140000h–14FFFFh0A0000h–0A7FFFh SA5211010064/32340000h–34FFFFh1A0000h–1A7FFFh SA2101010164/32150000h–15FFFFh0A8000h–0AFFFFh SA5311010164/32350000h–35FFFFh1A8000h–1AFFFFh SA2201011064/32160000h–16FFFFh0B0000h–0B7FFFh SA5411011064/32360000h–36FFFFh1B0000h–1B7FFFh SA2301011164/32170000h–17FFFFh0B8000h–0BFFFFh SA5511011164/32370000h–37FFFFh1B8000h–1BFFFFh SA2401100064/32180000h–18FFFFh0C0000h–0C7FFFh SA5611100064/32380000h–38FFFFh1C0000h–1C7FFFh SA2501100164/32190000h–19FFFFh0C8000h–0CFFFFh SA5711100164/32390000h–39FFFFh1C8000h–1CFFFFh SA2601101064/321A0000h–1AFFFFh0D0000h–0D7FFFh SA5811101064/323A0000h–3AFFFFh1D0000h–1D7FFFh SA2701101164/321B0000h–1BFFFFh0D8000h–0DFFFFh SA5911101164/323B0000h–3BFFFFh1D8000h–1DFFFFh SA2801110064/321C0000h–1CFFFFh0E0000h–0E7FFFh SA6011110064/323C0000h–3CFFFFh1E0000h–1E7FFFh SA2901110164/321D0000h–1DFFFFh0E8000h–0EFFFFh SA6111110164/323D0000h–3DFFFFh1E8000h–1EFFFFh SA3001111064/321E0000h–1EFFFFh0F0000h–0F7FFFh SA6211111064/323E0000h–3EFFFFh1F0000h–1F7FFFh SA3101111164/321F0000h–1FFFFFh0F8000h–0FFFFFh SA6311111164/323F0000h–3FFFFFh1F8000h–1FFFFFh
20S29GL-N MirrorBit? Flash Family S29GL-N_01_09November16,2007