AD7914BRU-REEL7中文资料
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/https://www.wendangku.net/doc/2c17841186.html, Fax: 781/326-8703? Analog Devices, Inc., 2002
REV.0
AD7904/AD7914/AD7924 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP
FUNCTIONAL BLOCK DIAGRAM
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V IN3
SCLK
DOUT
DIN
CS
V DRIVE REF IN
V IN0
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V DD of 2.7V to 5.25V
Low Power:
6 mW max at 1 MSPS with 3 V Supplies
13.5 mW max at 1 MSPS with 5 V Supplies
4 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:
AD7924, 70 dB SNR at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface SPI TM/QSPI TM/
MICROWIRE TM/DSP Compatible
Shutdown Mode: 0.5 ?A Max
16-Lead TSSOP Package
GENERAL DESCRIPTION
The AD7904/AD7914/AD7924 are respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 4-channel, successive-approxi-mation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track/hold amplifier that
can handle input frequencies in excess of 8 MHz.
The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. There are no pipeline delays associated with the part.
The AD7904/AD7914/AD7924 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7904/AD7914/AD7924 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 2.7 mA maximum.
Through the configuration of the Control Register, the analog input range for the part can be selected as 0 V to REF IN or 0 V to 2 × REF IN, with either straight binary or twos complement output coding. The AD7904/AD7914/AD7924 each feature four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time for the AD7904/AD7914/AD7924 is deter-mined by the SCLK frequency, as this is also used as the master clock to control the conversion.PRODUCT HIGHLIGHTS
1.High Throughput with Low Power Consumption.
The AD7904/AD7914/AD7924 offer up to 1 MSPS through-put rates. At the maximum throughput rate with 3 V sup`plies, the AD7904/AD7914/AD7924 dissipate just 6 mW of
power maximum.
2.Four Single-Ended Inputs with a Channel Sequencer.
A consecutive sequence of channels can be selected, through which the ADC will cycle and convert on.
3.Single-Supply Operation with V DRIVE Function.
The AD7904/AD7914/AD7924 operate from a single 2.7 V to 5.25 V supply. The V DRIVE function allows the serial inter-face to connect directly to either 3 V or 5 V processor systems independent of V DD.
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 μA max when in full shutdown.
5. No Pipeline Delay.
The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD7904–SPECIFICATIONS
(AV DD = V DRIVE = 2.7V to 5.25V, REF IN = 2.5V, f SCLK = 20MHz, T A = T MIN to T MAX,
unless otherwise noted.)
Parameter B Version1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f IN = 50 kHz Sine Wave, f SCLK = 20 MHz
Signal-to-Noise + Distortion (SINAD)249dB min
Signal-to-Noise Ratio (SNR)249dB min
Total Harmonic Distortion (THD)2–66dB max
Peak Harmonic or Spurious Noise
(SFDR)2–64dB max
Intermodulation Distortion (IMD)2fa = 40.1 kHz, fb = 41.5 kHz
Second Order Terms–90dB typ
Third Order Terms–90dB typ
Aperture Delay10ns typ
Aperture Jitter50ps typ
Channel-to-Channel Isolation2–85dB typ f IN = 400 kHz
Full Power Bandwidth8.2MHz typ @ 3 dB
1.6MHz typ @ 0.1 dB
DC ACCURACY2
Resolution8Bits
Integral Nonlinearity±0.2LSB max
Differential Nonlinearity±0.2LSB max Guaranteed No Missed Codes to 8 Bits
0 V to REF IN Input Range Straight Binary Output Coding
Offset Error±0.5LSB max
Offset Error Match±0.05LSB max
Gain Error±0.2LSB max
Gain Error Match±0.05LSB max
0 V to 2 × REF IN Input Range–REF IN to +REF IN Biased about REF IN with
Positive Gain Error±0.2LSB max Twos Complement Output Coding
Positive Gain Error Match±0.05LSB max
Zero Code Error±0.5LSB max
Zero Code Error Match±0.1LSB max
Negative Gain Error±0.2LSB max
Negative Gain Error Match±0.05LSB max
ANALOG INPUT
Input Voltage Range0 to REF IN V RANGE Bit Set to 1
0 to 2 × REF IN V RANGE Bit Set to 0, V DD/V DRIVE = 4.75 V to 5.25 V DC Leakage Current±1μA max
Input Capacitance20pF typ
REFERENCE INPUT
REF IN Input Voltage 2.5V±1% Specified Performance
DC Leakage Current±1μA max
REF IN Input Impedance36k? typ f SAMPLE = 1 MSPS
LOGIC INPUTS
Input High Voltage, V INH0.7 × V DRIVE V min
Input Low Voltage, V INL0.3 × V DRIVE V max
Input Current, I IN±1μA max Typically 10 nA, V IN = 0 V or V DRIVE
Input Capacitance, C IN310pF max
LOGIC OUTPUTS
Output High Voltage, V OH V DRIVE – 0.2V min I SOURCE = 200 μA, V DD = 2.7 V to 5.25 V
Output Low Voltage, V OL0.4V max I SINK = 200 μA
Floating-State Leakage Current±1μA max
Floating-State Output Capacitance310pF max
Output Coding Straight (Natural) Binary Coding Bit Set to 1
Twos Complement Coding Bit Set to 0
CONVERSION RATE
Conversion Time800ns max16 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time300ns max Sine Wave Input
300ns max Full-Scale Step Input
Throughput Rate1MSPS max See Serial Interface Section
–2–REV. 0
AD7904/AD7914/AD7924
–3–
REV. 0Parameter
B Version 1Unit Test Conditions/Comments
POWER REQUIREMENTS V DD 2.7/5.25V min/max V DRIVE 2.7/5.25V min/max I DD 4
Digital I/Ps = 0 V or V DRIVE
Normal Mode (Static)
600μA typ V DD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational)
2.7mA max V DD = 4.75 V to 5.25 V, f SCLK = 20 MHz 2mA max V DD = 2.7 V to
3.6 V, f SCLK = 20 MHz Using Auto Shutdown Mode 960μA typ f SAMPLE = 250 kSPS 0.5μA max (Static)
Full Shutdown Mode 0.5μA max SCLK On or Off (20 nA typ)Power Dissipation 4
Normal Mode (Operational)13.5mW max V DD = 5 V, f SCLK = 20 MHz 6mW max V DD = 3 V, f SCLK = 20 MHz Auto Shutdown Mode (Static) 2.5μW max V DD = 5 V 1.5μW max V DD = 3 V Full Shutdown Mode
2.5μW max V DD = 5 V 1.5
μW max
V DD = 3 V
NOTES 1
Temperature ranges as follows: B Version: –40°C to +85°C.2
See Terminology section.3
Sample tested @ 25°C to ensure compliance.4
See Power Versus Throughput Rate section.Specifications subject to change without notice.
–4–
REV. 0
Parameter
B Version 1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
f IN = 50 kHz Sine Wave, f SCLK = 20 MHz
Signal-to-Noise + Distortion (SINAD)261dB min Signal-to-Noise Ratio (SNR)2
61dB min Total Harmonic Distortion (THD)2–72dB max Peak Harmonic or Spurious Noise (SFDR)2
–74dB max
Intermodulation Distortion (IMD)2fa = 40.1 kHz, fb = 41.5 kHz
Second Order Terms –90dB typ Third Order Terms –90dB typ Aperture Delay 10ns typ Aperture Jitter
50ps typ Channel-to-Channel Isolation 2–85dB typ f IN = 400 kHz Full Power Bandwidth 8.2MHz typ @ 3 dB 1.6MHz typ
@ 0.1 dB
DC ACCURACY 2Resolution
10Bits
Integral Nonlinearity ±0.5LSB max Differential Nonlinearity ±0.5LSB max Guaranteed No Missed Codes to 10 Bits 0 V to REF IN Input Range Straight Binary Output Coding
Offset Error
±2LSB
max
Offset Error Match ±0.2LSB max Gain Error
±0.5LSB max Gain Error Match
±0.2LSB max
0 V to 2 × REF IN Input Range –REF IN to +REF IN Biased about REF IN with Positive Gain Error
±0.5LSB max Twos Complement Output Coding Positive Gain Error Match ±0.2LSB max Zero Code Error
±2LSB max Zero Code Error Match ±0.2LSB max Negative Gain Error
±0.5LSB max Negative Gain Error Match ±0.2
LSB max ANALOG INPUT Input Voltage Range 0 to REF IN
V RANGE Bit Set to 1
0 to 2 × REF IN V
RANGE Bit Set to 0, V DD /V DRIVE = 4.75 V to 5.25 V
DC Leakage Current ±1μA max Input Capacitance 20pF typ REFERENCE INPUT REF IN Input Voltage 2.5V
±1% Specified Performance DC Leakage Current ±1μA max REF IN Input Impedance 36
k ? typ f SAMPLE = 1 MSPS
LOGIC INPUTS
Input High Voltage, V INH 0.7 × V DRIVE V min Input Low Voltage, V INL 0.3 × V DRIVE V max Input Current, I IN
±1μA max Typically 10 nA, V IN = 0 V or V DRIVE
Input Capacitance, C IN 3
10
pF max
LOGIC OUTPUTS
Output High Voltage, V OH V DRIVE – 0.2V min I SOURCE = 200 μA, V DD = 2.7 V to 5.25 V Output Low Voltage, V OL
0.4V max I SINK = 200 μA Floating-State Leakage Current ±1μA max Floating-State Output Capacitance 310pF max Output Coding
Straight (Natural) Binary Coding Bit Set to 1Twos Complement Coding Bit Set to 0
CONVERSION RATE Conversion Time
800ns max 16 SCLK Cycles with SCLK at 20 MHz Track/Hold Acquisition Time 300ns max Sine Wave Input 300ns max Full-Scale Step Input
Throughput Rate
1
MSPS max
See Serial Interface Section
(AV DD = V DRIVE = 2.7V to 5.25V, REF IN = 2.5V, f SCLK = 20MHz, T A = T MIN to T MAX ,unless otherwise noted.)
AD7914–SPECIFICATIONS
AD7904/AD7914/AD7924
–5–
REV. 0Parameter
B Version 1Unit Test Conditions/Comments
POWER REQUIREMENTS V DD 2.7/5.25V min/max V DRIVE 2.7/5.25V min/max I DD 4
Digital I/Ps = 0 V or V DRIVE
Normal Mode (Static)
600 μA typ V DD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational)
2.7mA max V DD = 4.75 V to 5.25 V, f SCLK = 20 MHz 2mA max V DD = 2.7 V to
3.6 V, f SCLK = 20 MHz Using Auto Shutdown Mode 960μA typ f SAMPLE = 250 kSPS 0.5μA max (Static)
Full Shutdown Mode 0.5μA max SCLK On or Off (20 nA typ)Power Dissipation 4
Normal Mode (Operational)13.5mW max V DD = 5 V, f SCLK = 20 MHz 6mW max V DD = 3 V, f SCLK = 20 MHz Auto Shutdown Mode (Static) 2.5μW max V DD = 5 V 1.5μW max V DD = 3 V Full Shutdown Mode
2.5μW max V DD = 5 V 1.5
μW max
V DD = 3 V
NOTES 1
Temperature ranges as follows: B Version: –40°C to +85°C.2
See Terminology section.3
Sample tested @ 25°C to ensure compliance.4
See Power Versus Throughput Rate section.Specifications subject to change without notice.
AD7924–SPECIFICATIONS
(AV DD = V DRIVE = 2.7V to 5.25V, REF IN = 2.5V, f SCLK = 20MHz, T A = T MIN to T MAX,
unless otherwise noted.)
Parameter B Version1Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f IN = 50 kHz Sine Wave, f SCLK = 20 MHz Signal to Noise + Distortion (SINAD)270dB min@ 5 V
69dB min@ 3 V Typically 69.5 dB
Signal to Noise Ratio (SNR)270dB min
Total Harmonic Distortion (THD)2–77dB max@ 5 V Typically –84 dB
–73dB max@ 3 V Typically –77 dB
Peak Harmonic or Spurious Noise–78dB max@ 5 V Typically –86 dB
(SFDR)2–76dB max@ 3 V Typically –80 dB
Intermodulation Distortion (IMD)2fa = 40.1 kHz, fb = 41.5 kHz
Second Order Terms–90dB typ
Third Order Terms–90dB typ
Aperture Delay10ns typ
Aperture Jitter50ps typ
Channel-to-Channel Isolation2–85dB typ f IN = 400 kHz
Full Power Bandwidth8.2MHz typ@ 3 dB
1.6MHz typ@ 0.1 dB
DC ACCURACY2
Resolution12Bits
Integral Nonlinearity±1LSB max
Differential Nonlinearity–0.9/+1.5LSB max Guaranteed No Missed Codes to 12 Bits
0 V to REF IN Input Range Straight Binary Output Coding
Offset Error±8LSB max Typically ±0.5 LSB
Offset Error Match±0.5LSB max
Gain Error±1.5LSB max
Gain Error Match±0.5LSB max
0 V to 2 × REF IN Input Range–REF IN to +REF IN Biased about REF IN with
Positive Gain Error±1.5LSB max Twos Complement Output Coding
Positive Gain Error Match±0.5LSB max
Zero Code Error±8LSB max Typically ±0.8 LSB
Zero Code Error Match±0.5LSB max
Negative Gain Error±1LSB max
Negative Gain Error Match±0.5LSB max
ANALOG INPUT
Input Voltage Range0 to REF IN V RANGE Bit Set to 1
0 to 2 × REF IN V RANGE Bit Set to 0, V DD/V DRIVE = 4.75 V to 5.25 V DC Leakage Current±1μA max
Input Capacitance20pF typ
REFERENCE INPUT
REF IN Input Voltage 2.5V±1% Specified Performance
DC Leakage Current±1μA max
REF IN Input Impedance36k? typ f SAMPLE = 1 MSPS
LOGIC INPUTS
Input High Voltage, V INH0.7 × V DRIVE V min
Input Low Voltage, V INL0.3 × V DRIVE V max
Input Current, I IN±1μA max Typically 10 nA, V IN = 0 V or V DRIVE
Input Capacitance, C IN310pF max
LOGIC OUTPUTS
Output High Voltage, V OH V DRIVE – 0.2V min I SOURCE = 200 μA, V DD = 2.7 V to 5.25 V Output Low Voltage, V OL0.4V max I SINK = 200 μA
Floating-State Leakage Current±1μA max
Floating-State Output Capacitance310pF max
Output Coding Straight (Natural) Binary Coding Bit Set to 1
Twos Complement Coding Bit Set to 0
–6–REV. 0
AD7904/AD7914/AD7924
–7–
REV. 0Parameter
B Version 1Unit Test Conditions/Comments
CONVERSION RATE Conversion Time
800ns max 16 SCLK Cycles with SCLK at 20 MHz Track/Hold Acquisition Time 300ns max Sine Wave Input 300ns max Full-Scale Step Input
Throughput Rate
1MSPS max See Serial Interface Section
POWER REQUIREMENTS V DD 2.7/5.25V min/max V DRIVE 2.7/5.25V min/max I DD 4
Digital I/Ps = 0 V or V DRIVE
Normal Mode(Static)
600μA typ V DD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational)
2.7mA max V DD = 4.75 V to 5.25 V, f SCLK = 20 MHz 2mA max V DD = 2.7 V to
3.6 V, f SCLK = 20 MHz Using Auto Shutdown Mode 960μA typ f SAMPLE = 250 kSPS 0.5μA max (Static)
Full Shutdown Mode 0.5μA max SCLK On or Off (20 nA typ)Power Dissipation 4
Normal Mode (Operational)13.5mW max V DD = 5 V, f SCLK = 20 MHz 6mW max V DD = 3 V, f SCLK = 20 MHz Auto Shutdown Mode (Static) 2.5μW max V DD = 5 V 1.5μW max V DD = 3 V Full Shutdown Mode
2.5μW max V DD = 5 V 1.5
μW max
V DD = 3 V
NOTES 1
Temperature ranges as follows: B Versions: –40°C to +85°C.2
See Terminology section.3
Sample tested @ 25°C to ensure compliance.4
See Power Versus Throughput Rate section.Specifications subject to change without notice.
–8–AD7904/AD7914/AD7924REV. 0
TIMING SPECIFICATIONS 1
(V DD = 2.7 V to 5.25 V, V DRIVE ? V DD , REF IN = 2.5 V, T A = T MIN to T MAX , unless otherwise noted.)
Limit at T MIN , T MAX AD7904/AD7914/AD7924Parameter V DD = 3 V V DD = 5 V Unit
Description
f SCLK 21010
kHz min 20
20
MHz max t CONVERT 16 × t SCLK 16 × t SCLK t QUIET 5050ns min Minimum Quiet Time Required Between CS Rising Edge and Start of Next Conversion t 21010ns min CS to SCLK Setup Time
t 333530ns max Delay from CS until DOUT Three-State Disabled t 4340
40
ns max Data Access Time after SCLK Falling Edge t 50.4 × t SCLK 0.4 × t SCLK ns min SCLK Low Pulsewidth t 60.4 × t SCLK 0.4 × t SCLK ns min SCLK High Pulsewidth
t 71010ns min SCLK to DOUT Valid Hold Time
t 8415/4515/35ns min/max SCLK Falling Edge to DOUT High Impedance t 91010ns min DIN Setup Time Prior to SCLK Falling Edge t 1055ns min DIN Hold Time after SCLK Falling Edge t 112020ns min Sixteenth SCLK Falling Edge to CS High t 12
1
1
μs max
Power-Up Time from Full Power-Down/Auto Shutdown Modes
NOTES 1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD ) and timed from a voltage level of 1.6 V.See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 × V DRIVE .4
t 8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.Specifications subject to change without notice.
AD7904/AD7914/AD7924
–9–
REV. 0ABSOLUTE MAXIMUM RATINGS 1
(T A = 25°C unless otherwise noted.)
AV DD to AGND ............................................... –0.3 V to +7 V V DRIVE to AGND................................ –0.3 V to AV DD + 0.3 V Analog Input Voltage to AGND ......... –0.3 V to AV DD + 0.3 V Digital Input Voltage to AGND........................ –0.3 V to +7 V Digital Output Voltage to AGND........... –0.3 V to AV DD + 0.3 V REF IN to AGND................................ –0.3 V to AV DD + 0.3 V Input Current to Any Pin Except Supplies 2................. ±10 mA Operating Temperature Range
Commercial (B Version)............................. –40°C to +85°C Storage Temperature Range...................... –65°C to +150°C Junction Temperature ................................................... 150°C
Figure 1.Load Circuit for Digital Output Timing Specifications
ORDERING GUIDE
Temperature Linearity Package Package Model
Range
Error (LSB)1Option Description AD7904BRU –40°C to +85°C ±0.2RU-16TSSOP AD7914BRU –40°C to +85°C ±0.5RU-16TSSOP AD7924BRU
–40°C to +85°C ±1
RU-16
TSSOP
EVAL-AD79x4CB 2
Evaluation Board EVAL-CONTROL BRD23
Controller Board
NOTES 1
Linearity error here refers to integral linearity error.2
This can be used as a stand alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.The board comes with one chip of each the AD7904, AD7914, and AD7924.3
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit you will need to order the particular ADC evaluation board, e.g., EVAL-AD79x4CB, the EVAL-CONTROL BRD2,and a 12 V ac transformer. See relevant Evaluation Board Technical Note for more information.
TSSOP Package, Power Dissipation ........................... 450 mW θJA Thermal Impedance......................... 150.4°C/W (TSSOP)θJC Thermal Impedance........................... 27.6°C/W (TSSOP)Lead Temperature, Soldering
Vapor Phase (60 secs)................................................ 215°C Infrared (15 secs)....................................................... 220°C ESD................................................................................. 2 kV
NOTES 1
Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2
Transient currents of up to 100 mA will not cause SCR latch up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7904/AD7914/AD7924 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–10–AD7904/AD7914/AD7924
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No.Mnemonic Function
1SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7904/AD7914/AD7924’s conversion process.2DIN Data In. Logic Input. Data to be written to the AD7904/AD7914/AD7924’s Control Register is
provided on this input and is clocked into the register on the falling edge of SCLK (see Control Register section).3
CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7904/AD7914/AD7924 and also frames the serial data transfer.
4, 8, 13, 16
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7904/AD7914/AD7924. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
5, 6AV DD Analog Power Supply Input. The AV DD range for the AD7904/AD7914/AD7924 is from 2.7 V to 5.25 V.For the 0 V to 2 × REF IN range, AV DD should be from 4.75 V to 5.25 V.
7REF IN Reference Input for the AD7904/AD7914/AD7924. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ±1% for specified performance.
12–9
V IN 0–V IN 3
Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on-chip track/hold. The analog input channel to be converted is selected by using the address bits ADD1 and ADD0 of the control register. The address bits, in conjunction with the SEQ1 and SEQ0 bits, allow the Sequencer to be programmed. The input range for all input channels can extend from 0 V to REF IN or 0 V to 2 × REF IN as selected via the RANGE bit in the control register. Any unused input channels should be connected to AGND to avoid noise pickup.
14DOUT
Data Out. Logic Output. The conversion result from the AD7904/AD7914/AD7924 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input.The data stream from the AD7904 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four
trailing zeros, provided MSB first; the data stream from the AD7914 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7924consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data provided MSB first. The output coding may be selected as straight binary or twos complement via the CODING bit in the control register.
15V DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines what voltage the serial interface of the AD7904/AD7914/AD7924 will operate at.
PIN CONFIGURATION
16-Lead TSSOP
SCLK DIN V DRIVE CS AGND AV DD V IN 0
AV DD V IN 1
REF IN V IN 2AGND V IN 3
AD7904/AD7914/AD7924
–11–
REV. 0TERMINOLOGY Integral Nonlinearity
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end-points of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., REF IN – 1 LSB) after the offset error has been adjusted out.
Gain Error Match
This is the difference in Gain error between any two channels.
Zero Code Error
This applies when using the twos complement output coding option, in particular to the 2 × REF IN input range with –REF IN to +REF IN biased about the REF IN point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal V IN volt-age, i.e., REF IN – 1 LSB.
Zero Code Error Match
This is the difference in Zero Code Error between any two channels.
Positive Gain Error
This applies when using the twos complement output coding option, in particular to the 2 × REF IN input range with –REF IN to +REF IN biased about the REF IN point. It is the deviation of the last code transition (011. . .110) to (011 . . . 111) from the ideal (i.e., +REF IN – 1 LSB) after the Zero Code Error has been adjusted out.
Positive Gain Error Match
This is the difference in Positive Gain Error between any two channels.
Negative Gain Error
This applies when using the twos complement output coding option, in particular to the 2 × REF IN input range with –REF IN to +REF IN biased about the REF IN point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., –REF IN + 1 LSB) after the Zero Code Error has been adjusted out.
Negative Gain Error Match
This is the difference in Negative Gain Error between any two channels.
Channel-to-Channel Isolation
Channel-to-Channel Isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 400 kHz sine wave signal to all three nonselected input channels and deter-mining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all four channels for the AD7904/AD7914/AD7924.
PSR (Power Supply Rejection)
Variations in power supply will affect the full scale transition,but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value. See Typical Performance Curves.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode at the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±1 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental.Noise is the sum of all nonfundamental sig-nals up to half the sampling frequency (f S /2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza-tion noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:
Signal to Noise Distortion N dB ()(..)+=+602176Thus for a 12-bit converter, this is 74dB, for a 10-bit converter
this is 62 dB, and for an 8-bit converter this is 50 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7904/AD7914/AD7924, it is defined as:
THD dB V V V V V V ()log
=++++202232425262
1
where V 1 is the rms amplitude of the fundamental and V 2, V 3,
V 4, V 5, and V 6 are the rms amplitudes of the second through the sixth harmonics.
–12–AD7904/AD7914/AD7924–Typical Performance Characteristics
REV. 0
PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7924 at 1MSPS sample rate and 50 kHz input frequency. TPC 2 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz.
TPC 3 shows the power supply rejection ratio versus supply ripple frequency for the AD7924 when no decoupling is used.The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AV DD supply of frequency f S :
PSRR dB Pf Pfs ()log(/)=10Pf is equal to the power at frequency f in ADC output; Pf S is
equal to the power at frequency f S coupled onto the ADC AV DD supply. Here a 200 mV p-p sine wave is coupled onto the AV DD supply.
TPC 4 shows a graph of total harmonic distortion versus analog input frequency for various supply voltages, while TPC 5 shows a graph of total harmonic distortion versus analog input frequency for various source impedances. See the Analog Input section.TPC 6 and TPC 7 show typical INL and DNL plots for the AD7924.
FREQUENCY – kHz
0100200300400500
S N R – d B
50150
2503504504096 POINT FFT V DD = 5V
f SAMPLE = 1MSPS f IN = 50kHz
SINAD = 71.147THD = –87.229SFDR = –90.744
TPC 1.AD7924 Dynamic Performance at 1 MSPS
INPUT FREQUENCY – kHz
75
10
1000
S I N A D – d B
70
65
60
55100
TPC 2.AD7924 SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS
SUPPL Y RIPPLE FREQUENCY – kHz
00
1000
P S R R –
d B
–40–60–80–90
500–20–50–70900
800700600400300200100
–10–30
TPC 3.AD7924 PSRR vs. Supply Ripple Frequency
INPUT FREQUENCY – kHz
–50
10
1000
T H D – d B
–65–75–85
–90
–60–70–80
100
–55TPC 4.AD7924 THD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS
INPUT FREQUENCY – kHz
–50
10
1000
T H D – d B
–65
–75–85–90
–60–70
–80100
–55TPC 5.AD7924 THD vs. Analog Input Frequency for Various Source Impedances
AD7904/AD7914/AD7924
–13–
REV. 0
Table I.Control Register Bit Functions
MSB LSB
WRITE SEQ1DONTC DONTC
ADD1ADD0PM1PM0SEQ0DONTC RANGE
CODING
Bit Mnemonic Comment
11
WRITE
The value written to this bit of the Control Register determines whether the following 11 bits will be loaded to the control register or not. If this bit is a 1 then the following 11 bits will be written to the control register; if it is a 0 then the remaining 11 bits are not loaded to the control register and so it remains unchanged.10SEQ1The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the use of the sequencer function. (See Table IV.)
9–8DONTCARE
7–6
ADD1, ADD0These two address bits are loaded at the end of the present conversion sequence and select which analog
input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in Table IV. The selected input channel is decoded as shown in Table II. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data,see the Serial Interface section. The next channel to be converted on will be selected by the mux on the fourteenth SCLK falling edge.5, 4PM1, PM0Power Management Bits. These two bits decode the mode of operation of the AD7904/AD7914/AD7924as shown in Table III.
3SEQ0The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the use of the sequencer function. (See Table IV.)
2DONTCARE 1
RANGE
This bit selects the analog input range to be used on the AD7904/AD7914/AD7924. If it is set to 0 then the analog input range will extend from 0 V to 2 × REF IN . If it is set to 1 then the analog input range will extend from 0 V to REF IN (for the next conversion). For 0 V to 2 × REF IN , V DD = 4.75 V to 5.25 V.
0CODING
This bit selects the type of output coding the AD7904/AD7914/AD7924 will use for the conversion result.If this bit is set to 0 the output coding for the part will be twos complement. If this bit is set to 1 then the
output coding from the part will be straight binary (for the next conversion).
CODE
1.00
4096
I N L E R R O R – L S B
–0.4–0.8–1.0
0.2–0.2–0.620480.6
V DD = V DRIVE = 5V TEMP = 25?C
0.40.825603072
3584
512
1024
1536
TPC 6.AD7924 Typical INL CONTROL REGISTER
The Control Register on the AD7904/AD7914/AD7924 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7904/AD7914/AD7924 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conver-sion result is read from the part. The data transferred on the DIN line corresponds to the AD7904/AD7914/AD7924 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.
CODE
1.00
4096
D N L
E R R O R – L S B
0–0.4–0.8–1.0
0.2–0.2–0.620480.6
0.40.825603072
3584
512
1024
1536
TPC 7.AD7924 Typical DNL
–14–AD7904/AD7914/AD7924
REV. 0
Table II.Channel Selection
ADD1ADD0Analog Input Channel 00V IN 001V IN 110V IN 21
1
V IN 3
Table III.Power Mode Selection
PM1PM0Mode 1
1
Normal Operation . In this mode, the AD7904/AD7914/AD7924 remain in full power mode regardless of the status of any of the logicinputs.This mode allows the fastest possible throughput rate from the AD7904/AD7914/AD7924.
10
Full Shutdown . In this mode, the AD7904/AD7914/AD7924 is in full shutdown mode with all circuitry on the AD7904/AD7914/AD7924
powering down. The AD7904/AD7914/AD7924retains the information in the Control Register while in full shutdown. The part remains in full shutdown until these bits are changed.01
Auto Shutdown . In this mode, the AD7904/AD7914/AD7924/ automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs has elapsed before
attempting to perform a valid conversion on the part in this mode.
00
Invalid Selection . This configuration is not allowed.
SEQUENCER OPERATION
The configuration of the SEQ1 and SEQ0 bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table IV outlines the three modes of operation of the Sequencer.
Figure 2 reflects the traditional operation of a multichannel ADC,where each serial transfer selects the next channel for conversion.In this mode of operation the Sequencer function is not used.Figure 3 shows how to program the AD7904/AD7914/AD7924to continuously convert on a sequence of consecutive channels from Channel 0 to a selected final channel. To exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 2), ensure that the WRITE bit = 1 and SEQ1 = SEQ0 = 0 on the next serial transfer.
Table IV.Sequence Selection
SEQ1 SEQ0Sequence Type
X
This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits ADD1, ADD0 in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC,without the Sequencer function being used, where each write to the AD7904/AD7914/AD7924selects the next channel for conversion (see Figure 2).
10
If the SEQ1 and SEQ0 bits are set in this way then the sequence function will not be interrupted upon completion of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while in a sequence without terminating the cycle.
11
This configuration is used in conjunction with the channel address bits ADD1, ADD0 to
program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the Control Register (see Figure 3).
AD7904/AD7914/AD7924
–15–
REV. 0
CS
CS
Figure 2.SEQ1 Bit = 0, SEQ0 Bit = x Flowchart
CS
CS
CS
Figure 3.SEQ1 Bit = 1, SEQ0 Bit = 1 Flowchart
CIRCUIT INFORMATION
The AD7904/AD7914/AD7924 are high speed, 4-channel, 8-bit,10-bit, and 12-bit, single supply, A/D converters, respectively.The parts can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V or 3 V supply, the AD7904/AD7914/AD7924 are capable of throughput rates of 1 MSPS when pro-vided with a 20 MHz clock.
The AD7904/AD7914/AD7924 provide the user with an on-chip track/hold, A/D converter, and a serial interface housed in a 16-lead TSSOP package. The AD7904/AD7914/AD7924 each have four single-ended input channels with a channel sequencer,allowing the user to select a channel sequence through which the ADC can cycle with each consecutive CS falling edge. The serial clock input accesses data from the part, controls the transfer of data written to the ADC, and provides the clock source for the successive-approximation A/D converter. The analog input range for the AD7904/AD7914/AD7924 is 0 V to REF IN or 0 V to 2 × REF IN , depending on the status of Bit 1 in the Control Register. For the 0 to 2 × REF IN range, the part must be operated from a 4.75 V to 5.25 V supply.
The AD7904/AD7914/AD7924 provide flexible power
management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the Power Management bits, PM1and PM0, in the Control Register.
CONVERTER OPERATION
The AD7904/AD7914/AD7924 are 8-, 10-, and 12-bit successive approximation analog-to-digital converters based around a capacitive DAC, respectively. The AD7904/AD7914/AD7924can convert analog input signals in the range 0 V to REF IN or 0 V to 2 × REF IN . Figures 4 and 5 show simplified schematics of the ADC. The ADC is comprised of Control Logic, SAR, and a Capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 4 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A.The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected V IN
channel.
V IN V IN Figure 4.ADC Acquisition Phase
–16–
AD7904/AD7914/AD7924
REV. 0
When the ADC starts a conversion (see Figure 5), SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The Control Logic and the Capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC output code. Figures 7 and 8 show the ADC transfer functions.
V IN
V IN Figure 5.ADC Conversion Phase
Analog Input
Figure 6 shows an equivalent circuit of the analog input structure of the AD7904/AD7914/AD7924. The two diodes D1 and D2provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The capacitor C1 in Figure 6 is typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped com-ponent made up of the on resistance of a switch (track and hold switch) and also includes the on resistance of the input multiplexer.The total resistance is typically about 400 ?. The capacitor C2 is the ADC sampling capacitor and has a capacitance of 30 pF typically. For ac applications, removing high frequency compo-nents from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog input pin. In applica-tions where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application.
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade
(see TPC 5).
V Figure 6.Equivalent Analog Input Circuit
ADC TRANSFER FUNCTION
The output coding of the AD7904/AD7914/AD7924 is either straight binary or twos complement, depending on the status of the LSB in the Control Register. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on).The LSB size is REF IN /256 for the AD7904 , REF IN /1024 for the AD7914, and REF IN /4096 for the AD7924. The ideal transfer characteristic for the AD7904/AD7914/AD7924 when straight binary coding is selected is shown in Figure 7, and the ideal transfer characteristic for the AD7904/AD7914/AD7924 when twos complement coding is selected is shown in Figure 8.
000 (000)
ANALOG INPUT
111...111000...001000...010111 (110)
??
111 (000)
?
011 (111)
??
NOTE: V REF IS EITHER REF IN OR 2 ? REF IN
Figure 7.Straight Binary Transfer Characteristic
A D C C O D E
ANALOG INPUT
V REF ? 1LSB
100 (000)
011...111100...001100...010011 (110)
??000...001111 (111)
??000…000Figure 8.Twos Complement Transfer Characteristic with REF IN ± REF IN Input Range Handling Bipolar Input Signals
Figure 9 shows how useful the combination of the 2 × REF IN input range and the twos complement output coding scheme is for handling bipolar input signals. If the bipolar input signal is biased about REF IN and twos complement output coding is selected, then REF IN becomes the zero code point, –REF IN is negative full scale and +REF IN becomes positive full scale, with a dynamic range of 2 × REF IN .
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7904/
AD7914/AD7924. In this setup the GND pin is connected to the analog ground plane of the system. In Figure 10, REF IN is connected to a decoupled 2.5 V supply from a reference source,the AD780, to provide an analog input range of 0 V to 2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although the AD7904/AD7914/AD7924 is connected to a V DD of 5 V, the serial interface is connected to a 3 V microprocessor. The V DRIVE pin of the AD7904/AD7914/AD7924 is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). The conversion result is output in a
AD7904/AD7914/AD7924
–17–
REV. 016-bit word. This 16-bit data stream consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data for the AD7924 (10 bits of data for the AD7914 and 8 bits of data for the AD7904, each followed by 2 and 4 trailing zeros, respec-tively). For applications where power consumption is of concern,the power-down modes should be used between conversions or bursts of several conversions to improve power performance.See the Modes of Operation section of the data sheet.
NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND
Figure 10.Typical Connection Diagram
Analog Input Selection
Any one of four analog input channels may be selected for con-version by programming the multiplexer with the address bits ADD1 and ADD0 in the Control Register. The channel con-figurations are shown in Table II.
The AD7904/AD7914/AD7924 may also be configured to auto-matically cycle through a number of channels as selected. The sequencer feature is accessed via the SEQ1 and SEQ0 bits in the Control Register, see Table IV. The AD7904/AD7914/AD7924can be programmed to continuously convert on a number of consecutive channels in ascending order from Channel 0 to a selected final channel as determined by the channel address bits ADD1 and ADD0. This is possible if the SEQ1 and SEQ0 bits are set to 1,1. The next serial transfer will then act on the sequence programmed by executing a conversion on Channel 0. The next serial transfer will result in a conversion on Channel 1, and so on, until the channel selected via the address bits ADD1, ADD0is reached.It is not necessary to write to the Control Register again once a sequencer operation has been initiated. The WRITE bit must be set to zero or the DIN line tied low to ensure the Control Regis-ter is not accidently overwritten, or the sequence operation interrupted. If the Control Register is written to at any time during the sequence then it must be ensured that the SEQ1 and SEQ0 bits are set to 1,0 to avoid interrupting the automatic conversion sequence. This pattern will continue until such time as the AD7904/AD7914/AD7924 is written to and the SEQ1and SEQ0 bits are configured with any bit combination except 1,0 resulting in the termination of the sequence. If uninter-rupted, however (WRITE bit = 0, or WRITE bit = 1 and SEQ1and SEQ0 bits are set to 1,0), then upon completion of the sequence, the AD7904/AD7914/AD7924 sequencer will return to the Channel 0 and commence the sequence again.
Regardless of which channel selection method is used, the 16-bit word output from the AD7924 during each conversion will always contain two leading zeros, two channel address bits that the con-version result corresponds to, followed by the 12-bit conversion result; the AD7914 will output two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the AD7904 will output two leading zeros, two channel address bits that the conver-sion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. See the Serial Interface section.
Digital Inputs
The digital inputs applied to the AD7904/AD7914/AD7924 are not limited by the maximum ratings that limit the analog inputs.Instead, the digital inputs applied can go to 7 V and are not restricted by the V DD + 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and CS not being restricted
by the V DD + 0.3 V limit is the fact that power supply sequenc-ing issues are avoided. If CS , DIN, or SCLK are applied before V DD there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to V DD .V DRIVE The AD7904/AD7914/AD7924 also have the V DRIVE feature.V DRIVE controls the voltage at which the serial interface oper-ates. V DRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7904/AD7914/AD7924were operated with a V DD of 5 V, the V DRIVE pin could be pow-ered from a 3 V supply. The AD7904/AD7914/AD7924 have
011 (111)
000 (000)
100 (000)
0V
V
Figure 9.Handling Bipolar Signals
–18–AD7904/AD7914/AD7924
REV. 0
better dynamic performance with a V DD of 5 V while still being able to interface to 3 V processors. Care should be taken to ensure V DRIVE does not exceed V DD by more than 0.3 V. (See the Absolute Maximum Ratings section).
Reference
An external reference source should be used to supply the 2.5 V reference to the AD7904/AD7914/AD7924. Errors in the refer-ence source will result in gain errors in the AD7904/AD7914/AD7924 transfer function and will add to the specified full-scale errors of the part. A capacitor of at least 0.1 μF should be placed on the REF IN pin. Suitable reference sources for the AD7904/AD7914/AD7924 include the AD780, REF 193, and the AD1582.If 2.5 V is applied to the REF IN pin, the analog input range can either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of the RANGE bit in the Control Register.
MODES OF OPERATION
The AD7904/AD7914/AD7924 have a number of different modes of operation. These modes are designed to provide flex-ible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for dif-fering application requirements. The mode of operation of the AD7904/AD7914/AD7924 is controlled by the power manage-ment bits, PM1 and PM0, in the Control Register, as detailed in Table III. When power supplies are first applied to the AD7904/AD7914/AD7924, care should be taken to ensure that the part is placed in the required mode of operation (see the Powering Up the AD7904/AD7914/AD7924 section).
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7904/AD7914/AD7924 remaining fully powered at all times. Figure 11 shows the general diagram of the operation of the AD7904/AD7914/AD7924 in this mode.
The conversion is initiated on the falling edge of CS and the track and hold will enter hold mode as described in the Serial Interface section. The data presented to the AD7904/AD7914/AD7924 on the DIN line during the first 12 clock cycles of the data transfer are loaded into the Control Register (provided WRITE bit is set to 1). The part will remain fully powered up in normal mode at the end of the conversion as long as PM1 and PM0 are set to 1in the write transfer during that same conversion. To ensure continued operation in Normal Mode, PM1 and PM0 must both be loaded with 1 on every data transfer, assuming a write opera-tion is taking place. If the WRITE bit is set to 0, then the power management bits will be left unchanged and the part will remain in Normal Mode.
Sixteen serial clock cycles are required to complete the conver-sion and access the conversion result. The track and hold will go back into track on the fourteenth SCLK falling edge. CS may then idle high until the next conversion or may idle low until sometime prior to the next conversion, (effectively idling CS low).Once a data transfer is complete (DOUT has returned to three-state), another conversion can be initiated after the quiet time,t QUIET , has elapsed by bringing CS low again.
CS
SCLK
NOTE: CONTROL REGISTER DA T A IS LOADED ON FIRST 12 SCLK CYCLES
Figure 11.Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7904/AD7914/AD7924 is powered down. The part retains information in the Control Register during full shutdown. The AD7904/AD7914/AD7924 remains in full shutdown until the power management bits in the Control Register, PM1 and PM0, are changed.If a write to the Control Register occurs while the part is in Full Shutdown, with the power management bits changed to PM0 =PM1 = 1, Normal mode, the part will begin to power up on the CS rising edge. The track and hold that was in hold while the part was in Full Shutdown will return to track on the fourteenth SCLK falling edge.
To ensure that the part is fully powered up, t POWER UP (t 12) should have elapsed before the next CS falling edge. Figure 12 shows the general diagram for this sequence.
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7904/AD7914/AD7924 automatically enters shutdown at the end of each conversion when the control register is updated. When the part is in shutdown, the track and hold is in hold mode. Figure 13 shows the general diagram of the operation of the AD7904/AD7914/AD7924 in this mode. In shutdown mode all internal circuitry on the AD7904/AD7914/AD7924 is powered down. The part retains information in the Control Register during shutdown. The AD7904/AD7914/AD7924remains in shutdown until the next CS falling edge it receives.On this CS falling edge the track and hold that was in hold while the part was in shutdown will return to track. Wake-up time from auto shutdown is 1 μs maximum, and the user should ensure that 1 μs has elapsed before attempting a valid conver-sion. When running the AD7904/AD7914/AD7924 with a 20 MHz clock, one 16 SCLK dummy cycle should be sufficient to ensure the part is fully powered up. During this dummy cycle the contents of the Control Register should remain unchanged,therefore the WRITE bit should be 0 on the DIN line. This dummy cycle effectively halves the throughput rate of the part,with every other conversion result being valid. In this mode the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion. When the Control Register is programmed to move into auto shutdown, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the CS signal.
AD7904/AD7914/AD7924
–19–
REV. 0CS
SCLK
DOUT DIN
1
14
16
1
14
16
P ART IS IN FULL SHUTDOWN
P
ART BEGINS TO POWER UP ON
THE P ART IS FULL Y POWERED UP CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
TO KEEP THE P ART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER
Figure 12.Full Shutdown Mode Operation
CS
SCLK
DOUT
DIN P ART ENTERS
SHUTDOWN ON CS RISING EDGE AS CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 ? 0, PM0 ? 1
CONTROL REGISTER CONTENTS SHOULD NOT CHANGE, WRITE BIT ? 0
TO KEEP P ART IN THIS MODE, LOAD PM1 ? 0, PM0 ? 1IN CONTROL REGISTER OR SET WRITE BIT = 0
P ART IS FULL Y P ART BEGINS TO POWER UP ON CS
P ART ENTERS
SHUTDOWN ON CS RISING EDGE AS Figure 13.Auto Shutdown Mode Operation
Powering Up the AD7904/AD7914/AD7924
When supplies are first applied to the AD7904/AD7914/AD7924,the ADC may power up in any of the operating modes of the part. To ensure the part is placed into the required operating mode the user should perform a dummy cycle operation as outlined in Figures 14a through 14c.
The dummy conversion operation must be performed to place the part into the desired mode of operation. To ensure the part is in normal mode, this dummy cycle operation can be performed with the DIN line tied HIGH, i.e., PM1, PM0 = 1,1 (depending on other required settings in the control register) but the minimum power-up time of 1 μs must be allowed from the rising edge of CS , where the control register is updated, before attempting the first valid conversion. This is to allow for the possibility that the part initially powered up in shutdown. If the desired mode of operation is Full Shutdown, then again only one dummy cycle is required after supplies are applied. In this dummy cycle the user simply sets the power management bits, PM1, PM0 = 1,0and upon the rising edge of CS at the end of that serial transfer the part will enter full shutdown.
If the desired mode of operation is Auto Shutdown after sup-plies are applied, then two dummy cycles will be required, the first with DIN tied high and the second dummy cycle to set the power management bits PM1 and PM0 = 0,1. On the second CS rising edge after the supplies are applied, the Control Regis-ter will contain the correct information and the part will enter Auto Shutdown mode as programmed. If power consumption is of critical concern, then in the first dummy cycle the user may set PM1, PM0 = 1,0, i.e., Full Shutdown, and then place the part into Auto Shutdown in the second dummy cycle. For illus-tration purposes, Figure 14c is shown with DIN tied high on the first dummy cycle in this case.
Figures 14a, 14b, and 14c each show the required dummy cycle(s)after supplies are applied in the case of Normal mode, Full Shutdown mode, or Auto Shutdown mode, respectively, being the desired mode of operation.
–20–AD7904/AD7914/AD7924
REV. 0
INVALID DA T A CHANNEL IDENTIFIER BITS + CONVERSION RESUL T
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DA T A IN TO CONTROL REGISTER
TO KEEP THE P ART IN NORMAL MODE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER
ALLOW TO ELAPSE
IF IN SHUTDOWN A T POWER-ON,P ART BEGINS TO POWER UP ON P ART IS IN
UNKNOWN MODE
CS
SCLK
DOUT DIN
Figure 14a.To Place AD7904/AD7914/AD7924 into Normal Mode after Supplies are First Applied
INVALID DA T A
P ART ENTERS SHUTDOWN ON
P ART IS IN
UNKNOWN MODE CS
SCLK
DOUT DIN
DA T A IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 0
Figure 14b.To Place AD7904/AD7914/AD7924 into Full Shutdown Mode after Supplies are First Applied
INVALID DA T
A INVALID DA T A
DIN LINE HIGH FOR FIRST DUMMY CONVERSION
DA T A IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 0, PM0 = 1
P ART IS IN
UNKNOWN MODE CS
SCLK
DOUT DIN
P ART ENTERS AUTO SHUTDOWN ON Figure 14c.To Place AD7904/AD7914/AD7924 into Auto Shutdown Mode after Supplies are First Applied
POWER VERSUS THROUGHPUT RATE
By operating in Auto Shutdown mode on the AD7904/AD7914/AD7924, the average power consumption of the ADC decreases at lower throughput rates. Figure 15 shows how as the through-put rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly.For example, if the AD7924 is operated in a continuous sam-pling mode, with a throughput rate of 100 kSPS and an SCLK of 20 MHz (V DD = 5 V), and the device is placed in Auto Shut-down mode, i.e., if PM1 = 0 and PM0 = 1, then the power consumption is calculated as follows:
The maximum power dissipation during normal operation is 13.5 mW (V DD = 5 V). If the power-up time from Auto Shutdown is one dummy cycle, i.e., 1 μs, and the remaining conversion time is another cycle, i.e., 1 μs, then the AD7924 can be said to dissipate 13.5 mW for 2 μs during each conversion cycle. For the remainder of the conversion cycle, 8 μs, the part remains in shutdown.The AD7924 can be said to dissipate 2.5 μW for the remaining 8 μs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is (2/10) × (13.5 mW) + (8/10) × (2.5 μW) = 2.702 mW.