ISL51002CQZ-165;ISL51002CQZ-150;ISL51002CQZ-110;ISL51002-EVALZ;中文规格书,Datasheet资料
FN6164.3 ISL51002
10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features The ISL51002 3-channel, 10-bit Analog Front End (AFE) contains all the functionality needed to digitize analog YPbPr video from HDTV tuners, set top boxes, SD and HD DVDs, as well as RGB graphics signals from personal computers and workstations. The fourth generation analog design delivers 10-bit performance and a 165MSPS maximum conversion rate supporting resolutions up to 1080p/UXGA at 60Hz. The front end's programmable input bandwidth ensures sharp, low noise images at all resolutions.
To accelerate and simplify mode detection, the ISL51002 integrates a sophisticated set of measurement tools that fully characterizes the video signal and timing, offloading the host microcontroller. Automatic Black Level Compensation (ABLC?) eliminates part-to-part offset variation, ensuring perfect black level performance in every application.
The ISL51002's Digital PLL generates a pixel clock from the analog source's HSYNC or SOG (Sync-On-Green) signals. Pixel clock output frequencies range from 10MHz to 165MHz with sampling clock jitter of 250ps peak to peak.
Applications
?Flat Panel TVs
?Front/Rear Projection TVs
?PC LCD Monitors and Projectors
?High Quality Scan Converters
?Video/Graphics Processing Features
?Automatic sampling phase adjustment
?10-bit triple Analog to Digital Converters with oversampling up to 8x in video modes
?165MSPS maximum conversion rate (ISL51002CQZ-165)?Robust, glitchless Macrovision?-compliant sync separator ?Analog VCR “Trick Mode” support
?ABLC? for perfect black level performance
? 3 channel input multiplexer
?Precision sync timing measurement
?RGB to YUV color space converter
?Low PLL clock jitter (250ps p-p)
?Programmable input bandwidth (10MHz to 450MHz)
?64 interpixel sampling positions
?±6dB gain adjustment rate
?Pb-free (RoHS compliant)
Related Literature
?Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”.
Simplified Block Diagram
Data Sheet February 29, 2012
Ordering Information
PART NUMBER
(Notes 1, 2)PART MARKING TEMPERATURE RANGE
(°C)
PACKAGE
(Pb-free)PKG. DWG #
ISL51002CQZ-110ISL51002CQZ -1100 to +70128 Ld MQFP MDP0055
ISL51002CQZ-150ISL51002CQZ -1500 to +70128 Ld MQFP MDP0055
ISL51002CQZ-165ISL51002CQZ -1650 to +70128 Ld MQFP MDP0055
ISL51002EVALZ Evaluation Platform
NOTES:
1.These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2.For Moisture Sensitivity Level (MSL), please see device information page for ISL51002-110, ISL51002-150, ISL51002-165. For more information on
MSL please see techbrief TB363.
Absolute Maximum Ratings Thermal Information
3.3V Supply Voltage (V A3.3, V D3.3, VPLL A3.3) . . . . . . . . . . . . .
4.6V 1.8V Supply Voltage (V A1.8, V D1.8, VADC D1.8). . . . . . . . . . . . . 2.5V Voltage on any Input Pin . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 6V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . .3000V Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .300V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage Range. . . . . . . . . . . . . . . . . 3.3V ±10%, 1.8V ±10%Thermal Resistance (Typical)θJA (°C/W)θJC (°C/W) MQFP Package (Notes 3, 4) . . . . . . . .3016 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below https://www.wendangku.net/doc/2d18310933.html,/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES:
3.θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4.For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Specifications apply for V A3.3 = V D3.3 = V PLLA3.3 = 3.3V, V A1.8 = V D1.8 = V PLLD1.8 = V ADCD1.8 = 1.8V,
pixel rate = 110MHz for ISL51002-110, 150MHz for ISL51002-150, 165MHz for ISL51002-165, f XTAL = 25MHz,
and T A = +0°C to +70°C, unless otherwise specified. Boldface limits apply over the operating temperature
range, 0°C to +70°C.
SYMBOL PARAMETER TEST LEVEL or NOTES
MIN
(Note 8)TYP
MAX
(Note 8)UNITS
FULL CHANNEL CHARACTERISTICS
Conversion Rate
ISL51002-11010110MHz
ISL51002-15010150MHz
ISL51002-16510165MHz ADC Resolution10Bits
Missing Codes Guaranteed monotonic None
DNL (Full-Channel)Differential Non-Linearity(Note 5)
ISL51002-110-0.99±0.5+1.2LSB ISL51002-150-0.99±0.7+1.3LSB ISL51002-165-0.99±0.8+1.4LSB
INL (Full-Channel)
Integral Non-Linearity(Note 5)
ISL51002-110±1.9±3.6LSB ISL51002-150±2.0±3.8LSB ISL51002-165±2.6±4.0LSB Gain Adjustment Range±6dB Gain Adjustment Resolution10Bits Gain Matching Between Channels Percent of full scale±2% Full Channel Offset Error,
ABLC? enabled
ADC LSBs, over time and temperature±0.5±3.0LSB
Offset Adjustment Range
(ABLC? enabled or disabled)
(see ABLC? applications information section)±50%ADC
Fullscale
ANALOG VIDEO INPUT CHARACTERISTICS (R IN 0-2, G IN 0-2, B IN 0-2)
Input Range 0.35
0.7 2.2V P-P Input Bias Current DC restore clamp off
±0.01±1
μA Input Capacitance 5pF Full Power Bandwidth
Programmable 10 to 450
MHz
SOG INPUT CHARACTERISTICS (SOG IN 0-2)
Sync Tip Clamp 600mV SOG Pull Down
1μA V IH /V IL
Input Threshold Voltage
(relative to bottom of sync tip)Programmable - See Register Listing for Details
0 to 0.3V Input Capacitance
5
pF
HSYNC INPUT CHARACTERISTICS (HSYNC IN 0-2)
V IH /V IL
Input Threshold Voltage Programmable - See Register Listing for Details 0.4 to 3.2V Hysteresis
Centered around threshold voltage
240mV I Input Leakage Current (Note 6)±10nA C IN
Input Capacitance
5
pF
DIGITAL INPUT CHARACTERISTICS (ALL DIGITAL INPUT PINS EXCEPT SCL, VSYNC IN 0-2)
V IH Input High Voltage 2.0
V V IL Input Low Voltage
0.8
V I Input Leakage Current (Note 6)RESET has a 65k Ω pull-up to V D3.3
±10nA C IN
Input Capacitance
5
pF
SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC IN 0-2)
V T +Low To High Threshold Voltage 1.45
V V T -High To Low Threshold Voltage 0.95
V I Input Leakage Current ±10nA C IN
Input Capacitance
5
pF
DIGITAL OUTPUT CHARACTERISTICS (ALL OUTPUT PINS EXCEPT INT AND SDA)
V OH Output HIGH Voltage, I O = 8mA 2.4
V V OL
Output LOW Voltage, I O = -8mA
0.4
V
DIGITAL OUTPUT CHARACTERISTICS (INT)
V OL
Output LOW Voltage, I O = -8mA
Open-drain, with 65k Ω pull-up to V D3.3
0.4
V
DIGITAL OUTPUT CHARACTERISTICS (SDA)
V OL
Output LOW Voltage, I O = -4mA
Open-drain
0.4
V
POWER SUPPLY REQUIREMENTS
V A3.3Analog Supply Voltage, 3.3V Includes VPLL A3.3
3.0 3.3 3.6V V A1.8Analog Supply Voltage, 1.8V 1.65 1.8 2.0V V D3.3Digital Supply Voltage, 3.3V 3.0 3.3 3.6V V D1.8
Digital Supply Voltage, 1.8V
Includes VADC D1.8, VPLL D1.8 1.65
1.8
2.0
V
A range, 0°C to +70°C. (Continued)
SYMBOL PARAMETER
TEST LEVEL or NOTES
MIN (Note 8)
TYP
MAX (Note 8)
UNITS
I A3.3Analog Supply Current, 3.3V (Note 6)
4590mA IPLL A3.314
25mA I A1.8Analog Supply Current, 1.8V (Note 6)
Includes 1.8V ADC reference current draw 270375mA I D3.3Digital Supply Current, 3.3V (Note 6)
Grayscale ramp input 3060mA I D1.8Digital Supply Current, 1.8V (Note 6)
Grayscale ramp input
6595mA IADC D1.83365mA IPLL D1.8 1.8
10mA P D
Total Power Dissipation
Grayscale ramp input Standby Mode
0.98 1.25W 50
100
mW
AC TIMING CHARACTERISTICS
PLL Jitter (Note 7)250
450
ps p-p
Sampling Phase Steps 5.6° per step
64
Sampling Phase Tempco ±1ps/°C Sampling Phase
Differential Nonlinearity Degrees out of +360°
±3
°HSYNC Frequency Range
10150kHz f XTAL Crystal Frequency Range 1225
27
MHz t SETUP Data Valid Before Rising Edge of Dataclk
20pF DATACLK load, 20pF DATA load 1.8ns t HOLD Data Valid After Rising Edge of Dataclk
20pF DATACLK load, 20pF DATA load 3.4
ns
NOTES:
5.Linearity tested at room temperature and guaranteed across commercial temperature range by correlation to characterization.
6.Supply current specified at max pixel rate (165MHz) with gray scale video applied.
7.Jitter tested at rated frequencies (165MHz, 150MHz, 110MHz) and at minimum frequency (10MHz).
8.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
A range, 0°C to +70°C. (Continued)
SYMBOL PARAMETER
TEST LEVEL or NOTES
MIN (Note 8)
TYP MAX (Note 8)UNITS
Timing Diagrams
RGB Output Data Timing and Latency
Pin Configuration (MQFP, ISL51002)
Pin Descriptions
SYMBOL DESCRIPTION
R IN0, 1, 2Analog inputs. Red channels. AC couple through 0.1μF. Do not connect if not used.
G IN0, 1, 2Analog inputs. Green channels. AC couple through 0.1μF. Do not connect if not used.
B IN0, 1, 2Analog inputs. Blue channels. A
C couple through 0.1μF. Do not connect if not used.
VREF RED, VREF GREEN, VREF BLUE Analog inputs. Reference voltage for ADCs. Tie to 1.8V reference voltage (V A1.8 is acceptable if low noise). Decouple with 0.1μF capacitor to GND A.
SOG IN0, 1, 2Analog inputs. Sync on Green. Connect to corresponding Green channel video source through a 0.01μF capacitor in series with a 500Ω resistor.
HSYNC IN0, 1, 2Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's HSYNC source. For 5V signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pFcapacitor
in parallel with the 1k resistor to reduce the filtering effect of the divider. Tie to GND D if not used.
VSYNC IN0, 1, 2Digital high impedance 3.3V inputs with 240mV hysteresis. Connect to corresponding channel's VSYNC source. For 5V signals divide input with a 1k/1.9k divider. Place the divider as close as possible to the device pin. Place a 50pF capacitor
in parallel with the 1k resistor to reduce the filtering effect of the divider. Tie to GND D if not used.
COAST IN Digital 3.3V input. When this input is high and external COAST is selected, the PLL will coast, ignoring all transitions on the active channel’s HSYNC/SOG.
CLAMP IN Digital 3.3V input.When this input is high and external CLAMP is selected, connects the selected channels inputs to the clamp DAC.
CLOCKINV IN Digital 3.3V input. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to D GND if unused.
FBC IN Digital 3.3V input.Connect to the Fast Blank signal of a SCART connector.
FBC OUT 3.3V digital output. A delayed version of the FBC IN signal, aligned with the digital pixel data.
RESET Digital 3.3V input, active low, 70kΩ pull-up to V D. Take low for at least 1μs and then high again to reset the ISL51002. This pin is not necessary for normal use and may be tied directly to the V D supply.
XTAL IN Analog input. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0V P-P centered around 0.5V.
XTAL OUT Analog output. Connect to external 12MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0V P-P centered around 0.5V.
XCLK OUT 3.3V digital output. Buffered crystal clock output at f XTAL or f XTAL/2. May be used as system clock for other system components.
SADDR Digital 3.3V input. Address = 0x98 (1001100x) when tied low.
Address = 0 x 9A (1001101x) when tied high.
SCL Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
EXTCLK IN Digital 3.3V input. External clock input for AFE.
R[9:0] 3.3V digital output. 10-bit Red channel pixel data.
G[9:0] 3.3V digital output. 10-bit Green channel pixel data.
B[9:0] 3.3V digital output. 10-bit Blue channel pixel data.
DATACLK 3.3V digital output. Data (pixel) clock output.
DATACLK 3.3V digital output. Inverse of DATACLK.
HS OUT 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is always purely horizontal sync (without any composite sync signals)
HSYNC OUT 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC period. This output will pass composite sync signals and Macrovision signals if present on HSYNC IN or SOG IN.
VSYNC OUT 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
Pin Descriptions (Continued)
SYMBOL DESCRIPTION
INT Digital output, open drain, 5V tolerant. Interrupt output indicating mode change or command execution status. Pull high with a 4.7k resistor.
DE 3.3V digital output. High when there is valid video data, low during horizontal and vertical blanking periods.
FIELD 3.3V digital output. For interlaced video, this output will changes states to indicate whether current field is even or odd.
Polarity is determined by configuration register.
V A3.3Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND A with 0.1μF.
V A1.8Power supply for the analog section. Connect to a 1.8V supply and bypass each pin to GND A with 0.1μF.
VPLL A3.3Power supply for the analog PLL section. Connect to a 3.3V supply and bypass to GND A with 0.1μF.
GND A Ground return for V A3.3, V A1.8, and VPLL A1.8.
V D3.3Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND D with 0.1μF.
V D1.8Power supply for digital core logic. Connect to a 1.8V supply and bypass each pin to GND D with 0.1μF.
VADC D1.8Power supply for the digital ADC section. Connect to a 1.8V supply and bypass to GND D with 0.1μF.
VPLL D1.8Power supply for the digital PLL section. Connect to a 1.8V supply and bypass to GND D with 0.1μF.
GND D Ground return for V D3.3, V D1.8, VADC D1.8, and VPLL D1.8.
ATEST1, 2For production use only. Tie to GND A.
DTEST1, 2, 3, 4For production use only. Tie to GND D.
NC Reserved. Do not connect anything to these pins.
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INTERSIL
ISL51002CQZ-165ISL51002CQZ-150ISL51002CQZ-110 ISL51002-EVALZ