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Part I TRUE/FALSE: Write 'T' if the statement is true and 'F' if the statement is false.

(1) %eax, %ebx and %ecx are CALLER saved registers. ( F )

(2) Callee can read and write CALLER saved registers. ( T )

(3) Caller cannot read and write CALLEE saved registers before the call happens. ( F )

(4) Callee can use %ebp to get parameters. ( T )

(5) Return address is saved by callee. ( F )

(6) There are two IEEE float representations exactly equal to zero. ( T )

(7) Denormalized floats represent magnitudes greater than those of normalized floats. ( F )

(8)The largest possible finite denormalized IEEE floating number is greater than the smallest possible positive normalized IEEE float-ing number. ( F )

(9)A direct-mapped cache memory has 1 line per set. ( T )

(10)Larger caches are more susceptible to capacity misses than smaller caches. ( F )

(11)Caches with lower associativity are more susceptible to conflict misses than those with higher associativy. ( T )

(12)Caches with higher associativity are more susceptile to cold misses than those with lower associativey. ( F )

(13)The operating system kernel runs as its own separate process. ( F )

(14)Each process shares the CPU with other processes. ( T )

(15)Each process has its own private address space. ( T )

(16)The environment for a process is stored on the stack. ( T )

(17) The x86 instructions lea can be used to add two registers and store the result without overwriting either of the original registers. ( T )

(18) A 32-bit IEEE float can represent any 32-bit integer to within 0.5.( F )

(19) All 32-bit IEEE floats with integer values are encoded with the binary point at the right most bit,so E (the exponent) is 0 and exp (the 8-bit exponent field) is E + bias = 127.( F )

(20) No decimal integer has an exact representation in IEEE floating point (10 is not a power of 2).( F )

(21) There is no exact representation in IEEE floating point of most decimal fractions.( T )

(22)In x86 64 the %rbp register can be used as a general purpose register. .( T )

(23) IA32 is able to make use of a larger address space than x86-64.( F )

(24) x86-64 is able to make use of more registers than IA32.( T )

(25) x86-64 is able to make use of larger registers than IA32.( T )

(26)The rule of mappings between unsigned and two’s complement numbers is that keep bit representations and reinterpret.( T )

(27)Any sequence of IA32 instructions can be executed on an x86-64 processor. ( T )

(28)IA32 systems are Little endian. ( T )

(29) x86-64 provides a larger virtual address space than x86.( T )

(30) The stack disciplines for x86 and x86-64 are different.( T )

(31) x86 uses %ebp as the base pointer for the stack frame.( T )

(32) x86-64 uses %rbp as the base pointer for the stack frame.( F )

(33)DRAM is faster then SRAM. ( F )

(34) Unsigned Addition is Commutative. ( T )

(35) Itanium maintains full backward compatibility with IA32.( F )

(36)In C language, two-dimensional arrays are stored in column-major order, to help with cache performance. ( F)

(37)Assembly can deal with datas of aggregate type directly. ( F )

(38) IA32 can not do memory-memory transfer with a single instruction. ( T )

(39)Under same ISA, there can be many different processors. ( T )

(40) For embedded processors, RISC makes sense. ( T )

Part II Fill in the blank.

1．On IA32 systems, where is the value of old %ebp saved in relation to the current value of %ebp? old %ebp is stored at(%ebp).

2．Internet is _______Big_______ Endian.

3．_______100______ is the maximum number of page faults per second that can be serviced in a system that has a disk with an average access time of 10ms.

4. In C, the value of a pointer is the _______virtual_______ address of the first byte of some block of storage.

5._______-231_______is the minimum (most negative) value of a 32-bit two’s complement integer.

6. In C, each character in string is encoded in _______ASCII_______ format.

7.After executing the following code, the value of variable c is0 .

unsigned int a = 0xffffffff;

unsigned int b = 1;

unsigned long c = a + b;

8. CISC stands for _______Complex_______ Instruction Set Computer.

9.In C, the expression ”15213U > ?1” evaluates to False (0).

10. In Boolean Algebra, “True” is encoded as _______1_______.

11.Let int y = -31 >> 3. So the values of y is -4 .

12. Basic rule for converting between signed and unsigned is that ______Bit pattern ______ is maintained but reinterpreted.

13.A 256-byte 2-way set associative cache with 16 byte blocks has 8 sets.

14.One important optimization used by compilers is to attempt to replace multiplications by constant factors with combinations of _______shift_______ and addition operations.

15.Register ______%rax _____________ stores the return value of functions in Intel x86-64. 16．ISA stands for _______ instruction _______ set architecture.

17. Virtual memory works because of locality .

18.The _______program counter_______ indicates the address in memory of the next instruction to be executed.

19. Static ram is used for cache memory which is placed between the CPU and the main memory.

20.In order to manage memory more efficiently and with fewer errors, modern systems provide an abstraction of main memory known as _______virtual memory _______ .

Part III Multiple Choice: Identify the choice that best completes the statement or answers the question.

1. If %esp has the value 0xBFFF0000 before a call instruction, the value immediately after the callinstruction (before the first instruction of the called function) is:( a )

(a) 0xBFFEFFFC

(b) 0xBFFF0004

(d) The address of the instruction after the call instruction.

2.Which of the following is true: ( d )

(a) A 32-bit IEEE float can represent any 32-bit integer to within 0.5.

(b) All 32-bit IEEE floats with integer values are encoded with the binary point at the rightmost bit,so E (the exponent) is 0 and exp (the 8-bit exponent field) is E + bias = 127.

(d) There is no exact representation in IEEE floating point of most decimal fractions.

3. Why does the compiler sometimes generate xorl %eax,%eax rather than movl $0x0,%eax? ( b )

(a) Using xorl allows the binary code to run on both IA32 and x86-64 architectures.

(b) The xorl form is faster and/or uses fewer bytes than movl.

(d) The xorl form stalls the processor until the the result value is stored in %eax and ready for useby the next instruction.

4.Arguments to a function, in Intel IA32 assembly, are passed via( a )

(a) The stack

(b) Registers

(d) A combination of the stack and registers.

5. In two’s compliment, what is -TMin? ( a )

(a) Tmin (b) Tmax (c) 0 (d) -1

6. By default, on Intel x86, the stack( b )

(a) Is located at the bottom of memory.

(b) Grows down towards smaller addresses

(d) Is located in the heap

7. If a is of type (int) and b is of type (unsigned int), then (a < b) will perform ( a )

(a) An unsigned comparison. (b) A signed comparison.

8. Consider a 4-way set associative cache (E = 4). Which one of the following statements it true? ( c )

(a) The cache has 4 blocks per line. (b) The cache has 4 sets per line.

9．Assume a function foo takes two arguments. When calling foo(arg1, arg2), which is thecorrect order of operations assuming x86 calling conventions and that foo must allocate stack space(implies that we must save the %ebp)? ( c )

(a) push arg1, push arg2, call foo, push %ebp

(b) push arg1, push arg2, push %ebp, call foo

(d) push arg2, push arg1, push %ebp, call foo

10.On what variable types does C perform logical right shifts? ( b )

(a) signed types (b) unsigned types

11. If a direct mapped cache is 8KB in size, and has 32 byte cache blocks, how many lines are there in each set? ( d )

(a) 256 (b) 64 (c) 32 (d) 1

12. You have a 32-bit virtual memory system with 4KB page frames, with a TLB with 4 sets, each of which is 8-way set associative. How many bits of the virtual address form the TLBi (TLB index)? ( a )

(a) 2 (b) 4 (c) 8 (d) 12

13. Consider a theoretical computer architecture with 50-bit virtual addresses and 16kb pages.

What is the maximum number of levels of page tables that could be used in the virtual memory system?( b )

(a) 16 (b) 36 (c) 2 (d) 50

14. Which of these features in a system best justifies the use of a two level page table structure, as opposed to a one level page table structure?( d )

(a) Small page sizes (b) Frequent memory accesses

15.Which of the following will reduce the number of compulsory (cold) cache misses in a program?( b )

(a) Increasing the associativity (b) Increasing line size

16. What is the maximum number of page faults per second that can be serviced in a system that has a disk with an average access time of 10ms? ( b )

(a) 10 (b) 100 (c) 50 (d) Depends on the percentage of memory accesses that are page faults

17. Why does Count Dracula not have to worry about his program’s memory addresses overlapping those of other processes run on the same system? ( a )

(a) Each process has its own page table

(b) The linker carefully lays out address spaces to avoid overlap

(d) He does need to worry

18. Dr. Frankenstein has a disk that rotates at 7,200 RPM (8ms per full revolution), has an average seektime of 5ms, and has 1000 sectors per track. How long (approximately) does the average 1-sectoraccess take? ( c )

(a) Not enough information to determine the answer (b) 13ms (c) 9ms (d) 10.5ms

19. How much virtual memory can be addressed by a 32-bit system? ( b )

(a) 2GB (b) 4GB (c) 8GB (d) 240TB

20. Which of the following is a reason why a virtual memory translation would fault? ( a )

(a) Page is not present (b) Page is read only (c) Page is empty (d) All of the above

21.How many bits are needed for the Virtual Page Offset if page size is 5000 bytes? ( d )

(a) 10 (b) 11 (c) 12 (d) 13

22．Consider an int *a and an int n. If the value of %ecx is a and the value of %edx is n, which of the following assembly snippets best corresponds to the C statement return a[n]? ( c )

(a) ret (%ecx,%edx,4)

(b) leal (%ecx,%edx,4),%eax

ret

(d) mov (%ecx,%edx,1),%eax

ret

23. Which of the following 8 bit floating point numbers (1 sign, 3 exponent, 4 fraction) represent NaN? ( b )

(a) 1 000 1111 (b) 0 111 1111 (c) 0 100 0000 (d) 1 111 0000

24. In C language, two-dimensional arrays are stored in_____ ( b )_______ order, to help

with cache performance.

(a) column-major (b) row-major (c) diagonal-major (d) Art-major

25.Which register holds the first argument when an argument is called in IA32 (32 bit) architecture? ( d )

(a) edi (b) esi (c) eax (d) None of the above

26. What is the C equivalent of mov 0x10(%rax,%rcx,4),%rdx ____ (c) ____

(a) rdx = rax + rcx + 4 + 10

(b) *(rax + rcx + 4 + 10) = rdx

(d) rdx = *(rax + rcx + 4 + 0x10)

27. What is the C equivalent of leal 0x10(%rax,%rcx,4),%rdx ____ (b) ____

(a) rdx = 10 + rax + rcx + 4

(b) rdx = 0x10 + rax + rcx*4

(d) *(0x10 + rax + rcx + 4) = rdx

28. What is the C equivalent of mov %rax,%rcx ____ (a) ____

(a) rcx = rax

(b) rax = rcx

(d) rcx = *rax

29. In x86 (IA32) an application’s stack grows from ____ (a) ____

(a) High memory addresses to low memory addresses

(b) Low memory addresses to high memory addresses

(d) Stacks are a fixed size and do not grow.

30. %rsp is 0xdeadbeefdeadd0d0. What is the value in %rsp after the following instruction exe-cutes? ( d )

pushq %rbx

(a) 0xdeadbeefdeadd0d4(b) 0xdeadbeefdeadd0d8(c) 0xdeadbeefdeadd0cc(d) 0xdeadbeefdeadd0c8

31.Which of the following lines of C code performs the same operation as the assembly statement lea 0xffffffff(%esi),%eax. ( c )

(a) *(esi-1) = eax (b) esi = eax + 0xffffffff (c) eax = esi – 1 (d) eax = *(esi -1)

32. test %eax, %eax

jne 3d

Which of the following values of %eax would cause the jump to be taken? ( a )

(a) 1 (b) 0 (c) Any value of %eax

(d) No value of %eax would cause the jump to be taken.

33. What sequence of operations does the leave instruction execute? ( a )

(a) mov %ebp,%esp

pop %ebp

(b) pop %ebp

mov %ebp,%esp

(d) push %ebp

mov %esp,%ebp

34. What is the difference between the %rbx and the %ebx register on an x86 64 machine? ( b )

(a) nothing, they are the same register

(b) %ebx refers to only the low order 32 bits of the %rbx register

(d) %ebx refers to only the high order 32 bits of the %rbx register

35. On IA32 systems, where is the value of old %ebp saved in relation to the current value of %ebp? ( d )

(a) there is no relation between where the current base pointer and old base pointer are saved.

(b) old %ebp is stored at (%ebp - 4)

(d) old %ebp is stored at (%ebp)

36. Who is responsible for storing the return address of a function call?（ a ）

(a) the caller (b) the callee (c) the kernel (d) the CPU

37.Assuming the register %rbx contains the value 0xfaaafbbbfcccfddd, which instruction would cause the register %rdi to contain the value 0x00000000fcccfddd?( c )

(a) movl %ebx, %rdi (b) movslq %ebx, %rdi (c) movzlq %ebx, %rdi (d) lea %ebx, %rdi

38. Extending the stack can by done by ( b )

(a) swapping the base pointer and the stack pointer

(b) subtracting a value from your stack pointer

(d) executing the ret instruction

39. In C, the result of shifting a value by greater than its type’s width is: ( b )

(a) illegal (b) undefined (c) 0 (d) Encouraged by the C1x standard.

40. Which of the following mov instructions is invalid? ( d )

(a) mov %esp, %ebp (b) mov $0xdeadbeef, %eax

41. What is the minimum (most negative) value of a 32-bit two’s complement integer? ( c )

(a) -232(b) -232+ 1(c) -231(d) -231+ 1

42. What is the difference between the mov and lea instructions? ( b )

(a) lea dereferences an address, while mov doesn’t.

(b) mov dereferences an address, while lea doesn’t.

(d) mov can be used to copy a register into another register, while lea cannnot.

43. After executing the following code, which of the variables are equal to 0? ( c )

unsigned int a = 0xffffffff;

unsigned int b = 1;

unsigned int c = a + b;

unsigned long d = a + b;

unsigned long e = (unsigned long)a + b;(Assume ints are 32 bits wide and longs are 64 bits wide.)

(a) None of them (b) c (c) c and d (d) c, d, and e

44. Which one of the following statements about cache memories is true? ( b )

(a) Fully associative caches offer better latency, while direct-mapped caches have lower miss rates.

(b) Fully associative caches offer lower miss rates, while direct-mapped caches have better latency.

(d) Both generally have similar latency and miss rates.

45.In C, the expression ”15213U > ?1” evaluates to( b )

(a) True (1) (b) False (0)

46.Let int x = -31/8 and int y = -31 >> 3. What are the values of x and y? ( c )

(a) x = -3, y = -3 (b) x = -4, y = -4 (c) x = -3, y = -4 (d) x = -4, y = -3

47. Consider the following code, what is the output of the printf? ( b )

int x = 0x15213F10 >> 4;

char y = (char) x;

unsigned char z = (unsigned char) x;

printf("%d, %u", y, z);

(a) -241, 15 (b) -15, 241 (c) -241, 241 (d) -15, 15

48.IA32 systems are

(a) Little endian (b) Big endian (c) Have no endianess (d) Depend on the operating system

49. Which of the following registers stores the return value of functions in Intel x86-64?( a )

(a) %rax (b) %rcx (c) %rdx (d) %rip

50. Denormalized floating point numbers are ( a )

(a) Very close to zero (small magnitude)

(b) Very far from zero (large magnitude)

(d) Zero.

51. Which of the following is a legitimate difference between IA-32 and x86-64?( d )

(a) Buffer overflow exploits are impossible under x86-64.

(b) IA-32 has caller- and callee-saved register conventions, while x86-64 does not.

(d) None of the above.

52. Which of the following is the best justification for using the middle bits of an address as the set indexinto a cache rather than the most significant bits? ( d )

(a) Indexing with the most significant bits would necessitate a smaller cache than is possible withmiddle-bit indexing, resulting in generally worse cache performance.

(b) It is impossible to design a system that uses the most significant bits of an address as the setindex.

(d) A program with good spatial locality is likely to make more efficient use of the cache withmiddle-bit indexing than with high-bit indexing.

53. Which of the following is not a benefit of virtual memory?( c )

(a) It allows the virtual address space to be larger than the physical address space

(b) No process can accidentally access the memory of another process

(d) Different processes can have overlapping virtual address spaces without conflict

54.Where is the first argument to a function located in 32-bit assembly code, immediately after the callinstruction is executed?( c )

(a) %ebp + 0x4 (b) %ebp - 0x4 (c) %esp + 0x4 (d) %exp - 0x4

55.Why would the kernel designer opt for a 2-level page table when a full 2-level page table takes upmore memory than a full 1-level page table? ( c )

(a) 2-level tables can translate virtual addresses faster.

(b) 2-level tables can reference more memory than 1 level tables.

(d) They woul dn’t. Adding more tables offers no advantages.

56. If a page table on a 32-bit system is 2KB in size, how many entries does it contain? ( c )

(a) 2048 (b) 1024 (c) 512 (d) 256

57. What is the function of the TLB? ( c )

(a) Caches data (b) Caches instructions

(d) Translates physical addresses to virtual addresses

58. What is distinctive about superscalar processors?

(a) Can run at frequencies over 3.5GHz

(b) Can address over 4GB of memory

(d) Can have more than 2 levels of cache

59. A 256-byte 4-way set associative cache with 16 byte blocks has( a )

(a) 4 sets (b) 16 sets (c) 64 sets (d) No sets

60. Imagine a floating point format with no sign bit, one exponent bit, and one fraction bit. Which of thefollowing is not a number?( c )

(a) 00(b) 01(c) 11(d) None of the above

Part IV Short Answer Directions: Answer the following questions

1.Consider the source code below, where M and N are constants declared with #define.

int array1[M][N];

int array2[N][M];

int copy(int i, int j)

{

array1[i][j] = array2[j][i];

}

Suppose the above code generates the following assembly code:

copy:

pushl %ebp

movl %esp,%ebp

pushl %ebx

movl 8(%ebp),%ecx

movl 12(%ebp),%ebx

leal (%ecx,%ecx,8),%edx

sall $2,%edx

leal (%ebx,%ebx,2),%eax

sall $2,%eax

movl array2(%eax,%ecx,4),%eax

movl %eax,array1(%edx,%ebx,4)

popl %ebx

movl %ebp,%esp

popl %ebp

ret

What are the values of M and N?

M =

N =

answer:

M=3

N=9

2.List any three types of Enhanced DRAM.

answer:

Fast page mode DRAM (FPM DRAM)

Extended data out DRAM (EDO DRAM)

Synchronous DRAM (SDRAM)

Double data-rate synchronous DRAM (DDR SDRAM)

Video RAM (VRAM)

3.This problem tests your ability of matching assembly code to the corresponding C pointer code. Note that some of the C code below doesn’t do anything useful.

int fun4(int ap, int bp)

{

int a = ap;

int b = bp;

return *(&a + b);

}

int fun5(int *ap, int bp)

{

int *a = ap;

int b = bp;

return *(a + b);

}

int fun6(int ap, int *bp)

{

int a = ap;

int b = *bp;

return *(&a + b);

}

pushl %ebp

movl %esp,%ebp

subl $24,%esp

movl 12(%ebp),%edx

movl 8(%ebp),%eax

movl %eax,-4(%ebp)

movl (%edx),%eax

sall $2,%eax

movl -4(%eax,%ebp),%eax

movl %ebp,%esp

popl %ebp

ret

Which of the functions compiled into the assembly code shown?

answer:fun6

4.Pick out the instruction which is not included in Y86 ISA from the following instructions.

nop , halt , leave , ret

answer: leave

5. Consider the following 12-bit floating point representation based on the IEEE floating point format:

There is a sign bit in the most significant bit.

The next k=4 bits are the exponent. The exponent bias is 7.

The last n=7 bits are the significand.

Numeric values are encoded in this format as a value of the form V=(-1)s×M×2E,where s is the sign bit,E is exponent after biasing, and M is the significand.

How many FP numbers are in the following intervals [a,b)?

For each interval [a,b), count the number of x such that a<=x

A. Interval [1,2): ________

B. Interval [2,3): ________

answer:

A. [1,2): 2^7

B. [2,3): 2^6

6.Please write the IEEE754 storage format for 20.59375 in hexadecimal format. answer:

(20.59375)

10＝(10100.10011)

＝1.010010011×2100E＝100=(4)10

S=0 Exp=E + Bias = E + (127)

= 100 + 01111111 = 10000011

M＝0100 1001 1000 0000 0000 000

Thus:

the IEEE754 storage format is

100 1 1010 0100 1100 0000 0000 0000＝(41A4C000)

7. Consider the following fragment of IA32 code taken directly from the C standard library:

0x400446e3: call 0x400446e8

0x400446e8: popl %eax

After the popl instruction completes, what hex value does register %eax contain?

answer:%eax = 0x400446e8

8.Assume a very small direct mapped 16 byte data cache with two cache lines and a float requires 4 bytes. For the following code sequence, we assume a cold cache and that the array X is cache aligned (that is, X[0] is loaded into the the beginning of the first cache line. All other variables are held in registers.

Hit rate is defined as

hit

accesses,please get the hit rate for the following code sequence.

float X[8], float t = 0;

for(i = 0; i < 2; i++)

for(k = 0; k < 2; k++)

for(j = 0; j < 4; j++)

t += X[j + i * 4];

answer: 75%

9. Wrlte out a corresponding function definition in C. sum:

pushl %ebp

movl %esp,%ebp

movl 12(%ebp),%eax

addl 8(%ebp),%eax

popl %ebp

ret

answer:

int sum(intx, inty)

{

int t = x+y;

return t;

}

10. test %eax, %eax

jne 3d

Give a value of %eax that would cause the jump not to be taken.

answer:0

Part V Comprehensive questions:

1．Write the secure version for the function below.

void* copy_elements(void *ele_src[], int ele_cnt, size_t ele_size) { void *result = malloc(ele_cnt * ele_size);

if (result == NULL)

return NULL;

void *next = result;

int i;

for (i = 0; i < ele_cnt; i++) {

memcpy(next, ele_src[i], ele_size);

next += ele_size;

}

return result;

}

answer:

void* copy_element（void *ele_src[], int ele_cnt, size_t ele_size) { long long unsigned required_size = ele_cnt * (long long unsigned)ele_size;

size_t request_size = (size_t) required_size;

if (request_size != required_size)

return NULL;

void *result = malloc(request_size);

if （result == NULL)

result NULL;

void *next = result ;

int i;

for （i = 0; i < ele_cnt; i++) {

memcpy(next, ele_src[i], ele_size);

next += ele_size;

}

return result ;

}

2. The following problem concerns the way virtual addresses are translated into physical addresses.

●The memory is byte addressable, and memory accesses are to 1-byte {not 4-byte}words.

●Virtual addresses are 18 bits wide.

●Physical addresses are 12 bits wide.

●The page size is 512 bytes.

●The TLB is 8-way set associative with 16 total entries.

●The cache is 2-way set associative, with a 4-byte line size and 32 total entries.

In the following tables, all numbers are given in hexadecimal. The contents of the TLB and the page table for the first 32 pages, and the cache are as follows:

Part 1

1.The box below shows the format of a virtual address. Indicate (by labeling the diagram) the

fields (ifthey exist) that would be used to determine the following: (If a field doesn’t exist, don’t draw it on the diagram.)

VPO The virtual page offset

VPN The virtual page number

TLBI The TLB index

TLBT The TLB tag

2.The box below shows the format of a physical address. Indicate (by labeling the diagram) the

fieldsthat would be used to determine the following:

PPO The physical page offset

PPN The physical page number

CO The Cache Block Offset

CI The Cache Index

CT The Cache Tag

Part 2

For the given virtual addresses, indicate the TLB entry accessed and the physical address. Indicate whetherthe TLB misses and whether a page fault occurs.

If there is a cache miss, enter “-” for “Cache Byte Returned.” If there is a page fault, enter “-” for “PPN”and leave part C blank.

Virtual address: 0x1A9F4

1. Virtual address format (one bit per box)

2. Address translation

3.Physical address format (one bit per box)

4.Physical memory reference

answer:

Part 1

1. VPO - [8:0] TLBI - [9]

VPN - [17:9] TLBT - [17:10]

2. PPO - [8:0] CO - [1:0] CT - [11:4]

PPN - [11:9] CI - [3:2]

Part 2

1. 01 1010 1001 1111 0100

2. VPN - 0xD4

TLBI - 0x0

TLBT - 0x6A

TLB Hit? - Y

Page Fault? - N

PPN - 0x3

3. 0111 1111 0100

4. BO - 0x0

CI - 0x1

CT - 0x7F

Cache Hit? - Y Byte - 0xFF