密码锁程序1
6.1顶层模块(cipher_top.vhd)
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE WORK.cipher_example.ALL;
ENTITY cipher_top IS
PORT(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9 : IN std_logic;
wait_t : IN std_logic;
ready : IN std_logic;
setup : IN std_logic;
open_t : IN std_logic;
clk : IN std_logic;
led_g,led_r,alert : OUT std_logic;
a,b,c,d,e,f,g : OUT std_logic;
sel : OUT std_logic_vector(2 DOWNTO 0));
END cipher_top;
ARCHITECTURE cipher_top_arch OF cipher_top IS
COMPONENT keysync_model—消抖模块
PORT(c1,c2,c3,c4: IN std_logic;
a00,a10,a20,a30,a40,a50,a60,a70,a80,a90: IN std_logic;
clk: IN std_logic;
c11,c22,c33,c44: OUT std_logic;
a01,a11,a21,a31,a41,a51,a61,a71,a81,a91: OUT std_logic);
END COMPONENT;
COMPONENT enable_model—使能电路模块
PORT(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9: IN std_logic;
en: IN std_logic;
a00,a10,a20,a30,a40,a50,a60,a70,a80,a90: OUT std_logic);
END COMPONENT;
COMPONENT mux4_model—密码预置模块
PORT(s0,s1,s2 : IN std_logic;
e1,e2,e3,e4 : OUT std_logic);
END COMPONENT;
COMPONENT encoder_model --编码模块
PORT(a01,a11,a21,a31,a41,a51,a61,a71,a81,a91 : IN std_logic;
reset,dus : IN std_logic;
b1,b2,b3,b4 : OUT std_logic;
data_in,di : OUT std_logic;
in1,in2,in3,in4,in5,in6 : OUT std_logic_vector(3 DOWNTO 0)); END COMPONENT;
COMPONENT comparator_model—比较模块
PORT(b1,b2,b3,b4: IN std_logic;
e1,e2,e3,e4: IN std_logic;
dep : OUT std_logic);
END COMPONENT;
COMPONENT counter_model—计数模块
PORT(reset : IN std_logic;
cnp : IN std_logic;
s0,s1,s2 : OUT std_logic;
full : OUT std_logic);
END COMPONENT;
COMPONENT decoder_model—数码显示模块
PORT(data : IN std_logic_vector(3 DOWNTO 0);
a,b,c,d,e,f,g: OUT std_logic);
END COMPONENT;
COMPONENT indicator_model—指示模块
PORT(wait_l : IN std_logic;
s_lg : IN std_logic;
s_lr : IN std_logic;
di,bjy : IN std_logic;
clk_div1 : IN std_logic;
led_g,led_r,alert: OUT std_logic);
END COMPONENT;
COMPONENT control_model—控制模块
PORT(c11,c22,c33,c44 : IN std_logic;
data_in : IN std_logic;
dep,dsw : IN std_logic;
full,notc : IN std_logic;
clk : IN std_logic;
en,dus,anc: OUT std_logic;
cnp,reset : OUT std_logic;
ds,ret : OUT std_logic;
s_lr,s_lg,wait_l: OUT std_logic);
END COMPONENT;
COMPONENT clkdiv_model—分频模块
PORT(clk : IN std_logic;
clk_div1 : OUT std_logic;
clk_div2 : OUT std_logic);
END COMPONENT;
COMPONENT keyscan_model
PORT(clkscan,reset : IN std_logic;
in1,in2,in3,in4,
in5,in6,in7,in8 : IN std_logic_vector(3 DOWNTO 0);
data : OUT std_logic_vector(3 DOWNTO 0);
sel : OUT std_logic_vector(2 DOWNTO 0));
END COMPONENT;
U1: keysync_model
PORT
MAP(wait_t,setup,ready,open_t,a00,a10,a20,a30,a40,a50,a60,a70,a80,a90, clk_div1,c11,c22,c33,c44,a01,a11,a21,a31,a41,a51,a61,a71, a81,a91);
U2: enable_model
PORT MAP(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,en,a00,a10,
a20,a30,a40,a50,a60,a70,a80,a90);
U3: mux4_model
PORT MAP(s0,s1,s2,e1,e2,e3,e4);
U4: encoder_model
PORT MAP(a01,a11,a21,a31,a41,a51,a61,a71,a81,a91,reset,dus,b1, b2,b3,b4,data_in,di,in1,in2,in3,in4,in5,in6);
U5: comparator_model
PORT MAP(b1,b2,b3,b4,e1,e2,e3,e4,dep);
U6: counter_model
PORT MAP(reset,cnp,s0,s1,s2,full);
U7: decoder_model
PORT MAP(data,a,b,c,d,e,f,g);
U8: indicator_model
PORT MAP(wait_l,s_lg,s_lr,di,bjy,clk,led_g,led_r,alert);
U9:control_model
PORT
MAP(c11,c22,c33,c44,data_in,dep,dsw,full,notc,clk_div1,en,dus,anc,cnp,reset, ds,ret,s_lr,s_lg,wait_l);
U10:clkdiv_model
PORT MAP(clk,clk_div1,clk_div2);
U11:keyscan_model
PORT MAP(clk,reset,in1,in2,in3,in4,in5,in6,in7,in8,data,
sel);
U12:wrong3_model
PORT MAP(anc,ds,clk_div2,ret,in7,in8,notc,dsw,bjy);
END cipher_top_arch;
1.230分频单元电路(clk_div30.vhd)
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY clk_div30 IS
PORT(clk : IN std_logic;
clk_div : OUT std_logic);
END clk_div30;
ARCHITECTURE behave OF clk_div30 IS
BEGIN
PROCESS(clk)
VARIABLE count:std_logic_vector(3 DOWNTO 0);
VARIABLE clk_tmp: std_logic;
BEGIN
IF(clk'event AND clk='1') THEN
IF(count="1110") THEN
count := (OTHERS => '0');
clk_tmp := NOT clk_tmp;
ELSE
count := count+1;
END IF;
END IF;
clk_div <= clk_tmp;
END PROCESS;
END behave;
准备就绪状态是指密码器在被按下WAIT_T键后处于的一种状态。这时如果操作人员按下READY键，密码器将会进入到第3种状态，等待密码数字的输入。在这种情况下，RESET 将被置1，DS信号将被置0。
WHEN QC => reset<='0';cnp<='0';en<='1';
dus<='0';anc<='0';
IF (c44='1') THEN
current_state <= QF;
anc<='1';
ELSIF(c33='1') THEN
current_state <= QC;
reset <= '1';
ELSIF(full='1') THEN
current_state <= QD;
ELSIF(data_in='0') THEN
current_state <= QC;
ELSE
dus <= '1';
IF(dep='0') THEN
current_state <= QE;
ELSE
cnp <= '1';
IF(full='1') THEN
current_state <= QD;
ELSE
current_state <= QC;
END IF;
END IF;
END IF;
密码输入状态是控制器模块的第3个状态，这是密码器将进入到密码输入的操作状态。当处于这种状态时，控制器模块的EN输出信号将变为有效，它意味着此时允许数字密码A0～A9的按键输入。在这种情况下，密码器每收到一个按键信号后，控制器模块应该判断出该按键输入是数字密码还是OPEN_T信号。
如果判断出按键输入OPEN_T信号，那么这是就不符合启动程序，这是密码器将转移到报警状态，同时还向密码错误次数计数模块发出ANC时钟，作为密码错误次数计数输入脉冲。是如果判断出是数字按键输入，则提供DUS时钟给编码模块作为密码输入位数计数脉冲信号，同时如果判断出该按键输入为正确密码，则向计数器选择模块发出CNP时钟信号，目的是选出对应的预置密码与输入的密码进行比较。对于比较模块来说，如果DEP的输出为0，那么控制器模块应该转移到密码错误状态；如果DEP的输出为0，那么这时检查计数器选择模块的输出FULL是否有效。如果FULL有效，那么表示已经接收了6个正确的数字密码，控制器模块将转移到启动状态，否则将返回本状态继续接收密码。
WHEN QD => en <= '1'; dus <= '0';
IF (data_in='1') THEN
dus <= '1';
ELSIF(c33='1') THEN
current_state <= QC;
reset <= '1';
ELSIF(c44='0') THEN
current_state <= QD;
ELSE
s_lg <='0';
current_state <= QA;
END IF;
启动状态是控制器模块的第4个状态，这时控制器将判断按键输入的具体信号：如果判断出按键输入是OPEN_T信号，那么将发出S_LG信号；如果判断出是数字按键输入，那么仍向编码模块发出DUS时钟。
WHEN QE => en <= '1'; dus <= '0';
anc<='0';
IF (data_in='1') THEN
dus <= '1';
ELSIF(c33='1') THEN
current_state <= QC;
reset <= '1';
ELSIF(c44='0') THEN
current_state <= QE;
ELSE
anc<='1';
current_state <= QF;
END IF;
当控制器处于这个状态时，如果按下READY键，那么控制器将发出复位信号RESET，并使控制器返回到密码输入状态：如果按下OPEN_T键，那么控制器将向误码模块发出ANC时钟，同时转移到报警状态；如果判断出是数字按键输入，那么向编码模块发出DUS时钟。
WHEN QF => IF (notc='1') THEN
s_lr <='0';
current_state <= QG;
ELSIF(dsw='1') THEN
current_state <= QB;
ELSE
ds <= '1';
current_state <= QF;
END IF;
当控制器处于这个状态时，这时控制器将判断NOTC信号是否有效，如果该信号有效，则表示密码输入错误次数已经达到3次，这时密码器将进入到死锁状态，同时控制器将转移到报警返回状态；如果NOTC信号无效，则向密码错误计数模块发出定时信号，这时指示设备将发出警告信号，这时任何按键输入都将不被响应；如果定时结束（4s）则，密码器将再次进入到准备就绪状态，这时允许再次输入密码。
WHEN QG => en <= '0';
IF (c22='0') THEN
current_state <= QG;
ELSE
current_state <= QA;
s_lr <= '1';
wait_l <= '0';
END IF;
END CASE;
END PROCESS;
报警返回状态是控制器模块的最后一个状态，这是密码器将判断输入的具体信号：如果按下SETUP信号，那么控制器模块将返回到密码建立等待状态；如果按下其他键，那么状态将不会发生变化。
END control_model_arch;