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CDB42406中文资料

CDB42406中文资料
CDB42406中文资料

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Copyright Cirrus Logic, Inc. 2003

(All Rights Reserved)

Cirrus Logic, https://www.wendangku.net/doc/3b8404904.html,

CDB42406

Evaluation Board For CS42406

Features

Single-ended analog inputs and outputs CS8406 S/PDIF digital audio transmitter CS8416 S/PDIF digital audio receiver Header for optional external configuration of

CS42406

Header for external DSP serial audio I/O 3.3 V to 5.0 V Logic Interface

14 Pre-defined Board Setup Options Demonstrates recommended layout and grounding arrangements

Windows compatible software interface to configure CS42406 and intra-board connections

ORDERING INFORMATION

CDB42406

Evaluation Board

Description

The CDB42406 demonstration board is an excellent means for evaluating the CS42406 CODEC. Evaluation requires an analog/digital signal source and analyzer,and power supplies. Optionally, a Windows PC compat-ible computer may be used to evaluate the CS42406DAC in control port mode.

System timing can be provided by the CS42406, by the CS8416 phase-locked to its S/PDIF input, by an I/O stake header or by an on-board oscillator. RCA phono jacks are provided for the CS42406 analog outputs and inputs. Digital data I/O is available via RCA phono or op-tical connectors to the CS8416 and CS8406. 14 pre-defined board setup options are selectable using a 4-po-sition DIP switch.

The Windows software provides a GUI to make configu-ration of the DAC easy. The software communicates through the PC’s parallel port to configure the control port registers so that all features of the CS42406 can be evaluated. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development.

AUG ‘03DS614DB1

TABLE OF CONTENTS

1. SYSTEM OVERVIEW (4)

1.1 CS42406 Stereo Audio CODEC (4)

1.2 CS8406 Digital Audio Transmitter (4)

1.3 CS8416 Digital Audio Receiver (4)

1.4 Canned Oscillator (5)

1.5 Analog Input (5)

1.6 Analog Outputs (5)

1.7 CPLD Board Setup (5)

1.7.1 S/PDIF IN & S/PDIF OUT (Setup 0 - Setup 2) (6)

1.7.1a Setup 0 (6)

1.7.1b Setup 1 (7)

1.7.1c Setup 2 (7)

1.7.2 Digital Loopback (Setup 3 - Setup 6) (8)

1.7.2a Setup 3 (8)

1.7.2b Setup 4 (9)

1.7.2c Setup 5 (9)

1.7.2d Setup 6 (10)

1.7.3 DSP Routing (10)

1.7.3a Setup 7 (11)

1.7.3b Setup 8 (11)

1.7.3c Setup 9 (12)

1.7.3d Setup 10 (12)

1.7.3e Setup 11 (13)

1.7.3f Setup 12 (14)

1.7.4 No Routing (14)

1.8 Stand-Alone Control (15)

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to https://www.wendangku.net/doc/3b8404904.html,

IIMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is sub-ject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and con-ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsi-bility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT-ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM-ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-marks or service marks of their respective owners.

I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.

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1.9 PC Parallel Port Control (15)

1.10 External Control Headers (15)

1.11 Power (16)

1.12 Grounding and Power Supply Decoupling (16)

2. BLOCK DIAGRAM (19)

3. SCHEMATICS (20)

4. LAYOUT (30)

LIST OF FIGURES

Figure 1. S/PDIF IN/OUT - Setup 0 (6)

Figure 2. S/PDIF IN/OUT - Setup 1 (7)

Figure 3. S/PDIF IN/OUT - Setup 2 (7)

Figure 4. Digital Loopback - Setup 3 (8)

Figure 5. Digital Loopback - Setup 4 (9)

Figure 6. Digital Loopback - Setup 5 (9)

Figure 7. Digital Loopback - Setup 6 (10)

Figure 8. DSP Routing - Setup 7 (11)

Figure 9. DSP Routing - Setup 8 (11)

Figure 10. DSP Routing - Setup 9 (12)

Figure 11. DSP Routing - Setup 10 (12)

Figure 12. DSP Routing - Setup 11 (13)

Figure 13. DSP Routing - Setup 12 (14)

Figure 14. No Routing (14)

Figure 15. Block Diagram (19)

Figure 16. CS42406 (20)

Figure 17. S/PDIF Input (21)

Figure 18. S/PDIF Output (22)

Figure 19. CPLD (23)

Figure 20. Analog Input (24)

Figure 21. Ch. 1 Analog Output (25)

Figure 22. Ch. 2 Analog Output (26)

Figure 23. Ch. 3 Analog Output (27)

Figure 24. DAC Control Port and I/O Headers (28)

Figure 25. Power (29)

Figure 26. Silk Screen (30)

Figure 27. Topside Layer (31)

Figure 28. Bottomside Layer (32)

LIST OF TABLES

Table 1. System Connections (17)

Table 2. Jumper/Switch Settings (18)

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1.SYSTEM OVERVIEW

The CDB42406 demonstration board is an excellent means for evaluating the CS42406 stereo CODEC.Analog and digital audio signal interfaces are provided, as well as a DB-25 computer parallel port interface for use with the supplied Windows configuration software.

The CDB42406 schematic set has been partitioned into 10 pages and is shown in Figures16 through25.

1.1CS42406 Audio CODEC

A complete description of the CS42406 is included in the CS42406 product data sheet.

1.2CS8406 Digital Audio Transmitter

The operation of the CS8406 transmitter (see Figure 18) and a discussion of the digital audio interface are included in the CS8406 data sheet.

The CS8406 converts the PCM data generated by the CS42406 to the standard S/PDIF data stream. The CS8406 operates in slave mode and only accepts a 256Fs master clock on the OMCK input pin. The serial audio input data for the CS8406 is received from the serial audio output of the CS42406. Digital Interface format selection of either Left Justified or I2S can be made via the I2S/LJ position on switch S3 (see Table2 for switch control options).

1.3CS8416 Digital Audio Receiver

The operation of the CS8416 receiver (see Figure 17) and a discussion of the digital audio interface are included in the CS8416 data sheet.

The CS8416 converts the input S/PDIF data stream into PCM data for the CS42406. The CS8416 operates in master mode only. Digital Interface format selection of either Left Justi-fied or I2S can be made via the I2S or LJ position on S1(see Table2 for switch control op-tions).

The CS8416 contains an internal input multiplexer which must be set to receive the appropri-ate stream from the Optical or Coaxial input connector. This is done via the Coaxial or Optical position on switch S1.

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1.4Canned Oscillator

Oscillator Y1 provides a System Clock. This clock can be routed through the CS8416 out the RMCK pin when the S/PDIF input is disconnected (refer to the CS8416 data sheet for details on OMCK operation). To use the canned oscillator as the source of the MCLK signal, select from one of the pre-defined options, detailed in section 1.7, using the SW[3:0] positions on switch S4.

The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with a 12.2880MHz crystal oscillator stuffed at Y1.

1.5Analog Input

RCA connectors supply the CS42406 analog inputs through unity gain, AC-coupled single-ended circuits. A 1 Vrms single-ended signal will drive the CS42406 inputs to full scale.

1.6Analog Outputs

The CS42406 analog outputs are routed through a single-pole RC filter. The corner frequen-cy can be extended to 190 kHz by simply removing one of the 1500 pF filter capacitors. 1.7CPLD Board Setup

The CPLD (U9) controls all digital signal routing between the CS42406, CS8416, CS8406, AUDIO MCLK (Y1), and DSP I/O HDR. The user may choose from 14 clock/data routing op-tions by setting certain combinations of switch S4. See sections 1.7.1 through 1.7.4 for a de-scription of each mode. Any combination can be realized in either stand-alone or control port mode.

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1.7.1S/PDIF IN & S/PDIF OUT (Setup 0 - Setup 2)

There are 3 different setup options for routing MCLK, LRCK and SCLK for S/PDIF input and output conversion. These options allow the user to choose between 3 different mas-ters for the ADC subclocks. Should the CS8416 lose lock to the S/PDIF input, the RMCK will automatically switch from the PLL to the OMCK input (see the CS8416 datasheet for details). The CS8406 is always clocked from the same source as the ADC.

1.7.1a Setup 0

Using the recovered clock from the S/PDIF input data stream, the CS8416 masters all clocks for the ADC and all clocks and data for the DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0000’b.

Figure 1. S/PDIF IN/OUT - Setup 0

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1.7.1b Setup 1

Using the recovered clock from the S/PDIF input data stream, the CS8416 masters MCLK, subclocks and data for the DAC. A DSP connected to the DSP I/O HDR masters the sub-clocks for the ADC and CS8406. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0001’b.

Figure 2. S/PDIF IN/OUT - Setup 1

1.7.1c Setup 2

Using the recovered clock from the S/PDIF input data stream, the CS8416 masters MCLK, subclocks and data for the DAC. The ADC masters its own subclocks. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0010’b.

Figure 3. S/PDIF IN/OUT - Setup 2

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1.7.2Digital Loopback (Setup 3 - Setup 6)

There are 4 different setup options for routing MCLK, LRCK and SCLK for digital loop-back. These setup configurations allow analog input/output analysis without the need for

a digital signal analyzer/source. These options also allow the user to choose between 2

different MCLK and 2 different subclock sources for the ADC/DAC.

1.7.2a Setup 3

Using the on-board crystal oscillator, AUDIO MCLK, the CS42406 ADC masters the sub-clocks and data for the DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0011’b.

Figure 4. Digital Loopback - Setup 3

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1.7.2b Setup 4

Using the on-board crystal oscillator, AUDIO MCLK, a DSP connected to DSP I/O HDR masters the subclocks for the ADC/DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0100’b.

Figure 5. Digital Loopback - Setup 4

1.7.2c Setup 5

Using the master clock from an external DSP connected to the DSP I/O HDR, DSP_MCLK, the CS42406 ADC masters the subclocks and data for the DAC. For imple-mentation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0101’b.

Figure 6. Digital Loopback - Setup 5

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1.7.2d Setup 6

An external DSP connected to DSP I/O HDR, masters all clocks for the ADC/DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0110’b.

Figure 7. Digital Loopback - Setup 6

1.7.3DSP Routing

There are 6 different setup options for routing MCLK, LRCK and SCLK for DSP control.

These options allow either shared or independent control over the subclocks for the DAC and ADC. The user may also choose between 2 different MCLK sources.

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1.7.3a Setup 7

An external DSP connected to DSP I/O HDR masters all clocks for the ADC/DAC and pro-vides data to the DAC. Subclocks for the ADC/DAC are input via DSP_ADC_LRCK and DSP_ADC_SCLK. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0111’b.

Figure 8. DSP Routing - Setup 7

1.7.3b Setup 8

Using the on-board crystal oscillator, AUDIO MCLK, a DSP connected to DSP I/O HDR masters the subclocks for the ADC/DAC and provides data to the DAC. Subclocks for the ADC/DAC are input via DSP_ADC_LRCK and DSP_ADC_SCLK. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘1000’b.

Figure 9. DSP Routing - Setup 8

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1.7.3c Setup 9

Using the on-board crystal oscillator, AUDIO MCLK, a DSP connected to DSP I/O HDR masters the subclocks for the ADC/DAC and provides data to the DAC. Subclocks for the ADC are input via DSP_ADC_LRCK and DSP_ADC_SCLK while subclocks for the DAC are input via DSP_DAC_LRCK and DSP_DAC_SCLK. This allows independent control of the sample rate for the ADC and DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘1001’b.

Figure 10. DSP Routing - Setup 9

1.7.3d Setup 10

A DSP connected to DSP I/O HDR masters all clocks for the ADC/DAC and provides data

to the DAC. Subclocks for the ADC are input via DSP_ADC_LRCK and DSP_ADC_SCLK while subclocks for the DAC are input via DSP_DAC_LRCK and DSP_DAC_SCLK. This allows independent control of the sample rate for the ADC and DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘1010’b.

Figure 11. DSP Routing - Setup 10

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1.7.3e Setup 11

Using the on-board crystal oscillator, AUDIO MCLK, a DSP connected to DSP I/O HDR masters the subclocks for the DAC and provides data to the DAC. Using the on-board crystal oscillator, AUDIO MCLK, the CS42406 ADC masters its subclocks and are output onto DSP_ADC_LRCK and DSP_ADC_SCLK. The subclocks for the DAC are input via DSP_DAC_LRCK and DSP_DAC_SCLK. This allows independent control of the sample rate for the ADC and DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘1011’b.

Figure 12. DSP Routing - Setup 11

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1.7.3f Setup 12

A DSP connected to DSP I/O HDR masters all clocks for the DAC and provides data to

the DAC. Using a DSP connected to DSP I/O HDR, the CS42406 ADC masters its sub-clocks and are output onto DSP_ADC_LRCK and DSP_ADC_SCLK. The subclocks for the DAC are input via DSP_DAC_LRCK and DSP_DAC_SCLK. This allows independent control of the sample rate for the ADC and DAC. For implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘1100’b.

Figure 13. DSP Routing - Setup 12

1.7.4No Routing

The remaining setup options will tri-state all clock/data output on the CPLD with the ex-ception of the ADC_SDOUT from the CS42406 to the inputs of the CS8406 and DSP_I/O_HDR.

Figure 14. No Routing

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1.8Stand-Alone Control

Switches S1-S4 allow signal routing and configuration of the CDB42406. Switch S1 controls the interface format of the CS8416 and allows selection between the OPTICAL and COAXIAL S/PDIF inputs. The DAC portion of the CS42406 may operate in either stand-alone (config-ured using switch S2) or control port mode (configured via the PC Parallel Port through a graphical user interface). The ADC portion of the CS42406 operates in stand-alone mode at all times and must be configured using switch S3. Switch S4 controls the routing of all clocks and data. See section1.7 for a list of the various stand-alone options available. After setting any of these switches, the user must assert a reset by pressing the RESET button (S5). Operation in stand-alone mode requires the parallel port cable to remain disconnected from the DB-25 connector (J24). Connecting a cable to the connector will enable the PC control port, automatically disabling various controls on switch S2.

1.9PC Parallel Port Control

A graphical user interface is included with the CDB42406 to allow easy manipulation of the DAC registers of the CS42406. Connecting a cable to the DB-25 connector (J24) will enable the PC control port, automatically disabling various controls on switch S2.

1.10External Control Headers

The evaluation board has been designed to allow interfacing with external systems via the headers J15 and J26.

The 32-pin header, J15, provides access to the serial audio signals required to interface with a DSP (see Figure24). These signals are routed based on the setting of switch S4. See “CPLD Board Setup” in section1.7 for various setup options for DSP routing.

The 6-pin header, J26, allows the user bidirectional access to the SPI/I2C control signals. The signals on J26 default to outputs. When a cable is connected to the DB-25 connector (J24), the header (J26) may be used as an input. In this case, the control signals on J26 are routed to the corresponding control pins on the CS42406 and external control signals may be ap-plied.

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1.11Power

Power must be supplied to the evaluation board through at least the +5.0V binding post, (J1). Jumpers J3 and J6 connect the VD and VA supply, respectively, to a fixed +5.0V or +3.3V supply or to two separate binding posts (J4 and J7) for variable voltage settings.

Jumper J5 allows the user to connect the VLS and VLC supplies of the CS42406 to a fixed +5.0V or +3.3V supply. All voltage inputs must be referenced to the single black banana-type ground connector (see Figure25).

WARNING:Please refer to the CS42406 data sheet for allowable voltage levels.

1.12Grounding and Power Supply Decoupling

The CS42406 requires careful attention to power supply and grounding arrangements to op-timize performance. Figure15 provides an overview of the connections to the CS42406, Figure26 shows the component placement, Figure27 shows the top layout, and Figure28 shows the bottom layout. The decoupling capacitors are located as close to the CS42406 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.

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CONNECTOR Reference

Designator INPUT/OUTPUT SIGNAL PRESENT

+5V J1Input+5.0V Power Supply

GND J2Input Ground Reference

VD J4Input+3.3V to +5.0V Variable Power Supply for VD

VA J7Input+3.3 V to +5.0V Variable Power Supply for VA

RX-COAX J10Input CS8416 digital audio input via coaxial cable

RX-OPT OPT1Input CS8416 digital audio input via optical cable

TX-COAX J18Output CS8406 digital audio output via coaxial cable

TX-OPT OPT2Output CS8406 digital audio output via optical cable

PC Port J24Input/Output Parallel connection to PC for SPI / I2C control port signals DSP HEADER J15Input/Output I/O for Clocks & Data

EXT CTRL I/O J26Input/Output I/O for external SPI / I2C control port signals.

AINL AINR J25

J27

Input RCA phono jacks for analog input signal to CS42406

AOUTA1 AOUTB1 AOUTA2 AOUTB2 AOUTA3 AOUTB3

J8

J11

J13

J16

J19

J22

Output RCA phono jacks for analog outputs

Table 1. System Connections

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JUMPER /

SWITCH PURPOSE IDENTIFIER POSITION FUNCTION SELECTED

S/PDIF In Setup (S1)Optical or Coaxial S/PDIF

Input Select

-*OPTICAL

COAXIAL

Optical Input

Coaxial Input

S/PDIF In Setup (S1)I2S or Left Justified

Input Select

-*LJ

I2S

Left Justified S/PDIF Input

I2S S/PDIF Input

J3Selects source of voltage

for the VD supply -VD_IN

+3.3V

*+5V

Voltage source is J4 binding post

Voltage source is +3.3V regulator

Voltage source is +5V regulator

J5Selects source of voltage

for the VLS and VLC sup-

plies -+3.3V

*+5V

Voltage source is +3.3 V regulator

Voltage source is +5V binding post (J1)

J6Selects source of voltage

for the VA supply -VA_IN

+3.3V

*+5V

Voltage source is J7 binding post

Voltage source is +3.3V regulator

Voltage source is +5V binding post (J1)

DAC SETUP

(S2)DAC Speed Mode Select DAC_Mx*00

01

10

11

Single-Speed Mode, w/out De-emphasis

Single-Speed Mode, with De-emphasis

Double-Speed Mode

Quad-Speed Mode

DAC SETUP

(S2) Interface Format Select DIFx*00

01

10

11

Left Justified, up to 24-bit data

I2S, up to 24-bit data

Right Justified 16-bit data

Right Justified 24-bit data

DAC SETUP

(S2)Resets DAC

RST_DAC

*1

DAC reset is enabled

DAC reset is disabled

ADC SETUP

(S3)ADC Speed Mode Select ADC_Mx00

01

10

*11

Clock Master, Single-Speed Mode

Clock Master, Double-Speed Mode

Clock Master, Quad-Speed Mode

Clock Slave, All Speed Modes

ADC SETUP

(S3)MCLK/LRCK Ratio Select

384x/256x

*0

1

MCLK/LRCK ratio is 256

MCLK/LRCK ratio is 384

ADC SETUP

(S3)ADC and CS8406 Inter-

face Format Selection

I2S/LJ

*1

Left Justified, up to 24-bit data

I2S, up to 24-bit data

ADC SETUP

(S3)Powerdown ADC

PDN_ADC

*1

ADC is powered down

ADC is powered up

J9, J12, J14, J17, J20, J23Mute Circuit Connection-*Shunted

Open

Connects Mute Circuit to AOUTxx

Disconnects Mute Circuit from AOUTxx

*Default factory settings

Table 2. Jumper/Switch Settings

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2.BLOCK DIAGRAM

F i g u r e 15. B l o c k D i a g r a m

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