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cd74hc283

Data sheet acquired from Harris Semiconductor

SCHS176D Features ?Adds Two Binary Numbers ?Full Internal Lookahead ?Fast Ripple Carry for Economical Expansion ?Operates with Both Positive and Negative Logic ?Fanout (Over Temperature Range)-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads -Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads ?Wide Operating Temperature Range . . .-55o C to 125o C ?Balanced Propagation Delay and Transition Times ?Signi?cant Power Reduction Compared to LSTTL Logic ICs ?HC Types -2V to 6V Operation -High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V ?HCT Types - 4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility,

V IL = 0.8V (Max), V IH = 2V (Min)

-CMOS Input Compatibility, I l ≤1μA at V OL , V OH Description

The ’HC283and ’HCT283binary full adders add two 4-bit

binary numbers and generate a carry-out bit if the sum

exceeds 15.

Because of the symmetry of the add function,this device

can be used with either all active-high operands (positive

logic)or with all active-low operands (negative logic).When

using positive logic the carry-in input must be tied low if there

is no carry-in.Ordering Information PART NUMBER TEMP. RANGE (o C)PACKAGE CD54HC283F3A -55 to 12516 Ld CERDIP CD54HCT283F3A -55 to 12516 Ld CERDIP CD74HC283E -55 to 12516 Ld PDIP CD74HC283M -55 to 12516 Ld SOIC CD74HC283MT -55 to 12516 Ld SOIC CD74HC283M96-55 to 12516 Ld SOIC CD74HCT283E -55 to 12516 Ld PDIP CD74HCT283M -55 to 12516 Ld SOIC CD74HCT283MT

-55 to 12516 Ld SOIC CD74HCT283M96-55 to 12516 Ld SOIC

NOTE:When ordering,use the entire part number.The suf?x 96

denotes tape and reel.The suf?x T denotes a small-quantity reel of

250.

Pinout

CD54HC283, CD54HCT283

(CERDIP)

CD74HC283, CD74HCT283

(PDIP , SOIC)

TOP VIEW

Functional Diagram 1415169131211101

8S1B1A1S0A0B0GND C IN V CC A2S2A3B3S3C OUT B256321511121449S2S1A0B0A1B1B2A3B3A27C IN GND = 8

V CC = 16

10131S0

S3C OUT November 1997 - Revised October 2003CD54HC283, CD74HC283,CD54HCT283, CD74HCT283

High-Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry

[ /Title (CD74HC283,CD74HCT28

/Sub-

ject

(High

Speed

CMOS

Logic

4-Bit

Binary

Full

Adder

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, V CC. . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7V DC Input Diode Current, I IK

For V I < -0.5V or V I > V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, I OK

For V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, I O

For -0.5V < V O < V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, I O

For V O > -0.5V or V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC V CC or Ground Current, I CC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions

Temperature Range, T A . . . . . . . . . . . . . . . . . . . . . .-55o C to 125o C Supply Voltage Range, V CC

HC T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, V I, V O . . . . . . . . . . . . . . . . .0V to V CC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400ns (Max)Thermal Resistance (T ypical, Note 1)θJA (o C/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .73 Maximum Junction T emperature. . . . . . . . . . . . . . . . . . . . . . .150o C Maximum Storage Temperature Range . . . . . . . . . .-65o C to 150o C Maximum Lead T emperature (Soldering 10s). . . . . . . . . . . . .300o C (SOIC - Lead Tips Only)

CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied.

NOTE:

1.The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speci?cations

PARAMETER SYMBOL

TEST

CONDITIONS V

(V)

25o C-40o C TO 85o C-55o C TO125o C

UNITS V I(V)I O(mA)MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input Voltage V IH--2 1.5-- 1.5- 1.5-V

4.5 3.15-- 3.15 - 3.15-V

6 4.2-- 4.2- 4.2-V

Low Level Input Voltage V IL--2--0.5-0.5-0.5V

4.5-- 1.35- 1.35- 1.35V

6-- 1.8- 1.8- 1.8V

High Level Output Voltage

CMOS Loads V OH V IH or V IL-0.022 1.9-- 1.9- 1.9-V -0.02 4.5 4.4-- 4.4 - 4.4-V

-0.026 5.9-- 5.9- 5.9-V

High Level Output Voltage

TTL Loads

---------V -4 4.5 3.98-- 3.84- 3.7-V -5.26 5.48-- 5.34- 5.2-V

Low Level Output Voltage

CMOS Loads V OL V IH or V IL0.022--0.1-0.1-0.1V

0.02 4.5--0.1-0.1-0.1V

0.026--0.1-0.1-0.1V

Low Level Output Voltage

TTL Loads

---------V

4 4.5--0.26-0.33-0.4V

5.26--0.26-0.33-0.4V

Input Leakage Current I I V CC or

GND

-6--±0.1-±1-±1μA

Quiescent Device Current I CC V CC or

GND

06--8-80-160μA

HCT Types

High Level Input

Voltage

V IH -- 4.5 to 5.52--2-2-V Low Level Input

Voltage

V IL -- 4.5 to 5.5--0.8-0.8-0.8V High Level Output

Voltage

CMOS Loads

V OH V IL or V IH -0.02 4.5 4.4-- 4.4- 4.4-V High Level Output

Voltage

TTL Loads

V OH V IL or V IH -4 4.5 3.98-- 3.84- 3.7-V Low Level Output

Voltage

CMOS Loads

V OL V IH or V IL 0.02 4.5--0.1-0.1-0.1V Low Level Output

Voltage

TTL Loads

V OL V IH or V IL 4 4.5--0.26-0.33-0.4V Input Leakage

Current

I I V CC to GND - 5.5--±0.1-±1-±1μA Quiescent Device

Current

ICC V CC or GND - 5.5--8-80-160μA Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

?I CC (Note 2)V CC - 2.1- 4.5 to 5.5-100360-450-490μA

NOTE:

2.For dual-supply systems theoretical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA.DC Electrical Speci?cations (Continued)

PARAMETER

SYMBOL TEST

CONDITIONS

V CC (V)25o C -40o C TO 85o C -55o C TO 125o C UNITS V I (V)I O (mA)MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table

INPUT

UNIT LOADS C IN

1.5B1, A1, A0

1B0

0.4B3, A3, A2, B20.5

NOTE:Unit Load is ?I CC limit speci?ed in DC Electrical

Speci?cations table, e.g., 360μA max at 25o C.

Switching Speci?cations Input t r , t f = 6ns

PARAMETER SYMBOL TEST

CONDITIONS

V CC (V)25o C -40o C TO 85o C -55o C TO 125o C UNITS MIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay t PLH,t PHL

C L = 50pF

2--160-200-240ns C IN to S0 4.5--32-40-48ns C L = 15pF

5-13-----ns C L = 50pF 6--27-34-41ns

C IN to S1t PLH,t PHL C L = 50pF

--180-225-270ns 4.5

--36-45-54ns C L = 15pF

5-15-----ns C L = 50pF

6--31-38-46ns C IN to S2, C IN to C OUT t PLH,t PHL C L = 50pF

2--195-245-295ns 4.5--39-49-59ns C L = 15pF

5-16-----ns C L = 50pF

6--33-42-50ns C IN to S3t PLH,t PHL C L = 50pF

2--230-290-345ns 4.5--46-58-69ns C L = 15pF

5-19-----ns C L = 50pF

6--39-49-59ns An, Bn to C OUT t PLH,t PHL C L = 50pF

2--195-245-295ns 4.5--39-49-59ns C L = 15pF

5-16-----ns C L = 50pF

6--33-42-50ns An, Bn to Sn t PLH,t PHL C L = 50pF

2--210-265-315ns 4.5--42-53-63ns C L = 15pF

5-18-----ns C L = 50pF

6--36-45-54ns Output Transition Time t TLH , t THL C L = 50pF 2

--75-95-110ns 4.5

--15-19-22ns 6

--13-16-19ns Input Capacitance

C IN C L = 50pF ---10-10-10pF Power Dissipation

Capacitance, (Notes 3, 4)

C P

D -5-70-----pF HCT TYPES

Propagation Delay

C IN to S0

t PLH , t PHL C L = 15pF 5-13-----ns C L = 50pF 4.5--31-39-47ns C IN to S1

t PLH , t PHL C L = 15pF 5-18-----ns C L = 50pF 4.5-43-54-65ns C IN to S2, C IN to C OUT

t PLH , t PHL C L = 15pF 5-19-----ns C L = 50pF 4.5-46-58-69ns C IN to S3

t PLH , t PHL C L = 15pF 5-22-----ns C L = 50pF 4.5-53-66-80ns An, Bn to C OUT

t PLH ,t PH L C L = 15pF 5-20-----ns C L = 50pF 4.5-48-60-72ns An, Bn to Sn t PLH , t PHL

C L = 15pF 5-21-----ns C L = 50pF 4.5-49-61-74ns Output Transition Time t TLH , t THL C L = 50pF 4.5-15-19-22ns PARAMETER SYMBOL TEST CONDITIONS V CC (V)

25o C

85o C 125o C UNITS MIN TYP MAX MIN MAX MIN MAX

Input Capacitance C IN --

--10-10-10pF Power Dissipation

Capacitance, (Notes 3, 4)

C P

D -

5-82-----pF NOTES:3.C PD is used to determine the dynamic power consumption, per package.

4.P D = V CC 2 f i (C PD + C L ) where: f i = Input Frequency, C L = Output Load Capacitance, V CC = Supply Voltage.

PARAMETER SYMBOL TEST CONDITIONS V CC (V)

25o C

85o C 125o C UNITS MIN TYP MAX MIN MAX MIN MAX Test Circuits and Waveforms

FIGURE 1.HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 2.HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

t PHL t PLH t THL t TLH

90%

50%

10%

50%

10%

INVERTING OUTPUT

INPUT GND V CC t r = 6ns

t f = 6ns 90%

t PHL t PLH t THL t TLH 2.7V 1.3V 0.3V 1.3V 10%INVERTING OUTPUT INPUT GND 3V t r = 6ns t f = 6ns 90%

PACKAGING INFORMATION

Orderable Device Status(1)Package

Type Package

Drawing

Pins Package

Qty

Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)

5962-8976501EA ACTIVE CDIP J161TBD A42N/A for Pkg Type CD54HC283F3A ACTIVE CDIP J161TBD A42N/A for Pkg Type CD54HCT283F3A ACTIVE CDIP J161TBD A42N/A for Pkg Type CD74HC283E ACTIVE PDIP N1625Pb-Free

(RoHS)

CU NIPDAU N/A for Pkg Type

CD74HC283EE4ACTIVE PDIP N1625Pb-Free

(RoHS)

CU NIPDAU N/A for Pkg Type

CD74HC283M ACTIVE SOIC D1640Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283M96ACTIVE SOIC D162500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283M96E4ACTIVE SOIC D162500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283M96G4ACTIVE SOIC D162500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283ME4ACTIVE SOIC D1640Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283MG4ACTIVE SOIC D1640Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283MT ACTIVE SOIC D16250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283MTE4ACTIVE SOIC D16250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HC283MTG4ACTIVE SOIC D16250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283E ACTIVE PDIP N1625Pb-Free

(RoHS)

CU NIPDAU N/A for Pkg Type

CD74HCT283EE4ACTIVE PDIP N1625Pb-Free

(RoHS)

CU NIPDAU N/A for Pkg Type

CD74HCT283M ACTIVE SOIC D1640Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283M96ACTIVE SOIC D162500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283M96E4ACTIVE SOIC D162500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283M96G4ACTIVE SOIC D162500Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283ME4ACTIVE SOIC D1640Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283MG4ACTIVE SOIC D1640Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283MT ACTIVE SOIC D16250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283MTE4ACTIVE SOIC D16250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD74HCT283MTG4ACTIVE SOIC D16250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows:

ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.

(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check https://www.wendangku.net/doc/359438990.html,/productcontent for the latest availability information and additional product content details.

TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.

Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)

(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Type Package Drawing

Pins

SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD74HC283M96SOIC

D 162500330.016.4 6.510.3 2.18.016.0Q1CD74HCT283M96SOIC D 162500330.016.4 6.510.3 2.1

8.016.0Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD74HC283M96SOIC D162500333.2345.928.6 CD74HCT283M96SOIC D162500333.2345.928.6

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