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IS61LV256AL-10JL中文资料

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.A 03/17/06

IS61LV256AL

ISSI

Copyright ? 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

?High-speed access times:— 10 ns

?Automatic power-down when chip is deselected ?CMOS low power operation

— 60 μW (typical) CMOS standby — 65 mW (typical) operating ?TTL compatible interface levels ?Single 3.3V power supply

?Fully static operation: no clock or refresh required

?Three-state outputs ?Lead-free available

DESCRIPTION

The ISSI IS61LV256AL is a very high-speed, low power,

32,768-word by 8-bit static RAM. It is fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum.When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 150 μW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW Chip Enable (CE ). The active LOW Write Enable (WE ) controls both writing and reading of the memory.The IS61LV256AL is available in the JEDEC standard 28-pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages.

32K x 8 LOW VOLTAGE CMOS STATIC RAM

FUNCTIONAL BLOCK DIAGRAM

MARCH 2006

IS61LV256AL

ISSI

2Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.A 03/17/06

PIN CONFIGURATION

28-Pin SOJ

1234567891011121314

2827262524232221201918171615

A14A12A7A6A5A4A3A2A1A0I/O0I/O1I/O2GND

VDD WE A13A8A9A11OE A10CE I/O7I/O6I/O5I/O4I/O3

PIN CONFIGURATION

28-Pin TSOP (Type I)

PIN DESCRIPTIONS

A0-A14Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7Input/Output V DD Power GND

Ground

TRUTH TABLE

Mode

WE CE OE I/O Operation

V DD Current Not Selected X H X High-Z I SB 1, I SB 2

(Power-down)Output Disabled H L H High-Z I CC Read H L L D OUT I CC Write

D IN

I CC

ABSOLUTE MAXIMUM RATINGS (1)

Symbol Parameter

Value Unit V DD Power Supply Voltage Relative to GND –0.5 to +4.6V V TERM Terminal Voltage with Respect to GND –0.5 to +4.6V T STG Storage Temperature –65 to +150

°C P D Power Dissipation 1W I OUT

DC Output Current

±20

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IS61LV256AL ISSI?OPERATING RANGE

Range Ambient Temperature Speed (ns)V DD(1)

Commercial0°C to +70°C10 3.3V, +10%, –5%

Industrial–40°C to +85°C10 3.3V + 10%, –5%

Note: 1. If operated at 12ns, V DD range is 3.3V + 10%.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions M in.Max.Unit V OH Output HIGH Voltage V DD = Min., I OH = –2.0 mA 2.4—V V OL Output LOW Voltage V DD = Min., I OL = 4.0 mA—0.4V V IH Input HIGH Voltage 2.2V DD + 0.3V V IL Input LOW Voltage(1)–0.30.8V

I LI Input Leakage GND ≤ V IN≤ V DD Com.–11μA

Ind.–22

I LO Output Leakage GND ≤ V OUT≤ V DD, Outputs Disabled Com.–11μA

Ind.–22

Notes:

1.V IL (min.) = –0.3V (DC); V IL (min.) = –

2.0V (pulse width ≤ 2.0 ns).

V IH (max.) = V DD + 0.5V (DC); V IH (max.) = V DD + 2.0V (pulse width ≤ 2.0 ns).

2.Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Integrated Silicon Solution, Inc. — 1-800-379-47743 Rev.A

03/17/06

IS61LV256AL ISSI?POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)

-10 ns

Sym.Parameter Test Conditions Min.Max.Unit

I CC1V DD O perating V DD = Max., CE = V IL Com.—20m A

Supply C urrent I OUT = 0 mA, f = 1 MHz Ind.—25

I CC2V DD D ynamic O perating V DD = Max., CE = V IL Com.—30m A

Supply C urrent I OUT = 0 mA, f = f MAX Ind.—35

typ.(2) 20

I SB1TTL Standby Current V DD=M ax.,Com.—1m A

(TTL Inputs)V IN = V IH or V IL Ind.—1

CE≥V IH, f = 0

I SB2CMOS S tandby V DD=M ax.,Com.—40μA

Current (CMOS Inputs)CE≤V DD – 0.2V,Ind.—50

V IN≥V DD – 0.2V, or typ.(2) 2

V IN≤ 0.2V, f = 0

Notes:

1.At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

2. Typical values are measured at V DD =

3.3V, T A = 25o C and not 100% tested.

CAPACITANCE(1,2)

Symbol Parameter Conditions Max.Unit

C IN Input Capacitance V IN = 0V6pF

C OUT Output Capacitance V OUT = 0V5pF

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: T A = 25°C, f = 1 MHz, V DD =

3.3V.

4Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.A

03/17/06

IS61LV256AL ISSI?READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)

-10 ns-12 ns

Symbol Parameter Min.Max.Min.Max.Unit

t RC Read Cycle Time10—12—ns

t AA Address Access Time—10—12ns

t OHA Output Hold Time2—2—ns

t ACE CE Access Time—10—12ns

t DOE OE Access Time—5—5ns

t LZOE(2)OE to Low-Z Output0—0—ns

t HZOE(2)OE to High-Z Output—5—5ns

t LZCE(2)CE to Low-Z Output3—3—ns

t HZCE(2)CE to High-Z Output—5—6ns

t PU(3)CE to Power-Up0—0—ns

t PD(3)CE to Power-Down—10—12ns

Notes:

1.Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2.Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.

3.Not 100% tested.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level0V to 3.0V

Input Rise and Fall Times 3 ns

Input and Output Timing 1.5V

and Reference Levels

Output Load See Figures 1 and 2

AC TEST LOADS

Integrated Silicon Solution, Inc. — 1-800-379-47745 Rev.A

03/17/06

IS61LV256AL

ISSI

6Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.A 03/17/06

(1,3)

Notes:

1.WE is HIGH for a Read Cycle.

2.The device is continuously selected. OE , CE = V IL .

3.Address is valid prior to or coincident with CE LOW transitions.

AC WAVEFORMS READ CYCLE NO. 1(1,2)

IS61LV256AL

ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.A 03/17/06

AC WAVEFORMS

WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1)

WRITE CYCLE SWITCHING CHARACTERISTICS (1,2) (Over Operating Range)

-10 ns

-12 ns

Symbol

Parameter Min.

Max.

Min.Max.

Unit

t WC Write Cycle Time 10—12—ns t SCE CE to Write End 8—8—ns t AW Address Setup Time 8—8—ns to Write End t HA Address Hold 0—0—ns from Write End t SA Address Setup Time 0—0—ns t PWE 1WE Pulse Width (OE HIGH)7—8—ns t PWE 2WE Pulse Width (OE LOW)10—12—ns t SD Data Setup to Write End 6.5—7—ns t HD Data Hold from Write End 0—0—ns t HZWE (3)WE LOW to High-Z Output — 3.5—5ns t LZWE (3)

WE HIGH to Low-Z Output

—

Notes:

1.Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1.

2.The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.

3.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IS61LV256AL

ISSI

8Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.A 03/17/06

WRITE CYCLE NO. 2 (WE Controlled, OE is HIGH During Write Cycle) (1,2)

WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) (1)

1.The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.

2.I/O will assume the High-Z state if OE > V IH .

IS61LV256AL ISSI?DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min.Typ.(1)Max.Unit V DR V DD f or D ata R etention See D ata R etention W aveform 2.0 3.6V

I D R Data R etention C urrent V DD = 2.0V, CE≥V DD – 0.2V Com.—240μA

V IN≥ V DD – 0.2V, or V IN≤ V SS + 0.2V Ind.——50 t SDR Data R etention S etup T ime See D ata R etention W aveform0—ns t RDR Recovery Time See D ata R etention W aveform t RC—ns Note:

1. T ypical V alues a re m easured a t V DD=3.3V, T A=25o C a nd n ot 100% t ested.

DATA RETENTION WAVEFORM (CE Controlled)

Integrated Silicon Solution, Inc. — 1-800-379-47749 Rev.A

03/17/06

IS61LV256AL ISSI?

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed (ns)Order Part No.Package

10IS61LV256AL-10T TSOP - Type I

IS61LV256AL-10TL TSOP - Type I, Lead-free

IS61LV256AL-10J300-mil Plastic SOJ

IS61LV256AL-10JL300-mil Plastic SOJ, Lead-free

ORDERING INFORMATION

Industrial Range: –40°C to +85°C

Speed (ns)Order Part No.Package

10IS61LV256AL-10TI TSOP - Type I

IS61LV256AL-10TLI TSOP - Type I, Lead-free

IS61LV256AL-10JI300-mil Plastic SOJ

IS61LV256AL-10JLI300-mil Plastic SOJ, Lead-free

10Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.A

03/17/06

PACKAGING INFORMATION

ISSI

Integrated Silicon Solution, Inc. — https://www.wendangku.net/doc/3816793703.html, — 1-800-379-4774

Rev.D 02/25/03

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

300-mil Plastic SOJ Package Code: J

PACKAGING INFORMATION

ISSI

2Integrated Silicon Solution, Inc. — https://www.wendangku.net/doc/3816793703.html, — 1-800-379-4774

Rev. D 02/25/03

MILLIMETERS

INCHES Sym.

Min.Typ.Max.

N0.Leads 28A —— 3.56— —0.140A1 0.64——0.025 ——A2 2.41— 2.670.095—0.105b 0.41—0.510.016—0.020B 0.66—0.810.026—0.032C 0.20—0.250.008—0.010D 18.29—18.540.720—0.730E 8.26—8.760.325—0.345E17.49—7.75 0.295—0.305E2 6.27

—

7.29

0.247

—

0.287

1.27 BSC 0.050 BSC MILLIMETERS INCHES Sym.

Min.Typ.Max.

N0.Leads

32A —— 3.56—

—0.140A1 0.64——0.025 ——A2 2.41— 2.670.095—0.105b 0.41—0.510.016—0.020B 0.66—0.810.026—0.032C 0.20—0.250.008—0.010D 20.83—21.080.820—0.830E 8.26—8.760.325—0.345E17.49—7.75 0.295—0.305E2 6.27

—

7.29

0.247

—

0.287

1.27 BSC 0.050 BSC

300-mil Plastic SOJ Package Code: J

Plastic TSOP - 28-pins

Integrated Silicon Solution, Inc. PK13197T28 Rev. B 01/31/97