i.MX53 DDR Calibration
Freescale Semiconductor Application Note
Document Number:AN4466
Rev. 0, 02/2012
1 Introduction
The purpose of this document is to describe how to perform
various calibration processes on the i.MX53 Enhanced
DRAM Controller (ESDCTL) for use with DDR3 and
LPDDR2 memories. These calibration processes are needed
to fine tune various delay-line parameters in the ESDCTL for
optimal performance and functionality at the target
frequency of 400 MHz.
2DDR Calibration Modes
i.MX53 DDR interface supports the following nine
calibration processes:
?ZQ calibration—Change the values of on-chip
pull-up and pull-down resistors connected to the
VCC/2 pins. Unlike all other types of calibration
which take place only at the i.MX53 DDR port, ZQ
calibration is taking place in the DDR device side as
well.
?Write leveling calibration—In DDR3 mode, Set
DQS, DQ and DM signals of each data byte to their
common timing delay relative to the DDR CLK,
ADDR and Controls. This calibration is associated
with the DDR3 “fly-by” board topology, as described
by the JESD79-3E standard.Contents 1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.DDR Calibration Modes . . . . . . . . . . . . . . . . . . . . . . . https://www.wendangku.net/doc/3d18020079.html,ing Calibration for the Different DDR Standards . . 24.Calibration Over Frequency Range . . . . . . . . . . . . . . . 25.Calibration and Chip Selects . . . . . . . . . . . . . . . . . . . . 36.Source of Calibration Delay Values . . . . . . . . . . . . . . . https://www.wendangku.net/doc/3d18020079.html,ing the DDR Calibration Modes . . . . . . . . . . . . . . . 38.Delay Unit HW Overview . . . . . . . . . . . . . . . . . . . . . . 69.Address and Data Content Used for Timing Calibration 710.ZQ Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811.Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312.DQS Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813.Read DQS Delay Calibration . . . . . . . . . . . . . . . . . . . 2614.Write DQS Delay Calibration . . . . . . . . . . . . . . . . . . 3215.Write Data Bit Delay Calibration . . . . . . . . . . . . . . . 3616.Read Data Bit Delay Calibration . . . . . . . . . . . . . . . . 3717.Clock Delay Calibration . . . . . . . . . . . . . . . . . . . . . . 3718.CA-Bus Bit Delay Calibration . . . . . . . . . . . . . . . . . . 3719.DDR Calibration Code Examples . . . . . . . . . . . . . . . 3820.Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . 42
i.MX53 DDR Calibration
By Freescale Semiconductor, Inc.
Using Calibration for the Different DDR Standards
?DQS gating calibration—Optimize the timing of ESDCTL mask of the incoming DQS signal during read access.
?Write data DQS calibration—Set DQS output of each data byte to its delay relative to this byte DQ and DM outputs.
?Read data DQS calibration—Set DQS input of each data byte to its delay relative to this byte DQ inputs.
?Write data bit delay calibration—Additional delay for each output data bit.
?Read data bit delay calibration—Additional delay for each input data bit.
?Clock Signal delay calibration—Additional delay for the SDCLK and SDCLK_B signals.
?CA-Bus bit delay calibration—In LPDDR2 mode, additional delay is available for each bit of the command/address CA-bus.
3Using Calibration for the Different DDR Standards
3.1DDR2
Setting the i.MX53 to DDR2, the above calibration processes should be considered, with the exception of write leveling calibration and CA-Bus bit delay calibration,who are associated with other DDR standards. Although ODT activation is not typical for DDR2, it should be noted that the ZQ calibration is recommended for setting the right VCC/2 bias for the DDR2 signals.
3.2DDR3
Setting the i.MX53 to DDR3, the above calibration processes should be considered, with the exception of CA-Bus bit delay calibration, which is associated with other DDR standards.
3.3LPDDR2
Setting the i.MX53 to LPDDR2, the above calibration processes should be considered, with the exception of DQS gating calibration and write leveling calibration, which is associated with other DDR standards. 4Calibration Over Frequency Range
Calibration, as any other aspect of the DDR setup, is frequency dependant. Changing DDR clock frequency requires running the various calibration sequences and obtaining new set of delay values.
The empirical rule is that a DDR setup for a target frequency, including a measured set of delay values at that frequency, is expected to be stable at the frequency range of ±10% around this point.
Calibration and Chip Selects 5Calibration and Chip Selects
The user has the option of populating DDR memory devices on chip select 0 (CS0), chip select 1 (CS1), or both chip selects. HW calibration sequences, as described in this document, only use CS0 domain. For DDR devices connected to CS1, the user should take the following step to get a valid calibration results:?CS1 DDR device placement and route should be in a strict mirroring to layout of the CS0 devices.
This board design rule is important for a common set of delay values, as well as several other
aspects of the DDR port stability. Keeping this, and the delay values received from CS0 HW
calibration, can be used for CS1 operation as well.
?If calibrating explicitly for CS1 is still required (for example, DDRs are populated only on CS1), user can apply SW calibration sequence, making sure the addresses used in the SW flow are at the CS1 domain.
6Source of Calibration Delay Values
Each of the Calibration parameters of Section2, “DDR Calibration Modes,” is supported by register/s in ESDCTL that hold its delay values. Source of delay values might be:
?Analysis of board features and layout.
?Trial and error run of different delay values, using a selected DDR test pattern.
?Iterative calibration sequence to select the best delay values, based on ESDCTL logics.
While first two methods are supported for all calibration parameters, the iterative calibration sequence is only provided for:
?ZQ calibration
?Write leveling calibration
?DQS gating calibration
?Read data DQS calibration
?Write data DQS calibration
7Using the DDR Calibration Modes
7.1Calibration Usage General Notes
?Calibration sequence should be executed after the DDR memory has been initialized.
?Calibration sequence should be executed by code mounted on the internal RAM of the i.MX and not on the external DDR device, as calibration sequence activity might interfere with program
fetch.
7.2ZQ Calibration Usage
Variations of the ZQ resistors values are mainly due to IC process and environmental (temperature and voltage) variations.Repeating auto-initialized ZQ calibration sequence by i.MX53 logic is thus a must for
Using the DDR Calibration Modes
proper DDR operation, and should be completed by one-time forced ZQ calibration, as described in the following sections.
7.2.1Calibrating Local ZQ Versus DDR Device ZQ
ZQ calibration is done in both i.MX53 DDR PHY and the DDR device. Control bits ZQ_MODE[1:0] should be set in order to determine the activation events of the local and distant ZQ resistors.
7.2.2One Time Forced HW ZQ Calibration
Both local i.MX53 DDR PHY and the DDR device ZQ calibrations can be performed as a one-time event, by setting a bit in ESDCTL register.
One-time HW ZQ calibration mode is recommended as part of the DDR setup before initiating any other DDR activity. In particular, forcing a one-time ZQ calibration and waiting its completion, is required before any other calibration process describe in this document.
7.2.3Auto Initialized ZQ HW Calibration
In addition, the local i.MX53 DDR PHY and the DDR device ZQ HW controlled calibrations can be auto initialized by the ESDCTL, upon the following events:
?i.MX53 power up
?Exiting DDR self refresh mode
?Exiting slow precharge power down
?Periodic ZQ calibration sequence, with period time configured to ESDCTL register
ZQ calibration auto initialization mode is recommended for keeping the ZQ registers calibrated during
i.MX53 operating modes and ambient temperature changes.
7.2.4DDR Device ZQ HW Calibration Type
While i.MX53 DDR PHY auto initiated HW calibration sequence is the same in all the above cases. DDR device sequence differs between long and short procedures, as described in Section10, “ZQ Calibration.”
7.2.5One Time SW ZQ Calibration
Local i.MX53 DDR PHY calibration can be also performed as a one-time event, by writing a selected ZQ values to ESDCTL register, reading ZQ comparator result, changing ZQ values and repeating the process until comparator toggling point is detected.
?One time SW ZQ calibration does not apply to DDR device.
?One-time SW ZQ calibration mode is mainly used for ESDCTL debugging. Keeping ZQ calibration in functional mode should be done by the other ZQ calibration modes.
Using the DDR Calibration Modes 7.3Timing Calibrations Usage
User can calibrate DDR timings (DQS gating, Write leveling and Write/Read DQS delay calibrations) using the DDR controller iterative calibration sequence features. Alternately, user can select a previously defined set of timing delay values and write them to delay registers, without calibration sequence activation. Not using any of these two methods, DDR controller is interfacing DDR device with its default (mid-range) delay values.
DDR timing variations are mainly associated with board design and selected DDR device type.
With less extent, DDR timing are influenced by parameters deviations between manufactured i.MX53 ICs, DDR devices, and boards.
Changing ambient temperature and product age can also have a minor effect on DDR timing. Considering all these, user can apply any of the following calibration policies:
?Run timing calibration sequence once for certain board design. Reuse calibration values result as fixed delay values for all the population of this board type and the ICs assembled.
?Timing calibration sequence run on each and any manufactured board + ICs, as an additional assembly line procedure. The resulted delay values can be then flashed to the product and be used as delay preset values in DDR setup throughout lifetime.
?Product SW is repeatedly running calibration sequence upon system power up.
There is no known need to repeat the timing calibration process during system activity.
7.4Order of the Calibration Sequence Running
When running timing calibration sequence, the following order should be kept:
1.One-time, forced ZQ Calibration
2.Write Leveling Calibration
3.DQS Gating
4.Read data DQS calibrations
5.Write data DQS calibrations
Delay Unit HW Overview
8Delay Unit HW Overview
Figure 1. i.MX53 Delay Units HW: Functional Diagram
There are several different delay mechanisms in ESDCTL. Each of them is duplicated per byte or bit, as described throughout this document. This section, however, describing the general HW structure and functionality which is in common for them all.
Delay mechanism is split by two:
?Delay logic, located at the ESDCTL, maintains the delay value in time units, and in some cases
also handle a delay calibration sequence.
?Delay unit, located at the DDR PHY , contains a physical chain of basic delay elements.
DDR PHY supports an ongoing measure process, to determine what is the time delay of the basic delay element. This basic time delay varies over temperature, and IC manufacturing. So the ongoing measurement is necessary.
A major signal in the handshake between delay logic and delay unit is the internal signal frc_msr.“frc_msr,” when sent by delay logic, after delay time value is updated, drives the following activities:
?
Absolute delay time value from delay logic is latched inside DDR PHY .?DDR PHY uses latest measured process to determine how many delay elements should be activated
to achieve the required absolute delay time value, and set the delay unit accordingly.
“frc_msr” assertion is thus a must as the terminating stage of a delay calibration. In the auto-initiate and HW calibration sequence cases, HW is asserting this signal.
In SW handled and forced delay value calibration cases, it is the user responsibility to assert this signal, by setting the FRC_MSR bit of the ESDCTL_MUR register, at the end of the calibration sequence.i.MX53
DDR PHY DDR Logic
(ESDCTL )
...
delay logic #1
delay unit #1delay logic #2delay unit #2
delay logic #n delay unit #n ......
delay time value delay time value delay time value frc_msr
Address and Data Content Used for Timing Calibration
NOTE
In previous i.MX products, there was a dual delay calibration mechanism,
allowing the user to update the delay by programming the absolute time
delay value, or by number of delay elements.
In ESDCTL, the later is no longer available. Only absolute time delay values
programming is possible for the user. However, there are read only status
registers which allow user to read from DDR PHY the calculated number of
delay element:
?WLDLST register for Write leveling
?DGDLST register for DQS gating
Reading the delay unit numbers is mainly used for IC validation and factory
tests. For the ESDCTL user, this is not a valuable source of information.
9Address and Data Content Used for Timing Calibration Read DQS delay, Write DQS delay and DQS gating calibration sequences are all using the same address, data content and compare registers when checking different delay values.
9.1Address Used in Timing Delay Calibration Sequence
Base address used during read and write operations are hard coded to be (Bank0, Row0, Col0).
In i.MX53, this is mapped to CSD0_BASE_ADDR +0x10000000, or absolute address of 0x80000000. Before any of the above calibration sequences take place, user should fill this target address with content matching ESDCTL_PDCMPR1 (i= 0 to 3):
?PDV1[7:0] to [CSD0_DDR_BA+ 0x10000000 + i * 16]
?PDV1[15:8] to [CSD0_DDR_BA+ 0x10000004 + i * 16]
?PDV2[7:0] to [CSD0_DDR_BA+ 0x100000008 + i * 16]
?PDV2[15:8] to [CSD0_DDR_BA+ 0x1000000c + i * 16]
NOTE
Looking into ESDCTL programming model, user can see a description of a
“dummy write and read” mechanism. This mechanism, is required for
systems where (Bank0, Row0, Col0) address is blocked from explicit core
access. The ESDCTL is accessing this address with no system read or write,
and set the data content as required for the calibration compare.
In i.MX53, however, the (Bank0, Row0, Col0) can be explicitly accessed.
This entire document describes setting content of (Bank0, Row0, Col0) with
explicit access, ignoring the “dummy access” option.
ZQ Calibration
9.2Optimal Data Content for DQS delay Calibration Sequence
?PDV2[15:8] is compared with all 8 data bytes of the 4th and 8th DQS (rising) edges of the calibrating burst
?PDV2[7:0] is compared with all 8 data bytes of the 3rd and 7th DQS (falling) edges of the calibrating burst
?PDV1[15:8] is compared with all 8 data bytes of the 2nd and 6th DQS (rising) edges of the calibrating burst
?PDV1[7:0] is compared with all 8 data bytes of the 1st and 5th DQS (falling) edges of the calibrating burst
Users are free to program any value to ESDCTL_PDCMPR1. There are, however, two rules for selecting an effective value:
1.Data better be toggled from rising edge to rising edge, and from falling edge to falling edge (data
is separated at IO to 2 stream according to edge).
2.Better toggle all bits at the same direction.
Following these rules, ESDCTL_PDCMPR1 was set to 0x00ffff00, with some systems, this was empirically found to give the best calibration results.
10ZQ Calibration
ZQ calibration is a process that tunes the DRAM and ESDCTL I/O pad output drivers (drive strength) and ODT values across changes in process, voltage, and temperature. There are two instances where ZQ calibration is performed: on the i.MX53 (DDR pads) and on the DDR device. ZQ calibration sequence can be initiated as a one-time event, or a periodic sequence.
On-time ZQ calibration can be one of the following two:
?One-time Forced HW ZQ calibration iterative sequence, as described in detail at Section10.1, “One-Time Forced HW ZQ Calibration Sequence.”
?One-time SW handled calibration iterative sequence ZQ calibration, as described in detail at Section10.2, “One-time SW ZQ Calibration Sequence.”
Once periodic ZQ calibration (described in detail in Section10.3, “Auto Initiated HW ZQ Calibration Sequence”) is programmed, the ESDCTL will automatically issue and perform the ZQ calibration without further user interaction. While i.MX53 side periodic calibration is the same at all times, there are two different types of ZQ calibration commands (long and short) that are sent to the DDR device and are described as follows.
Long DDR device ZQ calibration is initiated upon:
?One time forced ZQ calibration
?i.MX53 power up
?Exiting DDR self refresh mode
?Exiting slow precharge power down
ZQ Calibration
Short DDR device ZQ calibration is initiated when a periodic ZQ is issued.
10.1One-Time Forced HW ZQ Calibration Sequence
One-time ZQ calibration, using HW loop logic is performed by the following sequence:
?Make sure all accesses to DDR are finished.
?Set ESDCTL register fields according to Table 1:
Table 1. One-Time HW ZQ Calibration Configurations
?
Assert the ZQ_HW_FOR bit in ZQHWCTRL register ?
Wait for ZQ_HW_FOR to be cleared by HW ?ZQ resistors are now calibrated. Pull-up, pull-down configured values can be read from
ZQ_HW_PD_RES and ZQ_HW_PU_RES fields of the ZQHWCTRL register.
10.2One-time SW ZQ Calibration Sequence
One time SW ZQ calibration is mainly used to debug, and not recommended to be used with customer products calibration. One time SW ZQ calibration only applies to local ESDCTL PHY and not for the Register
Field Description ESDCTL
Registers
--Program the entire i.MX53 register set to fit the selected DDR mode and DDR device. It is recommended to “DDR INIT” setup code provided with the development kit or operating system in use.ZQHWCTRL ZQ_MODE[1:0]One time HW ZQ calibration involves both local ESDCTL PHY and DDR device.
ZQ_MODE should thus be set to one of the following modes:
?0x1 ZQ calibration is issued to i.MX ZQ pad and external device (only when exiting
self refresh).
?0x3 ZQ calibration is issued to i.MX ZQ pad and external device (both periodic and
when exiting self refresh).
ZQHWCTRL TZQ_INIT[2:0]TZQ_OPER[2:0]For DDR2, DDR3 operation:
?Set the DDR device ZQ timings to match DDR device Datasheet.
?This field is ignored if DDR device ZQ calibration is not selected by ZQ_MODE.
ZQLP2CTL ZQ_LP2_HWZQ INIT[8:0]ZQ_LP2_HW_Z QCL[7:0]For LPDDR2 operation:
?Set the DDR device ZQ timings to match DDR device Datasheet.
?ESDCTL logic selects between ZQHWCTRL and ZQLP2CTL parameters according
to ESDMISC/DDR_TYPE.
ZQHWCTRL
ZQ_P ARA_EN Device ZQ calibration parallel enable.
0- Device ZQ calibration is done in serial (CSD0 first and then CSD1).
1- ZQ calibration of both CS is done in parallel
In functional mode, parallel calibration should be preferred for its speed. Choose serial
as a for debugging if ZQ calibration issues are suspected.ZQSWCTRL USE_ZQ_SW_V AL
Should be selected to ‘0’ for fields ZQ_HW_PD_VAL and ZQ_HW_PU_VAL to be used.
ZQ Calibration
DDR device. It is using HW ZQ comparator, but handling the iterative sequence by SW. The following sequence should be followed:
?Make sure all accesses to DDR are finished
?Set ESDCTL register fields according to Table 2:
Table 2. One-Time HW ZQ Calibration Configurations
10.2.1
Pull-up Calibration ?
Set ZQ_SW_PD in register ZQSWCTRL to ‘0’ (PU calibration)?
Set ZQ_SW_PU_V AL in register ZQSWCTRL to a selected value ?
Assert the ZQ_SW_FOR bit in ZQSWCTRL register ?
Wait for ZQ_SW_FOR to be cleared by HW ?
If ZQ_SW_RES is ‘1’, increase ZQ_SW_PU_V AL and repeat previous steps ?When ZQ_SW_RES==0 is detected, stop sequence and read ZQ_SW_PU_V AL
10.2.2
Pull-Down Calibration ?
Set ZQ_SW_PD in register ZQSWCTRL to ‘1’ (PD calibration)?
Set ZQ_SW_PD_V AL in register ZQSWCTRL to a selected value ?
Assert the ZQ_SW_FOR bit in ZQSWCTRL register ?
Wait for ZQ_SW_FOR to be cleared by HW ?
If ZQ_SW_RES is ‘1’, decrease ZQ_SW_PD_V AL and repeat previous steps.?When ZQ_SW_RES==0 is detected, stop sequence and read ZQ_SW_PD_V AL
10.2.3Apply ZQ Calibration
Set the FRC_MSR for the new calculated ZQ_SW_PU_RES and ZQ_SW_PD_RES start being used.Register
Field Description ESDCTL
Registers
--Program the entire ESDCTL register set to fit the selected DDR mode and DDR device. It is recommended to “DDR INIT” setup code provided with the development kit or operating system in use.ZQHWCTRL ZQ_MODE[1:0]One time SW ZQ calibration involves Only local ESDCTL PHY .
ZQ_MODE field options are not relevant in this case. Anyway, ZQ_MODE better be
kept in one of the following modes:
?0x1 ZQ calibration is issued to i.MX ZQ pad and external device (only when exiting
self refresh).
?0x3 ZQ calibration is issued to i.MX ZQ pad and external device (both periodic and
when exiting self refresh).
ZQSWCTRL
USE_ZQ_SW_V AL Should be selected to ‘1’ for fields ZQ_SW_PD_VAL and ZQ_SW_PU_VAL to be used.
ZQ Calibration
10.3Auto Initiated HW ZQ Calibration Sequence
Auto initiated ZQ calibration, using HW loop logic is performed by the following sequence:
1.Make sure all accesses to DDR are finished.
2.Set ESDCTL register fields according to Table 3:
Table 3. Auto Initiated HW ZQ Calibration Configurations
3.ZQ resistors will be auto calibrated according to the operation mode selected by ZQ_MODE[1:0].Register
Field Description ESDCTL
Registers
--Program the entire ESDCTL register set to fit the selected DDR mode and DDR device. It is recommended to “DDR INIT” setup code provided with the development kit or operating system in use.ZQHWCTRL ZQ_MODE[1:0]
Enables the automatic ZQ calibration process. It is recommended for the user to set this
field to 0x3, which programs the ESDCTL to issue ZQ calibration to the i.MX ZQ
calibration pad together with the ZQ calibration command to the external DDR device
periodically (short command) and when exiting self refresh (long command). ZQHWCTRL ZQ_HW_PER[3:0]ZQ HW calibration period time. This field determines how often ZQ HW calibration time
is performed in regular operation mode.
It is recommended for the user to simply leave this filed set to 1 ms (bit setting 0000).
This field is ignored if periodic ZQ calibration is not selected by ZQ_MODE.
ZQHWCTRL ZQ_HW_FOR Force ZQ automatic calibration process with the i.MX ZQ calibration pad.
No need to set this bit during normal operations as the ZQ calibration of the i.MX DDR
pads are taken care of periodically.
ZQHWCTRL TZQ_INIT[2:0]
TZQ_INIT holds the number of cycles that are required by the external DDR device to
perform ZQ long calibration right after reset. The default bit setting of 100 (512 cycles)
is recommended. ZQHWCTRL TZQ_OPER[2:0]Holds the number of cycles that are required by the external DDR device to perform ZQ
long calibration except the first ZQ long command that is issued after reset. The default
bit setting of 011 (256 cycles) is recommended.
ZQHWCTRL
TZQ_CS[2:0]Holds the number of cycles that are required by the external DDR device to perform ZQ
short calibration. Note that the default value of 128 cycles (bit setting 010) is also the
minimum amount of cycles that can be set. Therefore, if the external DDR3 device
specifies this. ZQLP2CTL ZQ_LP2_HWZQI NIT[8:0]ZQ_LP2_HW_Z QCL[7:0]For LPDDR2 operation:
?Set the DDR device ZQ timings to match DDR device Datasheet.
?ESDCTL logic selects between ZQHWCTRL and ZQLP2CTL parameters according
to ESDMISC/DDR_TYPE.
ZQHWCTRL
ZQ_P ARA_EN Device ZQ calibration parallel enable.
0- Device ZQ calibration is done in serial (CSD0 first and then CSD1)
1- ZQ calibration of both CS is done in parallel
In functional mode, parallel calibration should be preferred for its speed. Choose serial
as a for debugging if ZQ calibration issues are suspected.ZQSWCTRL USE_ZQ_SW_V AL
Should be selected to ‘0’ for fields ZQ_HW_PD_VAL and ZQ_HW_PU_VAL to be used.
ZQ Calibration
10.4Local ESDCTL PHY HW ZQ Calibration Sequence
Upon forced or auto initiated HW calibration of local PHY , the following sequence is done by the ESDCTL logic (all steps are HW driven, no user activity is required):
Figure 2. i.MX53 DDR PHY ZQ Calibration HW: Functional Diagram
10.4.1Pull-Up Calibration (Step 1-8)
The internal pull-up resistor calibration is done versus the 240 Ω, 1%, external resistor.
Step 1: zq_comperator_en and zq_pu_pd_sel are set to ‘1’.
Step 2: Set MSB of zq_pu_val (zq_pu_val=’10000’). If comparator output is 1 (output voltage is higher than Vdd/2 => internal resistor is less than 240 Ω) keep zq_pu_val[4] set. Else, clear zq_pu_val[4].
Step 3: Set Bit 3 of zq_pu_val (zq_pu_val=’x1000’). If comparator output is 1(output voltage is higher than Vdd/2 => internal resistor is less than 240 Ω) keep zq_pu_val[3] set. Else, clear zq_pu_val[3].
Step 4: Step6 - Repeat the same for bit 2 (step 4), bit 1 (step 5) and bit 0 (step 6).
Step 7: hw_zq_pu_en is driven to 0.
Step 8: ESDCTL drives ZQ calibration result to ZQHWCTRL[ZQ_HW_PU_RES].
10.4.2Pull-Down Calibration (Step 9-16)
The internal pull-down resistor calibration is done vs. internal pull-up resistor.
Step 9: zq_comperator_en is set to ‘1.’ zq_pu_pd_sel is set to ‘0.’
External ZQ Resistor 240 Ohm Configurable pull-down
Resistor
(240 Ohm, Nominal)Configurable
pull-up
Resistor
(240 Ohm, Nominal)
vcc
ZQ
VREF comp i.MX53
zq_pu_val[4:0]zq_pd_val[4:0]comp_out Logic Calibration
zq_comparator_en && zq_pu_pd_sel
zq_comparator_en & !(zq_pu_pd_sel)
1%
zq_compare_en
Write Leveling Step 10: Set MSB of zq_pd_val (zq_pd_val=’10000’). If comparator output is 1 (output voltage is higher than Vdd/2 => internal pd resistor is less than 240 Ω) clear zq_pd_val[4] set. Else, keep zq_pd_val[4] set. Step 11: Set MSB of zq_pd_val (zq_pd_val=’x1000’). If comparator output is 1(output voltage is higher than Vdd/2 => internal pd resistor is less than 240 Ω) clear zq_pd_val[3] set. Else, keep zq_pd_val[3] set. Step 12: Repeat the same for bit 2
Step 13: Repeat the same for bit 1
Step 14: Repeat the same for bit 0
Step15: hw_zq_pu_en is driven to 0
Step 16: ESDCTL drives ZQ calibration result to ZQHWCTRL[ZQ_HW_PD_RES].
10.4.3Apply ZQ Calibration (Step 17)
Step 17: Set an internal “Force measure” signal for the new calculated ZQ_HW_PU_RES and
ZQ_HW_PD_RES start being used.
10.5DDR Device ZQ Calibration Sequence
Upon forced or auto initiated HW calibration of DDR device happens, the following sequence is done by the ESDCTL logic (all steps are HW driven, no user activity is required):
1.Send a precharge-all command to DDR device.
2.Wait for tRP period.
3.Send a ZQ calibration command to DDR device. CSD0/CSD1 are set according to selected DDR
target. A10 is ‘0’ for long ZQ calibration, or ‘0’ for short ZQ calibration.
4.Keep the DDR port idle for the time period indicated by
ZQ_HW_ZQC/ZQ_LP2_HW_ZQCL/ZQ_LP2_HW_ZQCS (according to DDR_TYPE).
11Write Leveling
Write leveling is associated with the DDR “fly-by” board topology. “Fly-by” has its advantages of layout simplicity and minimal stubs. In the fly-by topology layout, the address, command, and clock signals are “daisy chain” routed from one DDR3 device to the next, where DQS and data (DQ) bus signals are routed “point-to-point” from the ESDCTL to the DDR3 device.
It, however, implies a skew between CK and DQS, a skew that is not the same for the different DQSx signals, depending on the board placement of the DDR device which is connected to the specific DQSx.
Write Leveling
Figure3. Fly-by Topology
Write leveling target is to give each set of {DQSx, DMx, DQx} its own delay, to de-skew the clock to DQS timing relationship at the DDR3 device. A proper 'fly-by' design is based on clock, address and command trace length, which is equal or greater than any of the data bytes trace lengths.
ESDCTL write leveling is based on this, as its delay value compensates for early data signals, while late data signals can't be compensated.
Write leveling calibration is a process that involves both the ESDCTL and the DDR device. The WL process has its own DDR signal setup which is different than DDR functional mode. During WL, DQSx is constantly driven by i.MX53. DQx is constantly driven by the DDR device.
WL sequence is described in Figure4. i.MX53 repeatedly sends single strobes on DQSx. CK is continuously sampled by DDR on DQSx rising edge and feed back the result to DQx. When CK and DQSx are unaligned, returned value is ‘0’. i.MX53 then adds delay to DQSx, until ‘1’ is returned on DQx. The measured delay is then applied to the entire {DQSx, DMx, DQx} group.
Each DQS has its own delay. In DDR3, the configurable value for each DQS can be different. WL calibration sequences of the different DQSx are done in parallel.
Write Leveling
Figure4. Timing Diagram: Before and After the Write Leveling
The i.MX53 supports up to 2.875 cycles of physical delay. Delay value is combined from the WL delay fields: (WL_DL_ABS_OFFSET/256 * cycle) + (WL_HC_DEL * half cycle) + (WL_CYC_DEL * cycle). It should be noted, however, that the WL calibration, as defined for the i.MX53 and the DDR device is limited to detect and align CK to DQSx skews of up to one cycles. Larger skews will cause DQSx to overlap and detect the next CK cycle, returning fault alignment feedback. Good DDR board design can keep the skew smaller than 1 cycle. If, however, a larger skew is required, user can program the number of integer cycle delays to the WL_CYC_DELx in WLDECTRLx register, and the WL calibration will be modified accordingly.
It should be noted that write leveling delay might also imply an increase of the overall cycle time of the DDR write access. This increase is achieved by changing W ALAT parameter from its default 0 to 1 (or more, in extreme cases). To be on the safer side, WALAT is always increased during the WL calibration process (see Section11.2, “HW Write Leveling Calibration Sequence”). If resulted WL delays are small, WALAT can be written back to 0, for the DDR normal operation. If, on the other hand, WL delays are significant (empirically seen to be at about 1/2 cycle and above, for one of DDR bytes, or more), increased WALAT should be kept as part of the new DDR setup that include the newly calculated WL delays. Increased W ALAT implies a small degradation in DDR port performance.
Write Leveling
It should be noted that the entire WL calibration is done using CK0, with DDR devices connected to CSD0. Applying CSD0 delay results to the DDR devices connected to CSD1 is conditioned by the a DDR board design that provide an identical route and placement to CSD0 and CSD1 DDR devices, sharing the same DQx bytes (typically done by mirror design of CSD0 and CSD1 DDR placement using both sides of the PCB).
i.MX53 WL calibration is sensing LSB of the DQx byte for the WL feedback. That is, bits 0, 8, 16, and 24 of the DQ bus are being used. This fact should be considered during board design. Regularly, board design is allowed to swap bit connections within the DDR byte, wherever it helps DDR route optimization. Swapping DQx LSBs, as above, will disable operation of the WL calibration. Swapping the LSBs should be avoided, unless a DDR device that reflect WL feedback to all bits of the DQx byte is used.
11.1Calibrating Write Leveling with a Preset Delay Value
Write leveling can be calibrated without running the calibration sequence, by programming a preset value of absolute delay.
Preset value source can be a write leveling calibration sequence done in the past. Alternately, the delay values can be an estimation of data delays based on DDR board route length.
The following empiric rule, based on simulations and board experience, can be used:
Each ([SDCLK_LENGTH] -[DQS_LENGTH])/6, measured in intches, implies 1 ns of delay.
The time delay received by this rule should be converted to ddr_cycle/256 units, and applied to delay register.
Calibrating with a preset value is done by the following:
?Write the WL preset value to WLDECTRL0, WLDECTRL1 registers
?Set MUR[FRC_MSR] bit.
11.2HW Write Leveling Calibration Sequence
The following steps should be executed by user code:
1.Store the contents originally programming in the DDR3 MR1 register. This register will be
overwritten in step 3 to enter write leveling mode (DDR3 device does not allow read of the mode registers, so MR1 content cannot be retrieved by read). Refer to the DDR3 device data sheet for details on the MR1 register.
2.Disable Auto initiated ZQ calibration and DDR auto refresh, so these processes would not
interfere with the WL calibration.
3.Increase W ALAT and RALAT parameters to maximum.
4.Configure the external DDR device to enter write leveling mode through MRS command.
Write Leveling
5.Activate the DQS output enable by setting ESDSCR[WL_EN]. Note that current and previous
steps can be performed simultaneously as both steps involve writing to the same ESDSCR
register.
Figure5. ESDSCR Register Example to Enable Write Leveling
6.Activate automatic calibration by setting WLGCR[HW_WL_EN].
7.Poll the WLGCR[HW_WL_EN] until cleared.
8.Read WL error bits, WLGCR[11:8], to verify WL calibration sequence terminated properly.
9.Configure the external DDR device to leave write leveling mode through MRS command (W rite to
DDR3 mode register MR1, clear bit 7, through the ESDSCR).
10.Clear ESDSCR[WL_EN]. As described above, current and previous steps can be performed
simultaneously as both steps involve writing to the ESDSCR register.
11.Configure ESDCTL to factional mode DDR parameters: RALAT, WALAT, auto ZQ calibration
and auto refresh.
12.Once this process is done, the WLDECTRL0 and WLDECTRL1 registers are updated with the
proper write leveling delays. These values can be kept and reused in future, as described in
Section11.1, “Calibrating Write Leveling with a Preset Delay Value.”
After WLGCR[HW_WL_EN] bit is activated (step 6 above), the following steps are executed automatically by the ESDCTL:
1.ESDCTL enters write leveling mode, counts 25 + 15 cycles and drives the DQS pads as output
while the DQ pads will remain inputs. In parallel the ESDCTL configures the write leveling delay line to “0” (WLDECTRL0[WL_DL_ABS_OFFSETx] = 0) and issue measurement process of the write-leveling delay-line to update itself with the new value.
2.ESDCTL drives one DQS pulse to the DDR external device.
DQS Gating
3.ESDCTL waits 16 cycles (to guarantee that the DQ prime data is stable) and samples the
associated prime DQ bit (for example for DQS1 the ESDCTL samples DQ[8]).
4.ESDCTL increments the write leveling delay line by 1/8 cycle and performs measurement process
in order to load the updated value to the associated delay-line.
5.ESDCTL repeats steps 5-7 till the write leveling delay is 1 cycle.
6.ESDCTL checks the 8 bit prime DQ results for each DQS and finds the first transition from 0 to 1.
If no transition is found then the ESDCTL indicates an error at WLGCR[HW_WL_ERRx].
7.ESDCTL stores the value that issues the last “0” on the prime DQ before the transition and loads
it to the write leveling delay-line. The ESDCTL initiates a fine-tune process by incrementing the delay-line values by 1 step (which is 1/256 part of a cycle) till detecting the most accurate
transition from 0 to 1.
8.Upon completion of this process the ESDCTL de-asserts the WLGCR[HW_WL_EN] and updates
the most accurate value of the delay-line at the associated.
WLDECTRLx[WL_DL_ABS_OFFSETx]
9.ESDCTL perform measurement process (internal frc_msr) in order to load the most accurate
value to the associated delay-line.
12DQS Gating
Figure6. DQS Read Gating Calibration: Timing Diagram
DQS Gating The read DQS gating calibration is not mandatory by DDR3 JEDEC standard, but it is required mechanism to determine the valid time period with which to begin sampling the incoming “read” DQS signal. The intent is to avoid inadvertently sampling an invalid DQS state, such as misinterpreting the initial High-Z to logic low transition as a valid read DQS edge.
?DQS gating is thus an over-time masking operation of the input DQS driven by the DDR device.
?DQS gating assertion is done according to the DQS gating delay, as configured to the ESDCTL registers.
?DQS gating negation has a fixed timing after the negedge of last DQS strobe (if there is no back to back access).
As shown in Figure6, a properly set DQS gate is starting at the middle of the DQS read preamble, that is, at the middle of the low DQS driven by the DDR device ahead of the first DQS strobe. Too early DQS gating assertion causes ESDCTL to sense the DQS signal when floating, and possibly sense false DQS signal assertions. Too late DQS gating assertion masks a valid DQS strobes from being sensed by the ESDCTL.
DQS gating calibration is the process of giving the DQS gate the proper delay. DQS latency is changing according to DDR device and board design, so DQS gate delay should be measured for each unit separately.
The HW DQS gating calibration sequence is based on finding the too-early and too-late gate boundaries, placing the boundary values at the status registers (DGHWSTx), then calculating the arith-metic average of the boundaries and placing it as delay value at the control registers (DGCTRLx). During read DQS calibration, the ESDCTL samples only the DQS signal. Its complementary DQS_B signal is not part of the process. Assumption is the signal pair is well balanced, thus sharing the same timing and require the same gate masking.
Each of the four DQS signals has a its own gating delay and gating calibration. The DQS gating calibration sequence, however, can be done for all DQS in parallel.
The DQS gating includes a delay of up to 7.875 cycles. Delay value is combined from the DQS gating delay fields: (DG_DL_ABS_OFFSET/256 * cycle) + (DG_HC_DEL * half cycle).
It should be noted that in order to mask out fault incoming DQS strobes, there is an alternative to DQS gating, by simply applying pull downs to DQS signals. Pull-downs, however, have their disadvantages, which include excessive power consumption and interference with ODT resistors. DQS gating is free from these, and hence considered as a better choice.
12.1Calibrating DQS Gating with a Preset Delay Value
DQS gating can be calibrated without running the calibration sequence, by programming a preset value of absolute delay.
Preset value source can be a DQS gating calibration sequence done in the past, or any other value estimated by user to optimize DQS gating location.
Calibrating with a preset value is done by the following:
1.Write the DQS gating preset value to DGCTRL0, DGCTRL1 registers
DQS Gating
2.Set MUR[FRC_MSR] bit.
12.2HW DQS Gating Calibration Sequence
?Options to set the data content used during DQS gating calibration:
—Calibration with ESDCTL predefined data, written to a selected address in DDR device RAM.
?There are two options to handle the iterative DQS gating sequence:
—HW DQS gating sequence
—SW DQS gating sequence
HW DQS gating calibration is the recommended sequence for the typical customer board, while
SW sequence is only used for debug and special cases, when necessary.
It should be noted that the entire DQS gating HW calibration sequence is done using CK0, with DDR devices connected to CSD0. Applying CSD0 delay results to the DDR devices connected to CSD1 is conditioned by a DDR board design that provides an identical route and placement to CSD0 and CSD1 DDR devices, sharing the same DQx bytes (typically done by mirror design of CSD0 and CSD1 DDR placement using both sides of the PCB).
During DQS gating SW calibration sequence, user can select any address for the write and read operations, so devices connected to CSD1 can participate similarly to CSD0 devices.
12.3ESDCTL Register Setup for DQS Gating Calibration Sequence
12.3.1Register Setup Prior to DQS Gating Calibration Sequence
Set ESDCTL register fields according to Table4:
Table4. Auto Initiated HW ZQ Calibration Configurations
Register Field Description
i.MX53 registers --Program the entire i.MX53 register set to fit the selected DDR mode and DDR device.
It is recommended to “DDR INIT” setup code provided with the development kit or
operating system in use.
IOMUXC/ SW_P AD_CTL
_DQSx pke,
pue,
pus
Configure DQS pads to have an active on-chip 47k pull-up. Pull up is required to make sure
the too early DQS gating settings will drive false data, by failing to gate off the Hi-Z
period.
DGCTRL0 DG_EXT_UP DG extend upper boundary.
‘0’ - upper boundary of DQS gating hw calibration is set according to first fail after at
least one pass.
‘1’ - upper boundary is set according to the last pass.
There is no significant difference observed in calibration results due to this bit setup. It
typically remains clear.