SA9227-v1.3a
BRAVO-DSD
SA9227
Stereo In/Out
DSD64/ DSD128,
PCM 32Bit/ 384KHz
USB Audio Streaming Controller
Datasheet v1.3
SAVITECH Corporation
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The SA9227 is a high performance up to 32bit, 384KHz PCM and DSD64/128 streaming USB High-Speed compliant audio steaming controller. It features one stereo playback and recording pairs and one IEC60958 S/PDIF receive and transmit streaming pair. The SA9227 is ideal for both one stereo-in and one stereo-out
professional digital audio interface applications. Its PCM resolution and sampling rate can be configurable with 16/24/32 bit and 32/ 44.1/ 48/ 88.2/ 96/ 176.4/ 192/ 352.8/ 384KHz respectively.
Overview
BRAVO-DSD/PCM
SA9227
USB Audio Streaming Controller
Features
SA9227 optional iAP1/iAP2, require MFi (Made for iDevice) license USB 2.0 High-Speed Compliant
USB Audio Class v1.0 and v2.0 supported
Incredible Bravo sound quality supported by Savitech innovative Bravo Tech*1
Bravo Tech*1 supporting Jitter-less outputs using local clock in Async-mode Isochronous input and output endpoints for recording and playback One interrupt endpoint for HID
One DSD interface for connect with external DSD DAC
Support resolutions up to 32-bit and sampling rates up to 384KHz Two I2S input pairs and four I2S output pairs for PCM
Independent sample rates for each pairs
32/ 44.1/ 48/ 88.2/ 96/ 176.4/ 192/ 352.8/ 384 KHz sampling rates 16/24/32 bit resolution
Built in IEC60958 professional S/PDIF TX and S/PDIF RX,
AES/EBU supported*
SCMS for copyright supported
Stereo SPDIF Input and S/PDIF Output
32/ 44.1/ 48/ 88.2/ 96/ 176.4/ 192/ 352.8/ 384 KHz sampling rates 16/24 bit resolution DSD with S/PDIF TX Control and I/O
I2C bus GPIOs
64-pin TQFP packages For iDevice, it is necessary to become a licensee of Apple Inc.
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Serial Audio Interfaces
Support 2-IN / 2-OUT
Two I2S input and four I2S output serial interfaces are supported to communicate with the external DACs / ADCs / CODECs. All the input channels share the same MCLK, SCLK and LRCLK and run at the same rate and same format. All the output channels share the same MCLK, SCLK and LRCLK and run at the same rate and same format.. Some internal routing capabilities are supported for audio stream switching, as shown in the following diagram.
CORE RDMA M U X
PDMA
M U X
M U X
I2S OUT0
SPDIF-TX
I2S IN0
SPDIF-RX
SPDIF RX to I2S TX
Routing Path
SPDIF-RX to SPDIF-TX pass-through path
Serial Audio Interfaces Formats
L-justified format:
In Left Justified mode, the MSB is available on the first rising edge of BCLK following
an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
I2S format
In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
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Serial Audio Interfaces Formats
R-justified format
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after
each LRCLK transition.In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
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Master Mode
Slave Mode
Master
Slave Master Slave
SA9227 supports both master mode and slave mode for following configurations.
Serial Audio Interfaces Configuration-DAC
SA9227 I2S Master Mode connection
SA9227 I2S Slave Mode connection
SA9227
DAC
MCLK LRCLK
SCLK SDO
SA9227
DAC
MCLK LRCLK
SCLK SDO
SA9227DAC MCLK LRCLK
SCLK SDO
CLK1(45.1584MHz)CLK2(49.152MHz)
MUX
OSC1OSC2
Sampling Rate
SA9227
DAC
MCLK LRCLK
SCLK SDO
Clock Generator
Sampling Rate
REFCLKIN to relpace MCLK
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Master Mode (with external REFCLKIN), Mode 0
Master Mode (with external REFCLKIN), Mode 1
Slave
Master Master
Slave
Serial Audio Interfaces Configuration-DAC
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Serial Audio Interfaces Configuration-ADC
SA9227
ADC
MCLK LRCLK
SCLK SDI
DSD Audio Data Interfaces
Playback:
SA9227 support three modes for playback DSD data over USB Audio stream
1. Sampling rate 88.2K and resolution 32-bits to transmit DSD data over USB streaming.
2. Sampling rate 176.4K and resolution 24-bits to transmit DSD64 data over USB
streaming.
3. Sampling rate 352.8K and resolution 24-bits to transmit DSD128 data over USB
streaming.
Summary these DSD formats:
DSD format for 88.2K 32-bit: DCLK (@2.8224MHz) Direct-DSD
DSD 64 format for 176.4K 24-bit: DCLK (@2.8224MHz) DoP/dCS
DSD 128 format for 352.8K 24-bit: DCLK (@5.6448MHz) DoP/dCS
The DSDL and DSDR are all output by negative edge of DCLK. And DSD DAC will sample them by
post edge of DCLK.
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DSD_FLAG : (0 : RESET, 1: Normal Operation in DSD format): Used to RESETN DSD DAC. DSD_FLAG : (0 : in PCM mode, 1: in DSD mode): used to switch DSD or PCM DAC.
DSD_128 : (0 : in DSD 64 mode, 1: in DSD 128 mode): used to switch DSD64 and DSD128 format for DSD DAC.
DSD External Control Signals
Application with PCM DAC and DSD DAC
SA9227
DSD DAC
MCLK
LRCLK DSD_128_FLAG
DATA
SWITCH
PCM DAC
MCLK SCLK DSD_CLK DSD_DL DSD_DR
GPIO1
MUTE
DSD64/128RESETN
DSD_FLAG
I2S/DSD
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Application with PCM/DSD multi function DAC
SA9227
DSD/PCM DAC
DSD_128_FLAG
GPIO1
MUTE
DSD64/128
RESETN
DSD_FLAG
I2S/DSD
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Apple strongly recommends the use of digital audio paths to and from accessories. Apple
device in USB Host Mode audio is the recommended approach. SA9227 will authenticate and identify itself to Apple device using iAP1/iAP2 CP before the iDevice will enumerate and start using USB Audio interface.
-Support 16 /24-bit linear PCM
-Support 44.1, 48KHz sampling rate and up to 384KHz for future.-Support input and output audio interface -Support Volume Control Feature Unit
-Support iAP1 and iAP2 by CP2.0B and CP2.0C.
Digital USB Audio Application for iDevice
iDevice support
For using of SA9227 on iDevice, It is necessary to become a licensee of Apple Inc. regarding "Made for iPod/iPhone/iPad License".
SA9227
DAC MCLK LRCLK SCLK SDO
HOST / iDevice
APPLE CP (Coprocessor)I2C GPIO8
RST
ADC
MCLK LRCLK SCLK SDO
S/PDIF TX & RX Interfaces
SA9227 support one S/PDIF TX and one S/PDIF RX interfaces, each can support up to24-bit 384K sampling rate. Built in IEC60958 professional S/PDIF TX and SPDIF RX,? AES/EBU supported
? DSD stream output on S/PDIF TX
? 32/ 44.1/ 48/ 88.2/ 96/ 176.4/ 192/ 352.8/ 384 KHz sampling rates
? 16/24 bit resolution
? DSD with SPDIF TX
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I2C Master Interfaces
One serial I2C master is supported in SA9227 to control external peripheral devices (EEPROM). SA9227/SA9227i need an EEPROM to load Firmware code from it to SA9227. SA9227 support use I2C Master Interfaces to read/write CP to support Apple MFi.
I2C Slave Interfaces
SA9227 have an I2C slave interface which is used for external uC to read status of SA9227. I2CS supports burst read /burst write.
Slave I2C
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Read Back Registers
SPDIF RX Read Back Registers:
S/PDIF RX Read Back Status Register 0
Offset 30
Length: 1 byte
Bit Type Reset Description
7RO0Non-Audio Samples
1: Non-PCM audio samples
0: Linear PCM samples
6RO0Copyright
1: Non-copyright
0: Copyright
5RO0Pre-emphasis
4RO0Lock Status
1: S/PDIF RX input is locked
0: S/PDIF RX input is unlocked
S/PDIF RX Read Back Status Register 1
Offset 31
Length: 1 byte
Bit Type Reset Description
7RO0Reserved
6:0RO0Category code
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S/PDIF RX Read Back Status Register 3
Offset 32
Length: 1 byte
Bit Type Reset Description
7RO0Reserved
6RO0Professional mode
1: Professional mode
0: Consumer mode
5RO0Validity
4RO0Generation Level (L)
3:0RO0s S/PDIF Sample Rate reported from channel status bit
4’b0000: 44.1KHz
4’b0010: 48KHz
4’b0011: 32KHz
4’b1000: 88.2KHz
4’b1010: 96KHz
SPDIF TX Read Back Registers :
S/PDIF TX Control Register 0
Offset 33
Length: 1 byte
Bit Type Reset Description
7RO0Non-Audio Samples
1: Non-PCM audio samples
0: Linear PCM samples
6RO0Copyright
1: Non-copyright
0: Copyright
5RO0Pre-emphasis
4RO0Reserved
3:0RO0000Reserved
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S/PDIF TX Control Register 1
Offset 34
Length: 1 byte
Bit Type Reset Description
7RO0Reserved
6:0RO0Category code
S/PDIF TX Control Register 2
Offset 35
Length: 1 byte
Bit Type Reset Description
7RO0Reserved
6RO0Professional mode
1: Professional mode
0: Consumer mode
5RO0Validity
4RO0Generation Level (L)
3:0RO0s S/PDIF Sample Rate reported from channel status bit
4’b0000: 44.1KHz
4’b0010: 48KHz
4’b0011: 32KHz
4’b1000: 88.2KHz
4’b1010: 96KHz
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S/PDIF TX Control Register 3
Offset 36
Length: 1 byte
Bit Type Reset Description
7R_W1’b0Integrated S/PDIF transmitter enable
1: enabled
0: disabled
6R_W1’b0Companion I2S enable
1: Enabled. The data is duplicated on the I2S data output
pin.
0: Disabled
5R_W1’b01: Force TX data to 0 when Validity (bit 16) is 1 and bit 1 is
0 (PCM data)
0: Do not change data when Validity is 1. (default)
This bit is for the SCMS compatibility issues sometimes
found when interfacing with MD devices.
4:2R/W3’b010S/PDIF TX data source select
3’b110: Data is from the track 0/1 of the 8-CH I2S input
(input 0)
3’b100: 8-channel Turbo Mode enable. Data is from the 8-
CH I2S streams (EP3)
3’b011: Data is from Stereo mixer output
3’b010: Data is from the track 0/1 of the 8-CH I2S streams
(EP3)
3’b001: 8-channel Turbo Mode enable. Data is from the 8-
CH I2S input (EP2)
3’b000: Data is from EP6
1RO1’b0Reserved
Offset 36 ~ 3F
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0reserved
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Offset 40
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF RX channel status Byte0
Offset 40
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF RX channel status Byte0
Offset 41
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF RX channel status Byte1
Offset 42
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF RX channel status Byte2
Offset 43
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF RX channel status Byte3
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Offset 44
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF RX channel status Byte4
Offset 45
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF RX channel status Byte5
Offset 46 ~ 4F
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0reserved
Offset 50
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF TX channel status Byte0
Offset 51
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF TX channel status Byte1
Offset 52
Length: 1 byte
Bit Type Reset Description
7:0R_O8’h0SPDIF TX channel status Byte2
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