SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
AMENDMENT HISTORY
Version Date Description
VER 1.90 Sep. 2002 V1.90 first issue
VER 1.93 Feb. 2003 1. Extend chip operating temperature from “0°C ~ +70°C” to“-20°C ~ +70°C”.
2. Change the description of ADD M,A instruction from “M M+A” to “M A+M”
3. Add ADC grade table.
4. Remove “Support hardware multiplier (MUL)” in SN8P1702 FEATURES section.
5. Change “Four internal interrupts” to “Three internal interrupts” in SN8P1704
FEATURES section.
6. Change “ACC can’t be access by “B0MOV” instruction” to “ACC can’t be access by
“B0MOV” instruction during the instant addressing mode”.
7. Correct the description of STKnH.
8. Change “special register is located at 08h~FFh” to “special register is located at
80h~FFh”.
9. Correct the bit definition of INTEN register.
10. Correct the description of “TC0 CLOCK FREQUENCY OUTPUT” section.
11. Correct the description of “TC1 CLOCK FREQUENCY OUTPUT” section.
12. SCKMD = 1 means SIO is in SLAVE mode. SCKMD = 0 means SIO is in MASTER
mode.
13. Remove “SIO clock and SPI clock are compatible”.
14. Modify ADB’s output data table.
15. Correct an error of template code: “b0bclr FWDRST” “b0bset FWDRST”.
16. Add a notice about OSCM register access cycle.
17. SN8P1702/SN8A1702A don’t provide “MUL, PUSH, POP” instruction.
18. Add a notice about OSCM register access cycle.
VER 1.94 Sep. 2003 1. Correct EOC description.
2. Correct watchdog timer overflow time.
3. Correct POP operand.
4. Correct ADCKS table.
5. Add new section about checksum calculate must avoid 04H~07H.
6. Reserved Last 16 word ROM addresses
7. Add SIOM table and SIO rate note
8. Remove register bit description
9. Modify TC0M description
10. Modify TC1M description
11. Modify PWM description
12. Modify ADC Frequency description
13. Change Code option table to Chapter 2
14. Add ADC current consumption
15. Add LVD detect voltage
16. Remove approval sheet.
17. Remove PCB layout notice section.
18. Add MASK/OTP relative table.
19. Modify the description of INTRQ register.
20. Modify the calculation formula of SIOR and SIO clock.
Table of Contents
AMENDMENT HISTORY (2)
PRODUCT OVERVIEW (11)
GENERAL DESCRIPTION (11)
FEATURES SELECTION TABLE (11)
MASK/OTP R ELATIVE T ABLE (11)
ADC GRADE TABLE (11)
SN8P1702 FEATURES (12)
SN8P1704 FEATURES (13)
SN8P1707/SN8P1708 FEATURES (15)
SYSTEM BLOCK DIAGRAM (16)
PIN ASSIGNMENT (17)
PIN DESCRIPTIONS (22)
PIN CIRCUIT DIAGRAMS (22)
CODE OPTION TABLE (23)
ADDRESS SPACES (24)
PROGRAM MEMORY (ROM) (24)
OVERVIEW (24)
USER RESET VECTOR ADDRESS (0000H) (26)
INTERRUPT VECTOR ADDRESS (0008H) (26)
CHECKSUM CALCULATION (28)
GENERAL PURPOSE PROGRAM MEMORY AREA (29)
LOOKUP TABLE DESCRIPTION (29)
JUMP TABLE DESCRIPTION (31)
DATA MEMORY (RAM) (33)
OVERVIEW (33)
RAM BANK SELECTION (35)
WORKING REGISTERS (36)
H, L REGISTERS (36)
Y, Z REGISTERS (37)
X REGISTERS (38)
R REGISTERS (38)
PROGRAM FLAG (39)
CARRY FLAG (39)
DECIMAL CARRY FLAG (39)
ZERO FLAG (39)
ACCUMULATOR (40)
STACK OPERATIONS (41)
OVERVIEW (41)
STACK REGISTERS (42)
STACK OPERATION EXAMPLE (43)
PROGRAM COUNTER (44)
ONE ADDRESS SKIPPING (45)
MULTI-ADDRESS JUMPING (46)
ADDRESSING MODE (47)
OVERVIEW (47)
IMMEDIATE ADDRESSING MODE (47)
DIRECTLY ADDRESSING MODE (47)
INDIRECTLY ADDRESSING MODE (47)
TO ACCESS DATA in RAM BANK 0 (48)
TO ACCESS DATA in RAM BANK 1 (48)
SYSTEM REGISTER (49)
OVERVIEW (49)
SYSTEM REGISTER ARRANGEMENT (BANK 0) (49)
BYTES of SYSTEM REGISTER (49)
BITS of SYSTEM REGISTER (51)
POWER ON RESET (55)
OVERVIEW (55)
EXTERNAL RESET DESCRIPTION (56)
LOW VOLTAGE DETECTOR (LVD) DESCRIPTION (57)
OSCILLATORS (58)
OVERVIEW (58)
CLOCK BLOCK DIAGRAM (58)
OSCM REGISTER DESCRIPTION (59)
EXTERNAL HIGH-SPEED OSCILLATOR (60)
OSCILLATOR MODE CODE OPTION (60)
OSCILLATOR DEVIDE BY 2 CODE OPTION (60)
OSCILLATOR SAFE GUARD CODE OPTION (60)
SYSTEM OSCILLATOR CIRCUITS (61)
External RC Oscillator Frequency Measurement (62)
INTERNAL LOW-SPEED OSCILLATOR (63)
SYSTEM MODE DESCRIPTION (64)
OVERVIEW (64)
NORMAL MODE (64)
SLOW MODE (64)
POWER DOWN MODE (64)
SYSTEM MODE CONTROL (65)
SN8P1700 SYSTEM MODE BLOCK DIAGRAM (65)
SYSTEM MODE SWITCHING (66)
WAKEUP TIME (67)
OVERVIEW (67)
HARDWARE WAKEUP (67)
TIMERS COUNTERS (68)
WATCHDOG TIMER (WDT) (68)
BASIC TIMER 0 (T0) (69)
OVERVIEW (69)
T0M REGISTER DESCRIPTION (69)
T0C COUNTING REGISTER (70)
T0 BASIC TIMER OPERATION SEQUENCE (71)
TIMER COUNTER 0 (TC0) (72)
OVERVIEW (72)
TC0M MODE REGISTER (73)
TC0C COUNTING REGISTER (74)
TC0R AUTO-LOAD REGISTER (75)
TC0 TIMER COUNTER OPERATION SEQUENCE (76)
TC0 CLOCK FREQUENCY OUTPUT (BUZZER) (78)
TC0OUT FREQUENCY TABLE (79)
TIMER COUNTER 1 (TC1) (81)
OVERVIEW (81)
TC1M MODE REGISTER (82)
TC1C COUNTING REGISTER (83)
TC1R AUTO-LOAD REGISTER (84)
TC1 TIMER COUNTER OPERATION SEQUENCE (85)
TC1 CLOCK FREQUENCY OUTPUT (BUZZER) (87)
PWM FUNCTION DESCRIPTION (88)
OVERVIEW (88)
PWM PROGRAM DESCRIPTION (89)
INTERRUPT (90)
OVERVIEW (90)
INTEN INTERRUPT ENABLE REGISTER (91)
INTRQ INTERRUPT REQUEST REGISTER (91)
INTERRUPT OPERATION DESCRIPTION (92)
GIE GLOBAL INTERRUPT OPERATION (92)
INT0 (P0.0) INTERRUPT OPERATION (93)
INT1 (P0.1) INTERRUPT OPERATION (93)
INT2 (P0.2) INTERRUPT OPERATION (94)
T0 INTERRUPT OPERATION (95)
TC0 INTERRUPT OPERATION (96)
TC1 INTERRUPT OPERATION (97)
SIO INTERRUPT OPERATION (98)
MULTI-INTERRUPT OPERATION (99)
OVERVIEW (101)
SIOM MODE REGISTER (102)
SIOB DATA BUFFER (103)
SIOR REGISTER DESCRIPTION (103)
SIO MASTER OPERATING DESCRIPTION (104)
RISING EDGE TRANSMITTER/RECEIVER MODE (104)
FALLING EDGE TRANSMITTER/RECEIVER MODE (105)
RISING EDGE RECEIVER MODE (106)
FALLING EDGE RECEIVER MODE (107)
SIO SLAVE OPERATING DESCRIPTION (108)
RISING EDGE TRANSMITTER/RECEIVER MODE (109)
FALLING EDGE TRANSMITTER/RECEIVER MODE (110)
RISING EDGE RECEIVER MODE (111)
FALLING EDGE RECEIVER MODE (112)
SIO INTERRUPT OPERATION DESCRIPTION (113)
I/O PORT (114)
OVERVIEW (114)
I/O PORT FUNCTION TABLE (115)
PULL-UP RESISTERS (116)
I/O PORT DATA REGISTER (119)
8-CHANNEL ANALOG TO DIGITAL CONVERTER (121)
OVERVIEW (121)
ADM REGISTER (122)
ADR REGISTERS (122)
ADB REGISTERS (122)
ADC CONVERTING TIME (124)
ADC CIRCUIT (125)
OVERVIEW (126)
DAM REGISTER (126)
D/A CONVERTER OPERATION (127)
CODING ISSUE (128)
TEMPLATE CODE (128)
CHIP DECLARATION IN ASSEMBLER (133)
PROGRAM CHECK LIST (133)
INSTRUCTION SET TABLE (134)
ELECTRICAL CHARACTERISTIC (135)
ABSOLUTE MAXIMUM RATING (135)
STANDARD ELECTRICAL CHARACTERISTIC (135)
SN8P1700 Series (OTP) (135)
PACKAGE INFORMATION (136)
P-DIP18 PIN (136)
SOP18 PIN (137)
SSOP20 PIN (138)
S-DIP28 PIN (139)
SOP28 PIN (140)
QFP 44 PIN (141)
SSOP 48 PIN (142)
P-DIP 48 PIN (143)
P-DIP 40 PIN (144)
PRODUCT OVERVIEW
GENERAL DESCRIPTION
The SN8P1700 is a series of 8-bit micro-controller including SN8P1702, SN8P1704, SN8P1706, SN8P1707 and SN8P1708. This series is utilized with CMOS technology fabrication and featured with low power consumption and high performance by its unique electronic structure.
These chips are designed with the excellent IC structure including the large program memory OTP ROM, the massive data memory RAM, one 8-bit basic timer (T0), two 8-bit timer counters (TC0, TC1), a watchdog timer, up to seven interrupt sources (T0, TC0, TC1, SIO, INT0, INT1, INT2), a 7-bit DAC converter, an 8-channel ADC converter with 8-bit/12-bit resolution, two channel PWM output (PWM0, PWM1), tw0 channel buzzer output (BZ0, BZ1) and 8-level stack buffers. Besides, the user can choose desired oscillator configurations for the controller. There are four oscillator configurations to select for generating system clock, including High/Low Speed crystal, ceramic resonator or cost-saving RC. SN8P1700 series also includes an internal RC oscillator for slow mode controlled by programming.
FEATURES SELECTION TABLE
Timer PWM Wakeup CHIP ROM RAM Stack T0 TC0TC1I/O ADC DAC Buzzer SIO Pin no. Package
SN8P1702 1K*16
64
- V - 124ch - 1 - 3 DIP18/SOP18
SN8P1704 2K*16 128 - V V 185ch 1ch 2 1 8 SKDIP28/SOP28
SN8P1706 V V V 308ch 1ch 2 1 9 DIP40 SN8P1707 V V V 338ch 1ch 2 1 9 QFP44 SN8P1708
4K*16 256 8
V
V
V
33
8ch
1ch
2
1
9
DIP48/SSOP48
Table 1-1. Selection Table of SN8P1700
MASK/OTP Relative Table
Mask Version Package Form OTP Chip for Verification Assembler Declaration SN8A1702A DIP18/SOP18/SSOP20 SN8P1702 CHIP SN8P1702 SN8A1704A SKDIP28/SOP28 SN8P1704 CHIP SN8P1704 SN8A1706A DIP40 SN8P1706 CHIP SN8P1706 SN8A1707A QFP44 SN8P1707 CHIP SN8P1707 SN8A1708A DIP48/SSOP48 SN8P1708
CHIP SN8P1708
Note: Recommend SN8P1702A to replace SN8P1702 in new design. Refer SN8P1702A datasheet for details.
Table 1-2. MASK/OTP Relative Table
ADC GRADE TABLE
CHIP PARAMETER MIN MAX UNITS REMARK
Resolution 12 Bits
No Mission Code 8 12 Bits
SN8P170X
Differential Nonlinearity (DNL) 16 LSB
170X:
1702~1708
Resolution 12 Bits
No Mission Code 10 12 Bits
SN8P170X-12
Differential Nonlinearity (DNL) 4 LSB
170X:
1702~1708
Table 1-3. ADC Grade Table
SN8P1702 FEATURES
?Memory configuration ?Two interrupt sources
OTP ROM size: 1K * 16 bits.One internal interrupts: TC0.
RAM size: 64 * 8 bits.One external interrupts: INT0.
?I/O pin configuration (Total 12 pins)?An 4-channel ADC with 8-bit/12-bit resolution Input only: P0
Bi-directional: P1, P4, P5?One channel PWM output. (PWM0)
Wakeup: P0, P1 ?One channel Buzzer output. (BZ0)
Pull-up resisters: P0, P1, P4, P5
External interrupt: P0?Dual clock system offers three operating modes P4 pins shared with ADC inputs.External high clock: RC type up to 10 MHz
External high clock: Crystal type up to 16 MHz
?One 8-bit timer counters. (TC0).Internal low clock: RC type 16KHz(3V), 32KHz(5V) ?On chip watchdog timer.Normal mode: Both high and low clock active
?Eight levels stack buffer.Slow mode: Low clock only
Sleep mode: Both high and low clock stop
?59 powerful instructions
Four clocks per instruction cycle
All of instructions are one word length. ?Package (Chip form support)
Most of instructions are one cycle only. PDIP 18 pins
All ROM area lookup table function (MOVC) SOP 18 pins / SSOP20 (MASK type only) Notice:
1. Declare “CHIP SN8P1702” in assembler.
2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information
3. Call @SET_PUR macro at least one time to avoid sleep mode fail.
SN8P1704 FEATURES
?Memory configuration ?Six interrupt sources
OTP ROM size: 2K * 16 bits.Three internal interrupts: TC0, TC1, SIO.
RAM size: 128 * 8 bits.Three external interrupts: INT0, INT1, INT2.
?I/O pin configuration (Total 18 pins)? A 5-channel ADC with 8-bit/12-bit resolution.
Input only: P0
Bi-directional: P1, P4, P5?One channel DAC with 7-bit resolution.
Wakeup: P0, P1
Pull-up resisters: P0, P1, P4, P5 ?SIO function.
External interrupt: P0?Two channel PWM output. (PWM0, PWM1) P4 pins shared with ADC inputs.?Two channel Buzzer output. (BZ0, BZ1)
?Two 8-bit timer counters. (TC0, TC1).?Dual clock system offers three operating modes ?On chip watchdog timer.External high clock: RC type up to 10 MHz
?Eight levels stack buffer.External high clock: Crystal type up to 16 MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V) ?60 powerful instructions Normal mode: Both high and low clock active Four clocks per instruction cycle Slow mode: Low clock only
All of instructions are one word length. Sleep mode: Both high and low clock stop
Most of instructions are one cycle only.
All ROM area lookup table function (MOVC) ?Package (Chip form support)
Support hardware multiplier (MUL). SOP 28 pins
pins
28
SKDIP
Notice:
1. Declare “CHIP SN8P1704” in assembler.
2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information
3. Call @SET_PUR macro at least one time to avoid sleep mode fail.
SN8P1706 FEATURES
?Memory configuration ?Seven interrupt sources
OTP ROM size: 4K * 16 bits.Four internal interrupts: T0, TC0, TC1, SIO.
RAM size: 256 * 8 bits (bank 0 and bank 1).Three external interrupts: INT0, INT1, INT2.
?I/O pin configuration (Total 30 pins)?An 8-channel ADC with 8-bit/12-bit resolution.
Input only: P0
Bi-directional: P1, P2, P4, P5?One channel DAC 7bit resolution.
Wakeup: P0, P1
Pull-up resisters: P0, P1, P2, P4, P5
External interrupt: P0?SIO function.
P4 pins shared with ADC inputs.?Two channel PWM output. (PWM0, PWM1)
?Two channel Buzzer output. (BZ0, BZ1)
?An 8-bit basic timer. (T0).
?Two 8-bit timer counters. (TC0, TC1).?Dual clock system offers three operating modes ?On chip watchdog timer.External high clock: RC type up to 10 MHz
?Eight levels stack buffer.External high clock: Crystal type up to 16 MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V) ?60 powerful instructions Normal mode: Both high and low clock active Four clocks per instruction cycle Slow mode: Low clock only
All of instructions are one word length. Sleep mode: Both high and low clock stop
Most of instructions are one cycle only.
All ROM area lookup table function (MOVC)
Support hardware multiplier (MUL). ?Package (Chip form support)
40
pins
P-DIP
Notice:
1. Declare “CHIP SN8P1706” in assembler.
2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information
SN8P1707/SN8P1708 FEATURES
?Memory configuration ?Seven interrupt sources
OTP ROM size: 4K * 16 bits.Four internal interrupts: T0, TC0, TC1, SIO.
RAM size: 256 * 8 bits (bank 0 and bank 1).Three external interrupts: INT0, INT1, INT2.
?I/O pin configuration (Total 33 pins)?An 8-channel ADC with 8-bit/12-bit resolution.
Input only: P0
Bi-directional: P1, P2, P4, P5?One channel DAC with 7-bit resolution.
Wakeup: P0, P1
Pull-up resisters: P0, P1, P2, P4, P5
External interrupt: P0?SIO function.
P4 pins shared with ADC inputs.?Two channel PWM output. (PWM0, PWM1)
?Two channel Buzzer output. (BZ0, BZ1)
?An 8-bit basic timer. (T0).
?Two 8-bit timer counters. (TC0, TC1).?Dual clock system offers three operating modes ?On chip watchdog timer.External high clock: RC type up to 10 MHz
?Eight levels stack buffer.External high clock: Crystal type up to 16 MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V) ?60 powerful instructions Normal mode: Both high and low clock active Four clocks per instruction cycle Slow mode: Low clock only
All of instructions are one word length. Sleep mode: Both high and low clock stop
Most of instructions are one cycle only.
All ROM area lookup table function (MOVC) Support hardware multiplier (MUL). ?Package (Chip form support) QPF 44 pins (SN8P1707)
SSOP 48 pins (SN8P1708)
PDIP 48 pins (SN8P1708)
Notice:
1. Declare “CHIP SN8P1707” for SN8P1707 in assembler.
2. Declare “CHIP SN8P1708” for SN8P1708 in assembler.
3. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information
SYSTEM BLOCK DIAGRAM
Figure 1-1.Simplified System Block Diagram
PIN ASSIGNMENT
Format Description:SN8P17XXY
Y = Q > QFP,P > PDIP,K > SKDIP,S > SOP,X> SSOP
OTP Type:
SN8P1702 (SOP 18PIN)
SN8P1702 (PDIP 18PIN)
18VDD/VPP
P0.0/INT0 1
U
17XIN
RST 2
16XOUT
P1.1 3
15P5.0
P1.0 4
14P5.1
VSS 5
P4.3/AIN3 6 13P5.2
P4.2/AIN27 12P5.3
P4.1/AIN18 11P5.4/BZ0/PWM0
P4.0/AIN09 10VDD
SN8P1702P
SN8P1702S
MASK Type:
SN8A1702A (SOP 18PIN)
SN8A1702A (PDIP 18PIN)
SN8A1702A (SSOP 20PIN)
18VDD
P0.0/INT01
U
17XIN
RST2
16XOUT
P1.13
15P5.0
P1.04
14P5.1
VSS5
P4.3/AIN36 13P5.2
P4.2/AIN27 12P5.3
P4.1/AIN18 11P5.4/BZ0/PWM0
P4.0/AIN09 10VDD
SN8A1702AP
SN8A1702AS
VSS1 U20P1.0
VSS2 19P1.1
P4.3/AIN33 18RST
P4.2/AIN24 17P0.0/INT0
P4.1/AIN15 16VDD
P4.0/AIN06 15XIN
AVREFH7 14XOUT
VDD8 13P5.0
P5.39 12P5.1
P5.210 11P5.4/BZ0/PWM0
SN8A1702AX
Only MASK type support SSOP20 package
OTP Type:
SN8P1704 (SOP 28PIN)
SN8P1704 (SKDIP 28PIN)
P1.4 1 U 28 RST
P1.3 2 27 P0.2/INT2
VDD 3 26 P0.1/INT1
P1.2 4 25 P0.0/INT0
P1.1 5 24 VDD/VPP
P1.0 6 23 XIN
VSS7 22 XOUT
P4.4/AIN48 21 VSS
P4.3/AIN39 20 P5.0/SCK
P5.1/SI
P4.2/AIN210 19
P5.2/SO
P4.1/AIN111 18
P4.0/AIN012 17
P5.3/BZ1/PWM1
P5.4/BZ0/PWM0
AVREFH13 16
DAO
VDD14 15
SN8P1704K
SN8P1704S
MASK Type:
SN8A1704A (SOP 28PIN)
SN8A1704A (SKDIP 28PIN)
P1.41 U 28RST
P1.32 27P0.2/INT2
VDD3 26P0.1/INT1
P1.24 25P0.0/INT0
P1.15 24VDD
P1.06 23XIN
VSS7 22XOUT
P4.4/AIN48 21VSS
P4.3/AIN39 20P5.0/SCK
P4.2/AIN210 19P5.1/SI
P4.1/AIN111 18P5.2/SO
P4.0/AIN012 17P5.3/BZ1/PWM1
AVREFH13 16P5.4/BZ0/PWM0
VDD14 15DAO
SN8A1704AK
SN8A1704AS
OTP Type:
SN8P1706 (P-DIP 40PIN)
P1.5 1 U 40RST
P1.4 2 39P0.2/INT2
P1.3 3 38P0.1/INT1
VDD 4 37P0.0/INT0
P1.2 5 36VDD/VPP
P1.1 6 35XIN
P1.0 7 34XOUT
P2.0 8 33VSS
P2.1 9 32P2.4
P2.2 1031P5.0/SCK
P2.3 1130P5.1/SI
VSS 1229P5.2/SO
P4.7/AIN7 1328P5.3/BZ1/PWM1
P4.6/AIN6 1427P5.4/BZ0/PWM0
P4.5/AIN5 1526P5.5
P4.4/AIN4 1625P5.6
P4.3/AIN3 1724P5.7
P4.2/AIN2 1823DAO
P4.1/AIN1 1922VDD
P4.0/AIN0 2021AVREFH
SN8P1706P
MASK Type:
SN8A1706A (P-DIP 40PIN)
P1.5 1 U 40RST
P1.4 2 39P0.2/INT2
P1.3 3 38P0.1/INT1
VDD 4 37P0.0/INT0
P1.2 5 36NC
P1.1 6 35XIN
P1.0 7 34XOUT
P2.0 8 33VSS
P2.1 9 32P2.4
P2.2 1031P5.0/SCK
P2.3 1130P5.1/SI
AVREFL 1229P5.2/SO
P4.7/AIN7 1328P5.3/BZ1/PWM1
P4.6/AIN6 1427P5.4/BZ0/PWM0
P4.5/AIN5 1526P5.5
P4.4/AIN4 1625P5.6
P4.3/AIN3 1724P5.7
P4.2/AIN2 1823DAO
P4.1/AIN1 1922VDD
P4.0/AIN0 2021AVREFH
SN8A1706AP
For OTP type (SN8P1706) compatible issue, please connect AVREFL pin of MASK type (SN8A1706A) to the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage.
OTP Type:
SN8P1707 (QFP 44PIN)
X I N
X O U T
V S S
P 2.7
P 2.6
P 2.5
P 2.4
P 5.0/S C K
P 5.1/S I
P 5.2/S O
P 5.3/B Z 1/P W M 1
44 43 42 4140393837363534
VPP/VDD 1 O 33P5.4/BZ0/PWM0 P0.0/INT0 2 32P5.5 P0.1/INT1 3 31P5.6 P0.2/INT2 4
30P5.7 RST 5 29DAO P1.5 6 SN8P1707Q 28VDD P1.47 27AVREFH P1.38 26P4.0/AIN0 VDD 9 25P4.1/AIN1 P1.210 24P4.2/AIN2 P1.111
23P4.3/AIN3 12 13 14 1516171819202122
P 1.0
P 2.0
P 2.1
P 2.2
P 2.3
V S S
A V S S
P 4.7/A I N 7
P 4.6/A I N 6
P 4.5/A I N 5
P 4.4/A I N 4
MASK Type:
SN8A1707A (QFP 44PIN)
X I N
X O U T
V S S
P 2.7
P 2.6
P 2.5
P 2.4
P 5.0/S C K
P 5.1/S I
P 5.2/S O
P 5.3/B Z 1/P W M 1
44 43 42 4140393837363534 NC 1 O 33P5.4/BZ0/PWM0
P0.0/INT0 2 32P5.5 P0.1/INT1 3 31P5.6 P0.2/INT2 4 30P5.7
RST 5 29DAO P1.5 6 SN8A1707AQ 28VDD P1.47 27AVREFH P1.38 26P4.0/AIN0 VDD 9 25P4.1/AIN1 P1.210 24P4.2/AIN2 P1.111 23P4.3/AIN3
12 13 14 1516171819202122
P 1.0
P 2.0
P 2.1
P 2.2
P 2.3
V S S
A V R E F L
P 4.7/A I N 7
P 4.6/A I N 6
P 4.5/A I N 5
P 4.4/A I N 4
For OTP type (SN8P1707) compatible issue, please connect AVREFL pin of MASK type (SN8A1707A) to
the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage.