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BK2471 Datasheet 1.2

BK2471 Datasheet V1.2

Preliminary Specification

联系人:雷小姐:159******** QQ:1025369666

Beken Corporation

Building 41, Capital of Tech Leaders, 1387 Zhangdong Road,

Zhangjiang High-Tech Park, Pudong New District, Shanghai, China

Tel: (86)21 51086811

Fax: (86)21 60871277

This document contains information that may be proprietary to, and/or secrets of, Beken Corporation. The contents of this document should not be disclosed outside the companies without specific written permission. Disclaimer: Descriptions of specific implementations are for illustrative purpose only, actual hardware implementation

may differ.

Revision History

Table of Contens

1General Description (6)

1.1Overview (6)

1.2Block Diagram (6)

1.3Features (7)

1.4Application (7)

2Pin Information (8)

2.1QFN56 (8)

2.2QFN32 (11)

3Function Description (13)

3.1Memory Address Mapping (13)

3.2Interrupt and Clock Unit (14)

3.3GPIO (14)

3.4ADC (14)

3.5UART (15)

3.6I2C-SMBus (15)

3.7SPI (16)

3.8PWM Timer (17)

3.9Watch dog (17)

4Electrical Specifications (17)

4.1General Specification (17)

4.2RF characterization (17)

5Package Information (18)

5.1QFN 7X7 56PIN: (18)

5.2QFN4X4 32PIN: (19)

6Application Schematic (20)

6.1QFN7X7 56PIN: (20)

7Order Information (20)

8Contact Information (20)

List of Figures

FIGURE 1 BLOCK DIAGRAM (6)

FIGURE 2 BK2471 QFN56PIN ASSIGNMENT (8)

FIGURE 3 BK2471 QFN56PIN ASSIGNMENT (11)

FIGURE 3 BK2471 QFN56PIN PACKAGE INFORMATION (19)

FIGURE 3 BK2471 QFN32PIN PACKAGE INFORMATION (20)

List of tables

TABLE 1 BK2471 QFN56 PIN DESCRIPTION (9)

TABLE 2 BK2471 QFN56 PIN DESCRIPTION (11)

TABLE 2 THE MEMORY MAPPING (13)

TABLE 3 GENERAL CHARACTERISTICS (17)

TABLE 4 BEKEN PROPRIETORY 2.4GHZ MODE RF CHARACTERISTICS (17)

TABLE 5 ORDER INFORMATION (20)

1 General Description

1.1 Overview

The BK2471 chip is a highly integrated SoC, which embedded Beken 2.4GHz proprietary protocol. It integrates a high-performance 2.4GHz RF transceiver, rich features baseband, ARM-core MCU and various peripheral IOs. It uses up-to-4Mbytes external Flash to execute the programmable protocol to support customized applications.

1.2 Block Diagram

Figure 1 Block Diagram

1.3 Features

●Supporting Beken 2.4GHz Proprietary protocol

●ARM968 Core MCU integrated

●External Flash up-to-4Mbytes for Program and 24KB RAM for Data

●Low-power 2.4GHz Transceiver

●Operation voltage from 1.8V to 3.6 V

●-92 dBm sensitivity at 1 Mbps data rate, -98 dBm sensitivity at 250 Kbps

data rate and +5dBm transmit power for 2.4GHz protocol application

●External power-amplifier supporting

●Clock

?16 MHz crystal reference clock

?96MHz optional clock provided by internal DPLL

?Internal 32kHz low-power oscillator with auto-calibration (±200ppm)

●Interface and peripheral units

?FLASH programming, JTAG, Dual I2Cs, SPI and UART interface

?Integrated OTP for customization

?On-chip high accurate temperature sensor

?On-chip 7-channel 10bit general ADC

?6-outputs PWM

?Real-time counter

●Package Type

?56-pin QFN 7mmx7mm package

1.4 Application

●Wireless Self-Timer

●Wireless Keyboards

●Wireless Gamepad

●LED Lighting Remote Control

●Wireless aerocraft

2 Pin Information

2.1 QFN56

The QFN56 package format is used for the full functions application, and it has total 34 GPIO available. The pin assignment for QFN56 package is shown in Figure 2.

P27P35VOUTBOOST

BOOST_CP1VCCMCU VDDSPI P36VCCRF TSTEN P15P14P30P01P00P24P 32

F L S _S I

P 25

P 02

P 03

P 20

F L S _H O L D

F L S _S C K

P 05

P 17

V C C X T A L

X T A L I

X T A L O

F L S _C S N

F L S _S O

F L S _W P

VPP P37P31

P33P16P34P 13

P 12

P 10

P 11

P 06

P 07

P26P40P04

P41V C C I F

A D C V R E F P 21

P 22

P 23

VDDPA15ANT X T A L 32K

BOOST_CP2

Figure 2 BK2471 QFN56Pin Assignment

Table 1 BK2471 QFN56 Pin Description

2.2 QFN32

X T A L O

P35BOOT_CP2BOOT_CP1VCCMCU VDDSPI VCCRF TSTEN P 13

P10

P04P15P14P30VOUTBOOST

P 31

P 02

P 03

P 20

P 32

X T A L I

V C C X

T A L

ANT V C C I F

A D C V R E F P 21

P 22

P 23

P05VPP

P 06P 07

Figure 3 BK2471 QFN56Pin Assignment

Table 2 BK2471 QFN56 Pin Description

3 Function Description

3.1 Memory Address Mapping

Table 3 The Memory Mapping

3.2 Interrupt and Clock Unit

The MCU core clock can be selected from three clock sources: 32KHz clock, 16 MHz clock and 96 MHz DPLL.

The ARM968E-S supports two interrupt level. The FIRQ has higher priority than nIRQ. In the BK2471, all the interrupts can be set as FIRQ or nIRQ. All interrupt can be enabled, disabled, and cleared. There are two low power modes: MCU stop and sleep, and any interrupt can be configured to be a wake up source to let MCU exit low power mode.

3.3 GPIO

There are totally 34 general purpose input/output ports (GPIO). All the 34 ports can be used for general I/O with selectable direction for each bit, or these lines can be used for specialized functions.

3.4 ADC

An 8bits SAR-ADC is integrated in the BK2471. Total 8 channels can be selected used for ADC transfer. The ADC supports continue mode and single transfer mode, and the sample rate can be 1 KHz to 32KHz. In single transfer mode, it will generate interrupt every time after transform.

The ADC has four work modes they are sleep mode, single mode, and software mode and continue mode.

IDLE mode(mode==00): ADC is in idle state.

Single mode(mode==01): The ADC will enter idle mode when transfer is done and waiting MCU to read the result. You should write mode=1 again for another transfer.

Controlled by software (mode==10): In this mode, interrupt will be triggered after transfer and wait MCU to read. The interrupt will be cleared after MCU read, and then the transfer will start again.

Continue mode(mode==11):The ADC will work at the sample rate set by register. The sample rate can be calculated by the next formula:

F_sample = input ADC clock/(2^(ADC_CLK_RATE+2) / 36(or 18))

The highest sample rate is 32k

The local interrupt flag of ADC need not be cleared by software; it will be set after transform and be cleared after the result has been read out. But the ADC INTstored ICU should be cleared after the ADC INT service finished.

The range of input voltage is from 0v to 1.5V. If the input voltage more than 1.5V, a resistor can be added to decrease the input voltage like the next diagram.

Note: There are eight GPIO can be ADC input. When used as this:

Voltage=data [9:0]/448; the saturate voltage is 1.5 volt.

3.5 UART

The UART interface has 128 bytes FIFO for both TX and RX. It will generate interrupt request when there is risk or event of FIFO underflow or overflow. For the RX, it will generate interrupt if found parity bit check error or stop bit check error.

When the UART RX line goes from idle state (‘HIGH’) to active state (‘LOW’) for

a set UART clock cycle, it will generate wake up interrupt to activate MCU clock.

3.6 I2C-SMBus

The I2C I/O interface is a two-wire, bi-directional serial bus. The I2C is compliant with the System Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to the interface by the system controller are byte oriented with the I2C interface autonomously controlling the serial transfer of the data.

Data can be transferred at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the I2C specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus.

The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation.

It is assumed the reader is familiar with the I2C-Bus Specification -- Version 2.0 and system Management Bus Specification -- Version 1.1.

The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free.

3.7 SPI

The Enhanced Serial Peripheral Interface (SPI) provides access to a flexible, full-duplex synchronous serial bus. SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slaves.

There are four pins for SPI interface. The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI is operating as a master and an input when SPI is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode.

The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI is operating as a master and an output when SPI is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register.

In slave mode, the data on MOSI are sampled at the middle of period of every bit. In master mode, the data on MISO are sampled at the last clock period to acquire the maximal setup time.

3.8 PWM Timer

There are six timers, all of them is 16 bit and can be works as PWM waveform generator. The PWM waveform can be output to GPIO to drive external device such as LED.

3.9 Watch dog

The watch dog is used to reset the whole chip when the firmware runs out of order.

4 Electrical Specifications

4.1 General Specification

Table 4 General Characteristics

4.2 RF characterization

Table 5 Beken Proprietory 2.4GHz mode RF Characteristics

5 Package Information

5.1 QFN 7X7 56PIN:

Figure 4 BK2471 QFN56Pin Package Information 5.2 QFN4X4 32PIN:

Figure 5 BK2471 QFN32Pin Package Information

6 Application Schematic

6.1 QFN7X7 56PIN:

TBD

7 Order Information

Table 6 Order Information

8 Contact Information

Beken Corporation Technical Support Center

Shanghai office

Building 41, 1387 Zhangdong Road, Zhangjiang High-Tech Park, Pudong New District, Shanghai, China Phone: 86-21-51086811 Fax: 86-21-60871089 Postal Code: 201203 Email: info@https://www.wendangku.net/doc/431217539.html,

Website: https://www.wendangku.net/doc/431217539.html,

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