ADM6996F中文资料
An Infineon Technologies Company ADM6996F
6 port 10/100 Mb/s
Single Chip Ethernet Switch Controller
Data Sheet
Version 1.02
Infineon-ADMtek Co Ltd
Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. Infineon-ADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Infineon-ADMtek Co Ltd reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them
The products may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. To obtain latest documentation please contact you local Infineon-ADMtek Co Ltd sales office or visit Infineon-ADMtek Co Ltd’s website at
https://www.wendangku.net/doc/4d1537212.html,
*Third-party brands and names are the property of their respective owners.
Copyright 2004 by Infineon-ADMtek Co Ltd Incorporated All Rights Reserved.
About this Manual
General Release
Intended Audience
Infineon-ADMtek Co Ltd’s Customers
Structure
This Data sheet contains 6 chapters
Chapter 1 Product Overview
Chapter 2 Interface Description
Chapter 3 Function Description
Chapter 4. Register Description
Chapter 5. Electrical Specification
Chapter 6. Packaging
Revision History
Change
Date Version
07 October 2003 1.0 1. First release of ADM6996F
17 November 2003 1.01 2. Updated Section 4.3.12 & 3.4
12 January 2004 1.02 3. Updated Section 5.3.3 - 6, 5.3.8 & 5.3.9 28 April 2004 1.03 Infineon ADMtek updated logo Customer Support
Infineon-ADMtek Co Ltd,
2F, No.2, Li-Hsin Rd.,
Science-based Industrial Park,
Hsinchu, 300, Taiwan, R.O.C.
Sales Information
Tel + 886-3-5788879
Fax + 886-3-5788871
Table of Contents
Chapter 1 Product Overview........................................................................................1-1 1.1 Overview..........................................................................................................1-1 1.2 Features............................................................................................................1-2 1.3 Applications.....................................................................................................1-2
Diagram.................................................................................................1-3 1.4 Block
1.5 Abbreviations...................................................................................................1-3 1.6 Conventions.....................................................................................................1-5
1.6.1 Data Lengths............................................................................................1-5
1.6.2 Pin Types..................................................................................................1-5
1.6.2 Register Types..........................................................................................1-5 Chapter 2 Interface Description...................................................................................2-1
2.1 Pin Diagram.....................................................................................................2-1 2.2 Pin Description by Function............................................................................2-2
2.2.1 Twisted Pair Interface..............................................................................2-2
2.2.2 5th Port (MII) Interfaces..........................................................................2-2
2.2.3 6th Port (MII) Interfaces..........................................................................2-3
2.2.4 LED Interface...........................................................................................2-5
2.2.5 EEPROM/Management Interface............................................................2-6
2.2.6 Power/Ground, 48 pins............................................................................2-6
2.2.7Miscellaneous..........................................................................................2-6 Chapter 3 Function Description...................................................................................3-1
3.1 Functional Descriptions...................................................................................3-1 3.2 10/100M PHY Block.......................................................................................3-1 3.3 100Base-X Module..........................................................................................3-1 3.4 100Base-X Receiver........................................................................................3-2
3.4.1 A/D Converter..........................................................................................3-2
3.4.2 Adaptive Equalizer and timing Recovery Module...................................3-2
3.4.3 NRZI/NRZ and Serial/Parallel Decoder..................................................3-2
3.4.4 Data De-scrambling.................................................................................3-3
3.4.5 Symbol Alignment....................................................................................3-3
3.4.6 Symbol Decoding.....................................................................................3-3
3.4.7 Valid Data Signal.....................................................................................3-3
3.4.8 Receive Errors.........................................................................................3-4
3.4.9 100Base-X Link Monitor..........................................................................3-4
3.4.10 Carrier Sense...........................................................................................3-4
3.4.11 Bad SSD Detection...................................................................................3-4
3.4.12 Far-End Fault..........................................................................................3-5 3.5 100Base-TX Transceiver.................................................................................3-5
3.5.1 Transmit Drivers......................................................................................3-5
3.5.2 Twisted-Pair Receiver..............................................................................3-5 3.6 10Base-T Module.............................................................................................3-5
3.6.1 Operation Modes.....................................................................................3-6
3.6.2 Manchester Encoder/Decoder.................................................................3-6
3.6.3 Transmit Driver and Receiver.................................................................3-6
3.6.4 Smart Squelch..........................................................................................3-6
3.7 Carrier Sense....................................................................................................3-7 3.8 Jabber Function................................................................................................3-7 3.9 Link Test Function...........................................................................................3-7 3.10 Automatic Link Polarity Detection..............................................................3-8 3.11 Clock Synthesizer........................................................................................3-8 3.12 Auto Negotiation..........................................................................................3-8 3.13 Memory Block.............................................................................................3-8 3.14 Switch Functional Description.....................................................................3-9 3.15 Basic Operation............................................................................................3-9
3.15.1 Address Learning.....................................................................................3-9
3.15.2 Address Recognition and Packet Forwarding.......................................3-10
3.15.3 Address Aging........................................................................................3-10
3.15.4 Back off Algorithm.................................................................................3-10
3.15.5 Inter-Packet Gap (IPG).........................................................................3-10
3.15.6 Illegal Frames........................................................................................3-11
3.15.7 Half Duplex Flow Control.....................................................................3-11
3.15.8 Full Duplex Flow Control......................................................................3-11
3.15.9 Broadcast Storm filter............................................................................3-11 3.16 Auto TP MDIX function................................................................................3-11 3.17 Port Locking...............................................................................................3-12 3.18 VLAN setting & Tag/Untag & port-base VLAN......................................3-12 3.19 Priority Setting...........................................................................................3-13 3.20 LED Display..............................................................................................3-13 Chapter 4 Register Description....................................................................................4-1
4.1 EEPROM Content............................................................................................4-1 4.2 EEPROM Register Map...................................................................................4-1 4.3 EEPROM Register...........................................................................................4-2
4.3.1 Signature Register, offset: 0x00h..............................................................4-2
4.3.2 Configuration Registers, offset: 0x01h ~ 0x09h......................................4-3
4.3.3Reserved Register, offset: 0x0ah..............................................................4-3
4.3.4Configuration Register, offset: 0x0bh......................................................4-4
4.3.5Reserved Register, offset: 0x0ch~0x0dh..................................................4-4
4.3.6 VLAN priority Map Register, offset: 0x0eh.............................................4-4
4.3.7TOS priority Map Register, offset: 0x0fh.................................................4-4
4.3.8Packet with Priority: Normal packet content..........................................4-5
4.3.9VLAN Packet............................................................................................4-5
4.3.10TOS IP Packet..........................................................................................4-1
4.3.11Miscellaneous Configuration Register, offset: 0x10h..............................4-1
4.3.12VLAN mode select Register, offset: 0x11h...............................................4-2
4.3.13Miscellaneous Configuration register, offset: 0x12h..............................4-4
4.3.14VLAN mapping table registers, offset: 0x22h ~ 0x13h............................4-4
4.3.15Reserved Register, offset: 0x27h ~ 0x23h................................................4-4
4.3.16Port0, 1 PVID bit 11 ~ 4 Configuration Register, offset: 0x28h.............4-1
4.3.17Port2, 3 PVID bit 11 ~ 4 Configuration Register, offset: 0x29h.............4-1
4.3.18Port4, 5 PVID bit 11~4 Configuration Register, offset: 0x2ah...............4-1
4.3.19Port6, 7 PVID bit 11~4 Configuration Register, offset: 0x2bh...............4-1
4.3.20Port8 PVID bit 11~4 & VLAN group shift bits Configuration Register..4-1
4.3.21Reserved Register, offset: 0x2dh..............................................................4-2
4.3.22Reserved Register, offset: 0x2eh..............................................................4-2
4.3.23 PHY Restart, offset: 0x2fh........................................................................4-2
4.3.24Miscellaneous Configuration Register, offset: 0x30h..............................4-2
4.3.25 Bandwidth Control Register0~3, offset: 0x31h........................................4-3
4.3.26Bandwidth Control Register 4~5, offset: 0x32h.......................................4-3
4.3.27Bandwidth Control Enable Register, offset: 0x33h..................................4-4 4.4 EEPROM Access.............................................................................................4-4 4.5 Serial Register Map..........................................................................................4-6 4.6 Serial Register Description..............................................................................4-7
4.6.1 Chip Identifier Register, offset: 0x00h.....................................................4-7
4.6.2Port Status 0 Register, offset: 0x01h.......................................................4-7
4.6.3Port Status 1 Register, offset: 0x02h.......................................................4-9
4.6.4Cable Broken Status Register, offset: 0x03h............................................4-9
4.6.5Over Flow Flag 0 Register, offset: 0x3ah..............................................4-10
4.6.6Over Flow Flag 0: Register 0x3bh........................................................4-10
4.6.7Over Flow Flag 2 Register, offset: 0x3ch..............................................4-11 4.7 Serial Interface Timing....................................................................................4-1 4.8 PHY Register Description................................................................................4-2
4.8.1 Control Register, offset: 0x00..................................................................4-2
4.8.2Status Register, offset: 0x01.....................................................................4-4
4.8.3PHY Identifier Register, offset: 0x02.......................................................4-5
4.8.4PHY Identifier Register, offset: 0x03.......................................................4-5
4.8.5Auto Negotiation Advertisement Register, offset : 0x04..........................4-6
4.8.6Auto Negotiation Link Partner Ability Register, offset: 0x0
5..................4-7
4.8.7Auto Negotiation Expansion Register, offset: 0x06.................................4-7
4.8.8Next Page Transmit Register, offset: 0x07.............................................4-8
4.8.9Link Partner Next Page Register, offset: 0x08........................................4-8 Chapter 5 Electrical Specification................................................................................5-1
5.1 TX/FX Interface...............................................................................................5-1
5.1.1TP Interface.............................................................................................5-1
5.1.2 FX Interface.............................................................................................5-1
Characteristics...........................................................................................5-2 5.2 DC
5.2.1 Absolute Maximum Rating.......................................................................5-2
5.2.2 Recommended Operating Conditions......................................................5-2
5.2.3 DC Electrical Characteristics for 3.3V Operation..................................5-2 5.3 AC Characteristics...........................................................................................5-3
5.3.1 Power On Reset........................................................................................5-3
5.3.2 EEPROM Interface Timing......................................................................5-3
5.3.3 10Base-TX MII Input Timing...................................................................5-4
5.3.4 10Base-TX MII Output Timing................................................................5-4
5.3.5 100Base-TX MII Input Timing.................................................................5-5
5.3.6 100Base-TX MII Output Timing..............................................................5-5
5.3.7 SMI Timing...............................................................................................5-6
5.3.8 GPSI(7-wire) Input Timing......................................................................5-6
5.3.9GPSI(7-wire) Output Timing...................................................................5-7
5.3.10 Serial Management Interface (MDC/MDIO) Timing..............................5-8 Chapter 6 Packaging......................................................................................................6-1
6.1 128 Pin PQFP Outside Dimension...................................................................6-1
List of Figures
Figure 1-1 ADM6996F Block Diagram...........................................................................1-3 Figure 2-1 4 TP/FX PORT + 2 MII PORT 128 Pin Diagram..........................................2-1
Chapter 1 Product Overview
1.1 Overview
The ADM6996F is a high performance, low cost, highly integrated (Controller, PHY and Memory) four-port 10/100 Mbps TX/FX plus two 10/100 MAC port Ethernet switch controller with all ports supporting 10/100 Mbps Full/Half duplex. The ADM6996F is intended for applications to stand alone bridge for low cost SOHO markets such as 5Port, Router applications. The 2nd MAC can be configured as PCS type MII with 10/100 PHY integrated.
ADM6996F provides the most advance functions such as: 802.1p(Q.O.S.), 802.1q(VLAN), Port MAC address Locking, Management, Port Status, TP Auto-MDIX, 25M Crystal & Extra MII port functions to meet customer requests on Switch demand.
The ADM6996F also supports Back Pressure in Half-Duplex mode and 802.3x Flow Control Pause packet in Full-Duplex mode to prevent packet loss when buffers are full.
When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the ADM6996F will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode.
The built-in SRAM used for the packet buffer and address learning table is divided into 256 bytes/block to achieve the optimized memory utilization through complicated link list on packets with various lengths.
ADM6996F also supports priority features by Port-Base, VLAN and IP TOS field checking. Users can easily set different priority modes in individual ports, through a small low-cost micro controller to initialize or on-the-fly to configure. Each output port supports four queues in the way of fixed N: 1 fairness queuing to fit the bandwidth demand on various types of packet such as Voice, Video and data. 802.1Q, Tag/Untag, and up to 16 groups of VLAN are also supported.
An intelligent address recognition algorithm allows ADM6996F to recognize up to 2048 different MAC addresses and enables filtering and forwarding at full wire speed.
Port MAC address Locking function is also supported by ADM6996F to use on Building Internet access to prevent multiple users sharing one port traffic.
1.2 Features
? Supports four 10M/100M auto-detect Half/Full duplex switch ports with TX/FX interfaces and two MII/GPSI ports.
? Supports 2048 MAC addresses table.
? Supports four queue for QoS
? Supports priority features by Port-Based, 802.1p VLAN & IP TOS of packets.
? Supports Store & Forward architecture and performs forwarding and filtering at non-blocking full wire speed.
? Supports buffer allocation with 256 bytes per block
? Supports Aging function Enable/Disable.
? Supports per port Single/Dual color mode with Power On auto diagnostic.
? Supports 802.3x Flow Control pause packet for Full Duplex in case buffer is full.
? Supports Back Pressure function for Half Duplex operation in case buffer is full.
? Supports packet lengths up to 1522 bytes.
? Broadcast Storming Filter function.
? Supports 802.1Q VLAN. Up to 16 VLAN groups are implemented by the last four bits of VLAN ID.
? 2bit MAC clone to support multiple WAN application
? Supports TP interface Auto MDIX function for auto TX/RX swap by strapping-pin.
? Easy Management 32bits smart counter for per port RX/TX byte/packet count, error count and collision count.
? Supports PHY status output for management system.
? 25M Crystal only for the whole system.
? 128 QFP package with 0.18um technology. 1.8V/3.3V power supply.
1.3 Applications
ADM6996F in 128-pin PQFP: SOHO 5-port switch
5-port switch + Router with MII CPU interface.
Clock
EEPROM
EESK
ESD End of Stream Delimiter
FEFI Far End Fault Indication
Effect
Transistor
Field
FET
Pulse
Link
Fast
FLP
Ground
GND
GPSI General Purpose Serial Interface
Gap
Inter-Packet
IPG
LFSR Linear Feedback Shift Register
Controller
Access
Media
MAC
Crossover
MDI
MDIX
Interface
Independent
Media
MII
NRZI Non Return to Zero Inverter
NRZ Non Return to Zero
Sub-layer
Coding
PCS
Physical
Layer
PHY
Physical
Lock
Loop
Phase
PLL
Attachment
Medium
Physical
PMA
Dependent
Medium
Physical
PMD
Service
of
Quality
QoS
Package
Flat
QFP
Quad
Reset
RST
Clock
RXCLK Receive
Data
Receive
RXD
Valid
Data
RXDV
Receive
Errors
Data
RXER
Receive
(Analog receive differential signal)
Negative
Receive
RXN
RXP Receive Positive (Analog receive differential signal) SA
Address
Source
SOHO Small Office Home Office
of
Delimiter
Stream
Start
SSD
Error
Quality
Signal
SQE
Service
of
TOS
Type
Pair
Twisted
TP
Logic
Transistor
TTL
Transistor
Clock
TXCLK Transmission
Data
Transmission
TXD
Enable
TXEN
Transmission
Transmission
Negative
TXN
Positive
TXP
Transmission
1.6 Conventions
1.6.1 Data Lengths
qword
64-bits dword
32-bits word
16-bits byte
8 bits nibble
4 bits
1.6.2 Pin Types
Pin Type Description
I Input
O Output
I/O Bi-directional
OD Open drain
SCHE Schmitt Trigger
PD internal pull-down
PU internal pull-up
1.6.2 Register Types
Register Type Description
RO Read-only
WO Write-only
RW Read/Write
2.2 Pin Description by Function
ADM6996F pins are categorized into one of the following groups:
Section 2.2.1 Twisted Pair Interface
Section 2.2.2 5th Port (MII) Interfaces
Section 2.2.3 6th Port (MII) Interfaces
Section 2.2.4 LED Interface
Section 2.2.5 EEPROM/Management Interface
Section 2.2.6 Power/Ground, 48 pins
Section 2.2.7 Miscellaneous
Note:
“Section 1.6.2 P in Types” can be used for reference.
2.2.1 Twisted Pair Interface
Pin Name
Pin# Type Descriptions RXP[0:4]
6, 14, 21, 29, 33 I/O, Analog Twisted Pair Receive Input Positive. RXN[0:4]
7, 15, 22, 30, 32 I/O, Analog Twisted Pair Receive Input Negative. TXP[0:4]
2, 10, 18, 25, 37 I/O, Analog Twisted Pair Transmit Output Positive. TXN[0:4] 3, 11, 19, 26, 36 I/O,
Analog Twisted Pair Transmit Output Negative.
2.2.2 5th Port (MII) Interfaces
Pin Name
Pin# Type Descriptions P4TXD[0]
Setting
P4TYPE0 106 I/O, 8mA PD Port4 MII transmit data 0 Acts as MII transmit data TXD[0]. Synchronous to the rising edge of TXCLK.
Setting
P4TYPE0 : At power-on-reset, latched as P4 TYPE0.
P4TXD[1] Setting P4TYPE1 105 I/O, 8mA PD Port4 MII Transmit Data bit 1
Synchronous to the rising edge of TXCLK. These pins act as MII TXD[1].
Setting
P4TYPE1 : At power-on-reset, latched as P4 TYPE1.
P4TXD[3:2] 103, 104 I/O, 8mA PD Port4 MII Transmit Data bit 3~2
Synchronous to the rising edge of TXCLK. These pins act
as MII TXD[3:2].
P4FX 62 I PD Port4 FX/TX mode select. Internal pull down.
1: Port4 as FX port.
0: Port4 as TX port.
P4TXEN 114 I/O 8mA PD Port4 MII Transmit Enable. Internal pull down.
P4RXD[0] 74 I PD Port4 MII port receive data 0
These pins act as MII RXD[0]. Synchronous to the rising
edge of P4RXCLK. Internal pull down.
P4RXD[3:1] 102, 101, 100 I PD Port4 MII port receive data 3~0
These pins act as MII RXD[3:0]. Synchronous to the rising
edge of P4RXCLK. Internal pull down.
P4RXDV 73 I PD Port4 MII receive data valid.
Internal pull down.
P4RXER 39 I PD Port4 MII Port Receive Error.
Internal pull down.
P4COL 78 I PD Port4 MII Port Collision input
Internal pull down.
P4CRS 77 I PD Port4 MII Port Carrier Sense
Internal pull down.
P4RXCLK 117 I PD
Port4 MII Port Receive Clock Input
P4TXCLK 115 I PD
Port4 MII Port Transmit clock Input
DHALFP4 107 I PD Port4 MII Port Hardware Duplex input pin.
Low: Full Duplex. High: Half Duplex.
Internal pull down.
LNKFP4 92 I PD Port4 MII Port Hardware Link input pin.
Low: Link OK. High: Link Off.
Internal pull down.
SPDTNP4 51 I PD Port4 MII Port Hardware Speed input pin.
Low: 100M. High: 10M.
Internal pull down.
2.2.3 6th Port (MII) Interfaces
Pin Name
Pin# Type Descriptions P5TXD[0]
Setting
GFCEN 63 I/O, 8mA PU MII transmit data 0 /GPSI TXD Acts as MII transmit data TXD[0]. Synchronous to the rising edge of TXCLK. Setting GFCEN: Global Flow Control Enable.
At power-on-reset, latched as Full Duplex Flow control
setting
“1” to enable flow-control (default ), “0” to disable flow-
control.
P5TXD[1]
Setting
P5GPSI 61 I/O, 8mA PD MII Transmit Data bit 1 Synchronous to the rising edge of TXCLK. These pins act as MII TXD[1]. Setting P5GPSI: Port 5 GPSI Enable.
At power-on-reset, latched as P5 GPSI Enable.
“0” to disable port 5 GPSI (default ), “1” to enable port 5
GPSI.
P5TXD[3:2] 59, 60 I/O, 8mA PD Port5 MII Transmit Data bit 3~2
Synchronous to the rising edge of TXCLK. These pins act
as MII TXD[3:2].
P5TXEN Setting PHYAS0 66 I/O 8mA PD Port5 MII Transmit Enable. Internal pull down.
Setting
PHYAS0: Chip physical address for multiple chip application
on read EEPROM data. Internal pull down.
Power on reset value PHYAS0 combines with PHYAS1
PHYAS1 PHYAS0
0 0 Master(93C46)
If there is no EEPROM then user must use 93C66 timing to
write chip’s register.
If user put 93C46 with correct Signature then user writes
chip register by 93C46 timing.
If user put 93C66 then data put in Bank0. User can write
chip register by 93C66 timing.
User must assert one SK cycle when CS at idle stage when
write chip internal register.
P5RXD[3:0] 56, 55, 54, 53 I PD Port5 MII port receive data 3~0
These pins act as MII RXD[3:0]. Synchronous to the rising
edge of P5RXCLK. Internal pull down.
P5RXDV 52 I PD Port5 MII receive data valid.
Internal pull down.
P5RXER 68 I PD Port5 MII Port Receive Error.
Internal pull down.
P5COL 58 I PD Port5 MII Port Collision input
Internal pull down.
P5CRS 57 I PD Port5 MII Port Carrier Sense
Internal pull down.
P5RXCLK 72 I PD
Port5 MII Port Receive Clock Input
P5TXCLK 67 I PD
Port5 MII Port Transmit clock Input
DHALFP5 91 I PD Port5 MII Port Hardware Duplex input pin.
Low: Full Duplex. High: Half Duplex.
Internal pull down.
LNKFP5 90 I PD Port5 MII Port Hardware Link input pin.
Low: Link OK. High: Link Off.
Internal pull down.
SPDTNP5 89 I PD Port5 MII Port Hardware Speed input pin.
Low: 100M. High: 10M.
Internal pull down.
2.2.4 LED Interface
Pin Name Pin# Type
Descriptions LNKACT[3:0] 95, 96, 97, 98 O,
8mA
LINK/Activity LED[3:0]. Active low “1” indicates no link activity on cable “0” indicates link okay on cable, but no activity and signals
on idle stage.
“Blinking” indicates link activity on cable.
DUPCOL[3] 110 O, 8mA Duplex/Collision LED[3]. Active low
“1” for half-duplex and “blinking” for collision indication
“0” for full-duplex indication
DUPCOL[2] Setting BPEN 111 O, 8mA, PU Duplex/Collision LED[2]. Active low
“1” for half-duplex and “blinking” for collision indication “0” for full-duplex indication
Setting
BPEN: At power-on-reset, latched as Back Pressure setting
“1” to enable Back-Pressure (defaulted), “0” to disable Back
Pressure.
At power-on-reset, latched as Back Pressure setting “1” to
enable Back-Pressure (defaulted), “0” to disable Back
Pressure.
DUPCOL[1] Setting PHYAS1 112 O, 8mA, PD Duplex/Collision LED[1]. Active low
“1” for half-duplex and “blinking” for collision indication “0” for full-duplex indication
Setting
PHYAS1: Power on Reset latch value combine with TXEN.
Internal pull down. Check pin 66.
DUPCOL[0] Setting ANEN 113 O, 8mA, PU Duplex/Collision LED[0]. Active low
“1” for half-duplex and “blinking” for collision indication “0” for full-duplex indication
Setting
ANEN: On power-on-reset, latched as Auto Negotiation
capability for all ports.
“1” to enable Auto Negotiation ( defaulted by pulled up
internally ),
“0” to disable Auto Negotiation.
LDSPD[3:0] 48, 47, 43, 42 O, 8mA Speed LED[3:0]. Used to indicate corresponding port’s
speed status. “0” for 100Mb/s, “1” for 10Mb/s
2.2.5 EEPROM/Management Interface
Pin Name Pin# Type Descriptions
EDO 84 I, TTL,PU EEPROM Data Output. Serial data input from EEPROM.
This pin is internally pull-up.
EECS 80 O, 4mA,PD EEPROM Chip Select. This pin is active high chip enable
for EEPROM. When RESETL is low, it will be Tri-state.
Internally Pull-down
EECK Setting XOVEN 81 I/O, 4mA PD Serial Clock. This pin is clock source for EEPROM. When RESETL is low, it will be tri-state.
Setting
XOVEN: This pin is internal pull-down. On power-on-reset,
latched as P4~0 Auto MDIX enable or not.
“0” to disable MDIX ( defaulted ), “1” to enable MDIX.
Suggest externally pull up to enable MDIX for all ports.
EDI Setting LEDMODE 79 I/O, 4mA PD EEPROM Serial Data Input. This pin is output for serial data transfer. When RESETL is low, it will be tri-state.
Setting
LEDMODE: This pin is internal pull-down. On power-on-
reset, latched as Dual Color mode or not.
“0” to set Single color mode for LED.
“1” to set Dual Color mode for LED.
2.2.6 Power/Ground, 48 pins
Pin Name
Pin# Type Descriptions GNDA
4,5,12, 13, 20, 27, 28, 34, 35 I Ground Used by AD Block. VCCA2
1, 9, 17, 24, 38 I 1.8V, Power Used by TX Line Driver. VCCAD
8, 16, 23, 31 I 3.3V, Power Used by AD Block. GNDBIAS
126 I Ground Used by Bias Block VCCBIAS
128 I 3.3V, Power Used by Bias Block. GNDPLL
123 I Ground used by PLL VCCPLL
122 I 1.8V, Power used by PLL GNDIK
45, 64, 76, 83, 93, 118 I Ground Used by Digital Core VCCIK
46, 65, 75, 82, 94, 116 I 1.8V, Power Used by Digital Core GNDO
50, 69, 70, 87, 99, 108 I Ground Used by Digital Pad VCC3O 49, 71, 88, 109 I 3.3V, Power Used by Digital Pad.
2.2.7 Miscellaneous
Pin Name
Pin# Type Descriptions CKO25M 85 O, 25M Clock Output.
Pin Name Pin# Type Descriptions
8mA
Control 124 O FET Control Signal.
The pin is used to control FET for 3.3V to 1.8V regulator.
RTX 127 Analog TX Resistor. Add 1.1K %1 resister to GND.
VREF 125 Analog Analog Reference Voltage.
RC 119 I, SCHE
RC Input for Power On reset. Reset input pin.
XI 120 I, Analog 25M Crystal Input. 25M Crystal Input. Variation is limited to
+/- 50ppm.
XO 121 O, Analog 25M Crystal Output. When connected to oscillator, this pin
should left unconnected.
CFG0 86 I, PU Configuration of Port 4 MII Mode
CFG0 P4TYPE Description
0 00 5 Port and 1 MII interface
0 01 4 Port and 2 MII(MAC) interface
1 xx 4 Port and 1 MII(MAC) and 1 MII(PCS)
MDIO 40 I/O, 8mA PU
Management Data. MDIO transfers management data in
and out of the device synchronous to MDC.
MDC 44 I, SCHE Management Data Reference Clock. A non-continuous
clock input for management usage. ADM7001/T will use
this clock to sample data input on MDIO and drive data onto
MDIO according to rising edge of this clock.
TEST 41 I, PD TEST Value.
At normal application connect to GND.
Chapter 3 Function Description
3.1 Functional Descriptions
The ADM6996F integrates four 100Base-X physical sub-layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, four complete 10Base-T modules, 6 port 10/100 switch controller and two 10/100 MII/GPSI MAC and memory into a single chip for both 10Mbits/s, 100Mbits/s Ethernet switch operation. It also supports 100Base-FX operation through external fiber-optic transceivers. The device is capable of operating in either Full Duplex mode or Half-Duplex mode in 10Mbits/s and 100Mbits/s.
Operational modes can be selected by hardware configuration pins, software settings of management registers, or determined by the on-chip auto negotiation logic.
The ADM6996F consists of three major blocks:
? 10/100M PHY Block
? Switch Controller Block
? Built-in SSRAM
The interfaces used for communication between PHY block and switch core is MII interface.
Auto MDIX function is supported in this block. This function can be Enable/Disable by hardware pin.
3.2 10/100M PHY Block
The 100Base-X section of the device implements the following functional blocks:
? 100Base-X physical coding sub-layer (PCS)
? 100Base-X physical medium attachment (PMA)
? Twisted-pair transceiver (PMD)
? The 100Base-X and 10Base-T sections share the following functional blocks.
? Clock synthesizer module
? MII Registers
? IEEE 802.3u auto negotiation
3.3 100Base-X Module
The ADM6996F implements 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as illustrated in Figure 2. Bypass options for each of the major functional blocks within the 100Base-X PCS provides flexibility for various applications.
100Mbits/s PHY loop back is included for diagnostic purpose.
3.4 100Base-X Receiver
The 100Base-X receiver consists of functional blocks required to recover and condition the 125Mbits/s receive data stream. The ADM6996F implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125Mbits/s receive data stream may originate from the on-chip twisted-pair transceiver in
a 100Base-TX application. Alternatively, the receive data stream may be generated by an
external optical receiver as in a 100Base-FX application.
The receiver block consists of the following functional sub-blocks:
? A/D Converter
? Adaptive Equalizer and timing recovery module
? NRZI/NRZ and serial/parallel decoder
? De-scrambler
? Symbol alignment block
? Symbol Decoder
? Collision Detect Block
? Carrier sense Block
? Stream decoder block
3.4.1 A/D Converter
A high performance A/D converter with 125Mhz sampling rate converts signals received
on RXP/RXN pins to 6 bits data streams; it also possess auto-gain-control capabilities that will further improve receive performance especially under long cable or harsh detrimental signal integrity. Due to high pass characteristic on transformer, built in base-line-wander correcting circuit will cancel it out and restore its DC level.
3.4.2 Adaptive Equalizer and timing Recovery Module
All digital design is especially immune from noise environments and achieves better
correlation between production and system testing. Baud rate Adaptive Equalizer/Timing Recovery compensates line loss induced from twisted pair and tracks far end clock at
125M samples per second. Adaptive Equalizer implemented with Feed forward and
Decision Feedback techniques meet the requirement of BER less than 10-12 for
transmission on CAT5 twisted pair cable ranging from 0 to 120 meters.
3.4.3 NRZI/NRZ and Serial/Parallel Decoder
The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned
to 4B/5B code group’s boundary.