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CY7C109B-12ZXC中文资料

128K x 8 Static RAM

CY7C109B CY7C1009B

Features

?High

speed —t AA = 12 ns ?Low active power —495 mW (max.)

?Low CMOS standby power —11 mW (max.) (L Version)?2.0V Data Retention

?Automatic power-down when deselected ?TTL-compatible inputs and outputs

?Easy memory expansion with CE 1, CE 2, and OE options ?CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package

Functional Description [1]

The CY7C109B/CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE 1), an active HIGH Chip Enable (CE 2), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE 1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE 2) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 7) is then written into the location specified on the address pins (A 0through A 16).

Reading from the device is accomplished by taking Chip Enable One (CE 1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE 2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.The eight input/output pins (I/O 0 through I/O 7) are placed in a high-impedance state when the device is deselected (CE 1HIGH or CE 2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE 1 LOW, CE 2 HIGH, and WE LOW).CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package. The CY7C109B and CY7C1009B are functionally equivalent in all other respects

Note:

1.For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at https://www.wendangku.net/doc/412030729.html,.

2.NC pins are not connected on the die.

1415Logic Block Diagram Pin A 1A 2A 3A 4A 5A 6A 7A 8

COLUMN DECODER

R O W D E C O D E R

S E N S E A M P S

INPUT BUFFER

POWER DOWN

I/O 0

CE 2I/O 1

I/O 2

I/O 3ARRAY

I/O 7

I/O 6I/O 5

I/O 4A 0A 11A 13A 12A A 101A A 16

A 912345678910111419202423222125282726Top View

SOJ 121329323130161517

18GND

A 16A 14A 12

A 7A 6A 5

A 4A 3WE V CC A 15A 13A 8A 9I/O 7I/O 6I/O 5I/O 4A 2NC I/O 0I/O 1I/O 2CE 1A 10I/O 3

A 1

A 0

A 11CE 2A 6A 7A 16A 14A 12WE V CC A 4

A 13A 8A 9OE TSOP I Top View (not to scale)

16234573227313029282621252423221920I/O 2I/O 1GND I/O 7I/O 4I/O 5I/O 6I/O 0CE A 11A 517

188910111213141516

CE 2A 15NC A 10I/O 3A 1A 0A 3

A 2Configurations [2]

128K x 8

CY7C109B CY7C1009B

Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature .................................–65°C to +150°C Ambient Temperature with

Power Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND[3]....–0.5V to +7.0V DC Voltage Applied to Outputs

in High Z State[3]....................................–0.5V to V CC + 0.5V DC Input Voltage[3].................................–0.5V to V CC + 0.5V Current into Outputs (LOW).........................................20 mA Static Discharge Voltage.. (2001)

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Selection Guide

7C109B-12 7C1009B-12

7C109B-15

7C1009B-15

7C109B-20

7C1009B-20Unit

Maximum Access Time121520ns Maximum Operating Current908075mA Maximum CMOS Standby Current101010mA Maximum CMOS Standby Current (L)2mA

Operating Range

Range

Ambient

Temperature V CC

Commercial0°C to +70°C 5V ± 10%

Industrial?40°C to +85°C5V ± 10% Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

7C109B-12

7C1009B-12

7C109B-15

7C1009B-15

7C109B-20

7C1009B-20

Unit Min.Max.Min.Max.Min.Max.

V OH Output HIGH Voltage V CC = Min., I OH = –4.0 mA 2.4 2.4 2.4V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA0.40.40.4V V IH Input HIGH Voltage 2.2V CC + 0.3 2.2V CC + 0.3 2.2V CC + 0.3V V IL Input LOW Voltage[3]–0.30.8–0.30.8–0.30.8V I IX Input Leakage

Current

GND < V I < V CC–1+1–1+1–1+1μA

I OZ Output Leakage

Current GND < V I < V CC,

Output Disabled

–5+5–5+5–5+5μA

I CC V CC Operating

Supply Current V CC = Max.,I OUT = 0 mA,

f = f MAX = 1/t RC

908075mA

I SB1Automatic CE

Power-Down Current

—TTL Inputs Max. V CC, CE1 > V IH

or CE2 < V IL,V IN > V IH or

V IN < V IL, f = f MAX

454030mA

I SB2Automatic CE

Power-Down Current

—CMOS Inputs Max. V CC,

CE1 > V CC – 0.3V,

or CE2 < 0.3V,

V IN > V CC – 0.3V,

or V IN < 0.3V, f = 0

101010mA

L2mA

Capacitance[4]

Parameter Description Test Conditions Max.Unit

C IN Input Capacitance T A = 25°C, f = 1 MHz,

V CC = 5.0V 9pF

C OUT Output Capacitance8pF Notes:

3.Minimum voltage is–2.0V for pulse durations of less than 20 ns.

4.Tested initially and after any design or process changes that may affect these parameters.

CY7C109B CY7C1009B

AC Test Loads and Waveforms

90%10%3.0V

GND

90%10%

ALL INPUT PULSES 5V OUTPUT

30 pF

INCLUDING JIG AND SCOPE 5V OUTPUT

5 pF

INCLUDING JIG AND SCOPE (a)

(b)

≤ 3 ns ≤3ns

OUTPUT

R1 480?

R1480?

255?

167?

Equivalent to:VENIN EQUIVALENT

1.73V THé Switching Characteristics [5]

Parameter Description

7C109B-12

7C1009B-12

7C109B-157C1009B-157C109B-207C1009B-20Unit

Min.

Max.

Min.

Max.

Min.

Max.

Read Cycle t RC Read Cycle Time 12

ns t AA Address to Data Valid

ns t OHA Data Hold from Address Change

ns t ACE CE 1 LOW to Data Valid, CE 2 HIGH to Data Valid 121520ns t DOE OE LOW to Data Valid 6

ns t LZOE OE LOW to Low Z 0

ns t HZOE OE HIGH to High Z [6, 7]

ns t LZCE CE 1 LOW to Low Z, CE 2 HIGH to Low Z [7]3

ns t HZCE CE 1 HIGH to High Z, CE 2 LOW to High Z [6, 7]6

ns t PU CE 1 LOW to Power-Up, CE 2 HIGH to Power-Up 0

ns t PD CE 1 HIGH to Power-Down, CE 2 LOW to Power-Down 12

ns Write Cycle [8]

t WC Write Cycle Time [9]

121520ns t SCE CE 1 LOW to Write End, CE 2 HIGH to Write End 101215ns t AW Address Set-Up to Write End 101215ns t HA Address Hold from Write End 000ns t SA Address Set-Up to Write Start 000ns t PWE WE Pulse Width

101212ns t SD Data Set-Up to Write End 7810ns t HD Data Hold from Write End 000ns t LZWE WE HIGH to Low Z [7]3

ns t HZWE

WE LOW to High Z [6, 7]

Notes:

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance.

6.t HZOE , t HZCE , and t HZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

7.At any given temperature and voltage condition, t HZCE is less than t LZCE , t HZOE is less than t LZOE , and t HZWE is less than t LZWE for any given device.

8.The internal write time of the memory is defined by the overlap of CE 1 LOW, CE 2 HIGH, and WE LOW. CE 1 and WE must be LOW and CE 2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

9.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD .

CY7C109B CY7C1009B

Data Retention Characteristics Over the Operating Range (Low Power version only )

Parameter Description

Conditions

Min.Max.

Unit V DR V CC for Data Retention No input may exceed V CC + 0.5V V CC = V DR = 2.0V,

CE 1 > V CC – 0.3V or CE 2 < 0.3V, V IN > V CC – 0.3V or V IN < 0.3V

2.0

V I CCDR Data Retention Current

150

μA t CDR Chip Deselect to Data Retention Time 0ns t R

Operation Recovery Time

200

μs

Data Retention Waveform

Switching Waveforms

Read Cycle No. 1[10, 11]

Read Cycle No. 2 (OE Controlled)[11, 12]

Notes:

10.Device is continuously selected. OE, CE 1 = V IL , CE 2 = V IH .11.12.1 transition LOW and CE 2 transition HIGH.

4.5V 4.5V CE

V CC

t CDR

V DR >2V

DATA RETENTION MODE

t R

PREVIOUS DATA VALID

DATA VALID

t RC

t AA

t OHA

ADDRESS

DATA OUT

50%

DATA VALID

t RC

t ACE

t DOE

t LZOE

t LZCE t PU

HIGH IMPEDANCE

t HZOE

t HZCE

t PD

HIGH OE

CE 1I CC I SB

IMPEDANCE

ADDRESS

CE 2

DATA OUT V CC SUPPLY CURRENT

CY7C109B CY7C1009B

Write Cycle No. 1 (CE 1 or CE 2 Controlled)[13, 14]

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]

Notes:

13.Data I/O is high impedance if OE = V IH .

14.If CE 1 goes HIGH or CE 2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.15.During this period the I/Os are in the output state and input signals should not be applied.

Switching Waveforms (continued)

t WC

DATA VALID

t AW

t SA

t PWE

t HA

t HD

t SD

t SCE

CE 1ADDRESS

CE 2

DATA I/O

t HD

t SD

t PWE

t SA

t HA

t AW

t SCE t SCE

t WC

t HZOE

DATA IN VALID

CE 1ADDRESS

CE 2

DATA I/O

NOTE 15

CY7C109B CY7C1009B

Write Cycle No. 3 (WE Controlled, OE LOW)[14]

Truth Table

CE 1CE 2OE WE I/O 0–I/O 7

Mode

Power

H X X X High Z Power-Down Standby (I SB )X L X X High Z Power-Down Standby (I SB )L H L H Data Out Read Active (I CC )L H X L Data In Write

Active (I CC )L

High Z

Selected, Outputs Disabled

Active (I CC )

Switching Waveforms (continued)

DATA VALID

t HD

t SD

t LZWE

t PWE

t SA

t HA

t AW

t SCE t SCE

t WC

t HZWE

CE 1ADDRESS

CE 2

DATA I/O

NOTE 15

CY7C109B

CY7C1009B Ordering Information

Speed

(ns)Ordering Code Package

Diagram Package Type

Operating

Range

12CY7C109B-12VC51-8503332-pin (400-Mil) Molded SOJ Commercial CY7C1009B-12VC51-8504132-pin (300-Mil) Molded SOJ

CY7C109B-12ZC51-8505632-pin TSOP Type I

CY7C109B-12ZXC32-pin TSOP Type I (Pb-Free)

15CY7C109BL-15VC51-8503332-pin (400-Mil) Molded SOJ Commercial CY7C109B-15VC32-pin (400-Mil) Molded SOJ

CY7C109B-15VXC32-pin (400-Mil) Molded SOJ (Pb-Free)

CY7C1009B-15VC51-8504132-pin (300-Mil) Molded SOJ

CY7C1009B-15VXC32-pin (300-Mil) Molded SOJ (Pb-Free)

CY7C109B-15ZC51-8505632-pin TSOP Type I

CY7C109B-15ZXC32-pin TSOP Type I (Pb-Free)

CY7C109B-15VI51-8503332-pin (400-Mil) Molded SOJ Industrial

CY7C1009B-15VI51-8504132-pin (300-Mil) Molded SOJ

20CY7C109B-20ZC51-8505632-pin TSOP Type I Commercial CY7C1009B-20VC51-8504132-pin (300-Mil) Molded SOJ

CY7C109B-20VI51-8503332-pin (400-Mil) Molded SOJ Industrial Please contact local sales representative regarding availability of parts

Package Diagrams

32-pin (300-Mil) Molded (51-85041)

51-85041-*A

CY7C109B

CY7C1009B Package Diagrams (continued)

32-pin(400-Mil)Molded SOJ (51-85033)

51-85033-*B

CY7C109B CY7C1009B

Document #: 38-05038 Rev. *C Page 9 of 10

All product and company names mentioned in this document may be the trademarks of their respective holders

Package Diagrams (continued)

51-85056-*D

32-pin TSOP Type I (8 x 20 mm) (51-85056)

CY7C109B

CY7C1009B Document History Page

Document Title: CY7C109B/CY7C1009B 128K x 8 Static RAM

Document Number: 38-05038

REV.ECN NO.Issue

Date

Orig. of

Change Description of Change

**10683209/22/01SZV Change from Spec number: 38-00971 to 38-05038

*A11646709/16/02CEA Added applications foot note to data sheet, page 1

*B397875See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Updated the Ordering Information Table on page 7

*C493543See ECN NXR Removed 25 ns and 35 ns speed bin from product offering

Added note# 2 on page# 1

Changed the description of I IX from Input Load Current to

Input Leakage Current in DC Electrical Characteristics table

Removed I OS parameter from DC Electrical Characteristics table

Updated the Ordering Information Table