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6548_SAMSUNG_DS_K6X8008TBN

K6X8008T2B Family CMOS SRAM Document Title

1Mx8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No.

0.0

0.1

1.0

Remark

Preliminary

Final History

Initial draft

Revised

- Deleted 44-TSOP2-400R package type.

Finalized

- Changed I CC2 from 40mA to 30mA

- Changed I SB1(industrial)from 30μA to 15μA

- Changed I SB1(Automotive)from 40μA to 25μA

Draft Date

October 31, 2002

December 11, 2002

September 16, 2003

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.

K6X8008T2B Family

CMOS SRAM

1Mx8 bit Low Power and Low Voltage full CMOS Static RAM

GENERAL DESCRIPTION

The K6X8008T2B families are fabricated by SAMSUNG ′s advanced full CMOS process technology. The families sup-port various operating temperature range for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current.

FEATURES

? Process Technology: Full CMOS ? Organization: 1M x8

? Power Supply Voltage: 2.7~3.6V

? Low Data Retention Voltage: 1.5V(Min)? Three state outputs

? Package Type: 44-TSOP2-400F

Name Function Name Function CS 1, CS 2

Chip Select Inputs Vcc Power OE Output Enable Input Vss

Ground

WE Write Enable Input A 0~A 19Address Inputs I/O 1~I/O 8

Data Inputs/Outputs

No Connect

PRO DUCT FAMILY

1. This parameter is measured with 50pF test load (Vcc=3.0~3.6V).

Product Family Operating Temperature Vcc Range

Speed Power Dissipation

PKG Type

Standby (I SB1, Max)Operating (I CC2, Max)K6X8008T2B-F Industrial(-40~85°C) 2.7~3.6V 551)/70ns 15μA 30mA

44-TSOP2-400F

K6X8008T2B-Q

Automotive(-40~125°C)

70ns

25μA

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

Row select

I/O 1~I/O 8

Data cont Data cont

Vcc Vss

Precharge circuit.

Memory array 1024 rows

1024×8 columns

I/O Circuit Column select

PIN DESCRIPTION

OE CS1Control Logic

CS2Row

Addresses

Column Addresses

A4A3A2A1A0CS1NC NC I/O1I/O2Vcc Vss I/O3I/O4NC NC WE A19A18A17A16A5A6A7OE CS2A8NC NC I/O8I/O7Vss Vcc I/O6I/O5NC NC A9A10A11A1244-TSOP2Forward

44434241403938373635343332313029282726252423

12345678910111213141516171819202122

A15

A14

A13

K6X8008T2B Family

CMOS SRAM

PRODUCT LIST

1. Operating voltage range is 3.0~3.6V

Industrial Temperature Products(-40~85°C)Automotive Temperature Products(-40~125°C)Part Name Function

Part Name Function

K6X8008T2B-TF551)K6X8008T2B-TF70

44-TSOP2-F, 55ns, LL 44-TSOP2-F, 70ns, LL

K6X8008T2B-TQ70

44-TSOP2-F, 70ns, L

ABSOLUTE MAXIMUM RATINGS 1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item

Symbol Ratings

Unit Remark

Voltage on any pin relative to Vss V IN , V OUT

-0.2 to V CC +0.3 (max. 3.9V)

V -Voltage on Vcc supply relative to Vss V CC -0.2 to 3.9

V -Power Dissipation P D 1.0W -Storage temperature T STG -65 to 150°C -Operating Temperature

T A

-40 to 85°C K6X8008T2B-F -40 to 125

°C

K6X8008T2B-Q

FUNCTIONAL DESCRIPTION

Note: X means don ′t care. (Must be low or high state)

CS 1CS 2OE WE I/O 1~8Mode Power H X X X High-Z Deselected Standby X L X X High-Z Deselected Standby L H H H High-Z Output Disabled

Active L H L H Dout Read Active L

Din

Write

Active

K6X8008T2B Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS 1)

Note:

1. Industrial Product: T A =-40 to 85°C, otherwise specified. Automotive Product: T A =-40 to 125°C, otherwise specified.

2. Overshoot: V CC +

3.0V in case of pulse width ≤30ns.3. Undershoot: -3.0V in case of pulse width ≤30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

Item

Symbol Product Min Typ Max Unit Supply voltage Vcc K6X8008T2B Family

2.7

3.0/3.3 3.6V Ground

Vss All Family 000V Input high voltage V IH K6X8008T2B Family 2.2-Vcc+0.32)

V Input low voltage

V IL

K6X8008T2B Family

-0.33)

-0.6

CAPACITANCE 1) (f=1MHz, T A =25°C)

1. Capacitance is sampled, not 100% tested.

Item

Symbol Test Condition

Min Max Unit Input capacitance C IN V IN =0V -8pF Input/Output capacitance

C IO

V IO =0V

DC AND OPERATING CHARACTERISTICS

Item

Symbol Test Conditions

Min Typ Max Unit Input leakage current I LI V IN =Vss to Vcc

-1-1μA Output leakage current

I LO CS 1=V IH, CS 2=V IL or OE=V IH or WE=V IL , V IO =Vss to Vcc -1-1μA Average operating current

I CC1

Cycle time=1μs, 100%duty, I IO =0mA, CS 1≤0.2V, CS 2≥Vcc-0.2V, V IN ≤0.2V or V IN ≥Vcc-0.2V

--3mA I CC2

Cycle time=Min, I IO =0mA, 100% duty, CS 1=V IL , CS 2=V IH, V IN =V IL or V IH --30mA Output low voltage V OL I OL = 2.1mA --0.4V Output high voltage V OH I OH = -1.0mA

2.4--V Standby Current(TTL)I SB CS 1=V IH , CS 2=V IL , Other inputs=V IH or V IL

--0.4mA

Standby Current(CMOS)

I SB1

Other input =0~Vcc,

1) CS 1≥Vcc-0.2V, CS 2≥Vcc-0.2V (CS 1 controlled) or

2) 0V ≤CS 2≤0.2V(CS 2 controlled)

K6X8008T2B-F --15μA K6X8008T2B-Q --25

K6X8008T2B Family

CMOS SRAM

C L 1)

1.Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns

Input and output reference voltage: 1.5V Output load(see right): C L =100pF+1TTL

C L =50pF+1TTL

DATA RETENTION CHARACTERISTICS

1. CS 1≥Vcc-0.2V,CS 2≥Vcc-0.2V(CS 1 controlled) or CS 2≥Vcc-0.2V(CS 2 controlled).

Item

Symbol Test Condition

Min Typ Max Unit Vcc for data retention V DR CS 1≥Vcc-0.2V 1)

1.5- 3.6V Data retention current I DR Vcc=1.5V, CS 1≥Vcc-0.2V 1)K6X8008T2B-F --6μA K6X8008T2B-Q

10Data retention set-up time t SDR See data retention waveform

0--ms

Recovery time

t RDR

--AC CHARACTERISTICS (V CC =2.7~3.6V, Industrial product: T A =-40 to 85°C, Automotive product: T A =-40 to 125°C)

1. Voltage range is 3.0V~3.6V for industrial product.

Parameter List

Symbol

Speed Bins

Units

55ns 1)

70ns

Min

Max Min Max Read

Read Cycle Time t RC 55-70-ns Address Access Time t AA -55-70ns Chip Select to Output t CO -55-70ns Output Enable to Valid Output

t OE -25-35ns Chip Select to Low-Z Output t LZ 10-10-ns Output Enable to Low-Z Output t OLZ 5-5-ns Chip Disable to High-Z Output t HZ 020025ns Output Disable to High-Z Output t OHZ 020025ns Output Hold from Address Change t OH 10-10-ns Write

Write Cycle Time

t WC 55-70-ns Chip Select to End of Write t CW 45-60-ns Address Set-up Time t AS 0-0-ns Address Valid to End of Write

t AW 45-60-ns Write Pulse Width t WP 40-50-ns Write Recovery Time t WR 0-0-ns Write to Output High-Z t WHZ 020020ns Data to Write Time Overlap t DW 25-30-ns Data Hold from Write Time t DH 0-0-ns End Write to Output Low-Z

t OW

-5

K6X8008T2B Family

CMOS SRAM

Address

Data Out

Previous Data Valid

Data Valid

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS 1=OE=V IL , CS 2=WE=V IH )

t AA

t RC

t OH

TIMING WAVEFORM OF READ CYCLE(2) (WE=V IH )

Data Valid

High-Z

CS 1

Address

Data ou t

NOTES (READ CYCLE)

1. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection.

CS 2

t OH

t AA t OLZ

t LZ

t OHZ

t HZ(1,2)

t RC

t CO2

t OE

t CO1

K6X8008T2B Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(2) (CS 1 Controlled)

Address

CS 1

Data in

Data out High-Z

High-Z

CS 2

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS 1

t CW(2)

t WR(4)

CS 2

t CW(2)

t WP(1)

t DW

t DH t OW t WHZ

Data Undefined

Data Valid

Data in

Data out

t WC

t AW

t AS(3)

K6X8008T2B Family

CMOS SRAM

DATA RETENTION WAVE FORM

CS 1 controlled

V CC 2.7V

2.2V V DR

CS 1GND

TIMING WAVEFORM OF WRITE CYCLE(3) (CS 2 Controlled)

Address

CS 1

t AW

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS 1, a high CS 2 and a low WE. A write begins at the latest transition among CS 1 goes low,CS 2 going high and WE going low : A write end at the earliest transition among CS 1 going high, CS 2 going low and WE going high,t WP is measured from the begining of write to the end of write.

2. t CW is measured from the CS 1 going low or CS 2 going high to the end of write.

3. t AS is measured from the address valid to the beginning of write.

4. t WR is measured from the end of write to the address change. t WR applied in case a write ends as CS 1 or WE going high t WR2 applied in case a write ends as CS 2 going to low.

CS 2

t CW(2)

Data in

Data Valid

Data out

High-Z High-Z

t CW(2)

t WR(4)

t WP(1)

t DW

t DH

t AS(3)

t WC

CS 2 controlled

V CC 2.7V 0.4V V DR CS 2

GND

K6X8008T2B Family

CMOS SRAM

Unit: millimeters(inches)

PACKAGE DIMENSIONS

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

#1 #22

#44#23

11.76±0.20 0.463±0.008

1.00±0.10

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