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WM8522中文资料

WM8522

24-bit, 192kHz 6-Channel DAC with 1.7Vrms Line Driver

WOLFSON MICROELECTRONICS plc

Pre Production, May 2006, 3.1

DESCRIPTION

The WM8522 is a multi-channel audio

DAC ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment.

Three stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported.

Each DAC channel has independent digital volume and mute control, and provides 1.7Vrms line drive capability from a 5V supply. This makes the device ideal for cost-sensitive consumer applications requiring high line drive audio outputs

The audio data interface supports I 2S, left justified, right justified and DSP digital audio formats

The device is controlled via a 3 wire serial interface or directly using the hardware interface. These interfaces provide access to features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is available in a 28-lead SSOP.

FEATURES

? 6-Channel DAC with 1.7Vrms line driver from 5V analogue supply

Audio performance ? SNR 102dB (‘A’ weighted @ 48kHz) ? THD -85dB (48kHz)

? DAC sampling frequency: 8kHz – 192kHz ? 3-Wire SPI serial or hardware control interface ?

Programmable audio data interface modes

? I 2S, left, right justified or DSP ? 16/20/24/32 bit word lengths

? Three independent stereo DAC outputs with independent digital volume controls

? Master or slave audio data interface

? 4.5V to 5.5V analogue, 2.7V to 3.6V digital supply operation

? Pin compatible with WM8766 ?

28-lead SSOP package

APPLICATIONS

? DVD Players

? Surround Sound AV Processors and Hi-Fi systems ?

Automotive Audio

BLOCK DIAGRAM

WM8522Pre-Production

TABLE OF CONTENTS DESCRIPTION (1)

FEATURES (1)

APPLICATIONS (1)

BLOCK DIAGRAM (1)

TABLE OF CONTENTS (2)

PIN CONFIGURATION 28 LEAD SSOP (3)

ORDERING INFORMATION (3)

PIN DESCRIPTION – 28 LEAD SSOP (4)

ABSOLUTE MAXIMUM RATINGS (5)

RECOMMENDED OPERATING CONDITIONS (6)

ELECTRICAL CHARACTERISTICS (6)

TERMINOLOGY (7)

MASTER CLOCK TIMING (7)

DIGITAL AUDIO INTERFACE – MASTER MODE (8)

DIGITAL AUDIO INTERFACE – SLAVE MODE (9)

MPU INTERFACE TIMING (10)

INTERNAL POWER ON RESET CIRCUIT (11)

DEVICE DESCRIPTION (12)

INTRODUCTION (12)

AUDIO DATA SAMPLING RATES (12)

HARDWARE CONTROL MODES (13)

DIGITAL AUDIO INTERFACE (15)

POWERDOWN MODES (18)

SOFTWARE CONTROL INTERFACE OPERATION (19)

CONTROL INTERFACE REGISTERS (19)

DIGITAL FILTER CHARACTERISTICS (34)

DAC FILTER RESPONSES (34)

DIGITAL DE-EMPHASIS CHARACTERISTICS (35)

APPLICATIONS INFORMATION (36)

RECOMMENDED EXTERNAL COMPONENTS (36)

SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS (37)

PACKAGE DIMENSIONS (38)

IMPORTANT NOTICE (39)

ADDRESS: (39)

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PIN CONFIGURATION 28 LEAD SSOP

ORDERING INFORMATION

DEVICE TEMPERATURE

RANGE PACKAGE MOISTURE

SENSITIVITY LEVEL

PEAK SOLDERING TEMPERATURE

WM8522GEDS/V -25 to +85o C 28-lead SSOP (Pb-free) MSL3 260°C WM8522GEDS/RV -25 to +85o C

28-lead SSOP (Pb-free, tape and reel)

MSL3

260°C

Note:

Reel quantity = 2,000

WM8522Pre-Production PIN DESCRIPTION – 28 LEAD SSOP

PIN NAME TYPE DESCRIPTION

1 MODE Digital input Control format selection

0 = Software control

1 = Hardware control

2 MCLK Digital input Master clock; 128, 192, 256, 384, 512 or 768fs (fs = word clock frequency)

3 BCLK Digital input/output Audio interface bit clock

4 LRCLK Digital input/output Audio left/right word clock

5 DVDD Supply Digital positive supply

6 DGND Supply Digital negative supply

7 DIN1 Digital input DAC channel 1 data input

8 DIN2 Digital input DAC channel 2 data input

9 DIN3 Digital input DAC channel 3 data input

10 DNC Do not connect Do not connect

11 CSB/I2S Digital input Software Mode: Serial interface Latch signal

Hardware Mode: Input Audio Data Format

12 SCLK/IWL Digital input Software Mode: Serial control interface clock

Hardware Mode: Audio data input word length

13 SDIN/DM Digital input Software Mode: Serial interface data

Hardware Mode: De-emphasis selection

14 MUTE Digital input/output DAC Zero Flag output or DAC mute input

15 TESTREF Analogue output Test reference

16 VREFN Supply DAC negative supply

17 VREFP Supply DAC positive reference supply

18 VMID Analogue output Midrail divider decoupling pin; 10uF external decoupling

19 NC No connect No internal connection

20 NC No connect No internal connection

21 VOUT1L Analogue output DAC channel 1 left output

22 VOUT1R Analogue output DAC channel 1 right output

23 VOUT2L Analogue output DAC channel 2 left output

24 VOUT2R Analogue output DAC channel 2 right output

25 VOUT3L Analogue output DAC channel 3 left output

26 VOUT3R Analogue output DAC channel 3 right output

27 AGND Supply Analogue negative supply and substrate connection

28 AVDD Supply Analogue positive supply

Note: Digital input pins have Schmitt trigger input buffers.

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ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Digital supply voltage -0.3V +5V Analogue supply voltage -0.3V +7V Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND -0.3V

AVDD +0.3V Master Clock Frequency 38.462MHz Operating temperature range, T A -25°C +85°C Storage temperature after soldering -65°C

+150°C

Notes: 1. Analogue and digital grounds must always be within 0.3V of each other for normal operation of the device.

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RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS

MIN TYP MAX UNIT Digital supply range DVDD 2.7 3.6 V Analogue supply range AVDD, VREFP 4.5 5.5 V Ground

AGND, VREFN, DGND

0 V Difference DGND to AGND

-0.3

+0.3

Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device.

ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, T A = +25o C, fs = 48kHz, MCLK = 256fs. PARAMETER SYMBOL

TEST CONDITIONS

MIN TYP MAX UNIT Digital Logic Levels (CMOS Levels)

Input LOW level V IL 0.3 x DVDD

V Input HIGH level V IH 0.7 x DVDD

V Output LOW V OL I OL =1mA 0.1 x DVDD

V Output HIGH

V OH

I OH = -1mA

0.9 x DVDD

Analogue Reference Levels Reference Voltage

V VMID

VREFP/2

V Potential Divider Resistance

R VMID

(VREFP to VMID) and (VMID to VREFN)

k ?

DAC Performance (Load = 10k ?, 50pF) 0dBFs Full Scale Output Voltage

1.6 x VREFP/5

1.7 x VREFP/5 1.8 x VREFP/5

Vrms SNR (Note 1,2,4) A-weighted, @ fs = 48kHz 95 102 dB SNR (Note 1,2,4) A-weighted @ fs = 96kHz 101 dB SNR (Note 1,2,4) A-weighted @ fs = 192kHz 101 dB SNR (Note 1,2,4)

A-weighted

@ fs = 48kHz, AVDD =

3.3V

101

SNR (Note 1,2,4) A-weighted

@ fs = 96kHz, AVDD =

3.3V

99 dB

Dynamic Range (Note 2,4) DNR A-weighted, -60dB full

scale input

95 102 dB Total Harmonic Distortion (THD) 1kHz, 0dBFs -85 -78 dB Mute Attenuation

1kHz Input, 0dB gain

100 dB DAC Channel Separation

100 dB 1kHz 100mVpp 50 dB Power Supply Rejection Ratio

PSRR

20Hz to 20kHz 100mVp-p

Supply Current Analogue Supply Current AVDD, VREFP = 5V

12 mA Digital Supply Current

DVDD = 3.3V

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Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’

weighted.

All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.

Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).

5. Channel Separation (dB) - Also known as crosstalk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.

Pass-Band Ripple - Any variation of the frequency response in the pass-band region.

MASTER CLOCK TIMING

Figure 1 DAC Master Clock Timing Requirements

Test Conditions

AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, T A = +25o C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER

SYMBOL TEST CONDITIONS

MIN TYP MAX UNIT System Clock Timing Information

MCLK System clock pulse width high

t MCLKH 11 ns MCLK System clock pulse width low

t MCLKL 11 ns MCLK System clock cycle time t MCLKY

26 1000 ns MCLK Duty cycle

40:60 60:40 Power-saving mode activated After MCLK stopped 2 10 μs Normal mode resumed

After MCLK re-started

0.5

MCLK cycle

Table 1 Master Clock Timing Requirements Note:

If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically powered up, but a write to the volume update register bit is required to restore the correct volume settings.

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DIGITAL AUDIO INTERFACE – MASTER MODE

Figure 2 Audio Interface - Master Mode

Figure 3 Digital Audio Data Timing – Master Mode

Test Conditions

AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, T A = +25o C, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge t DL 0 10 ns DIN1/2/3 setup time to BCLK rising edge t DST 10 ns DIN1/2/3 hold time from BCLK rising edge

t DHT

10 ns Table 2 Digital Audio Data Timing – Master Mode

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DIGITAL AUDIO INTERFACE – SLAVE MODE

Figure 4 Audio Interface – Slave Mode

Figure 5 Digital Audio Data Timing – Slave Mode

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T A = +25o C, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time t BCY 50 ns BCLK pulse width high t BCH 20 ns BCLK pulse width low t BCL 20 ns LRCLK set-up time to BCLK rising edge

t LRSU 10 ns LRCLK hold time from BCLK rising edge t LRH 10 ns DIN1/2/3 set-up time to BCLK rising edge t DS 10 ns DIN1/2/3 hold time from BCLK rising edge

t DH

10 ns Table 3 Digital Audio Data Timing – Slave Mode

WM8522Pre-Production MPU INTERFACE TIMING

Figure 6 SPI Compatible Control Interface Input Timing

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, T A = +25o C, fs = 48kHz, MCLK = 256fs unless otherwise stated

PARAMETER SYMBOL MIN TYP MAX UNIT SCLK/IWL rising edge to CSB/I2S rising edge t SCS60 ns SCLK/IWL pulse cycle time t SCY 80 ns SCLK/IWL pulse width low t SCL 30 ns SCLK/IWL pulse width high t SCH30 ns SDIN/DM to SCLK/IWL set-up time t DSU20 ns SCLK/IWL to SDIN/DM hold time t DHO20 ns CSB/I2S pulse width low t CSL20 ns CSB/I2S pulse width high t CSH20 ns CSB/I2S rising to SCLK/IWL rising t CSS20 ns Table 4 3-Wire SPI Compatible Control Interface Input Timing Information

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INTERNAL POWER ON RESET CIRCUIT

Figure 7 Internal Power on Reset Circuit Schematic

The WM8522 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used reset the digital logic into a default state after power up. The POR circuit is powered from DVDD and monitors DVDD. It asserts PORB low if DVDD is below a minimum threshold.

Figure 8 Typical Power-Up Sequence

Figure 8 shows a typical power-up sequence. When DVDD goes above the minimum threshold, Vpord, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When DVDD rises to Vpor_on, PORB is released high and all registers are in their default state and writes to the control interface may take place.

On power down, PORB is asserted low whenever DVDD drops below the minimum threshold Vpor_off. SYMBOL MIN TYP MAX UNIT V pord 0.3 0.5 0.8 V V por_on 1.3 1.7 2.0 V V por_off

1.3

1.7

2.0

Table 5 Typical POR Operation (typical values, not tested)

WM8522Pre-Production DEVICE DESCRIPTION

INTRODUCTION

WM8522 is a complete 6-channel DAC including digital interpolation and decimation filters and

switched capacitor multi-bit sigma delta DACs with digital volume controls on each channel and

output smoothing filters. The device is capable of driving line levels up to 1.7Vrms from a 5V

analogue supply, minimising external filter component count.

The device is implemented as 3 separate stereo DACs in a single package and controlled by a single

interface.

Each stereo DAC has its own data input DIN1/2/3. DAC word clock LRCLK, DAC bit clock BCLK and

DAC master clock MCLK are shared between them.

The Audio Interface may be configured to operate in either master or slave mode. In Slave mode,

LRCLK and BCLK are all inputs. In Master mode, LRCLK and BCLK are all outputs.

Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume

controls may be operated independently. In addition, a zero cross detect circuit is provided for each

DAC for the digital volume controls. The digital volume control detects a transition through the zero

point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values

change.

Control of internal functionality of the device is by 3-wire serial or pin programmable control interface.

The software control interface may be asynchronous to the audio data interface as control data will

be re-synchronised to the audio processing internally.

Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC.

In Slave mode selection between clock rates is automatically controlled. In master mode, the sample

rate is set by control bit DACRATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are

allowed for the DAC, provided the appropriate master clock is input.

The audio data interface supports right justified, left justified and I2S interface formats along with a

highly flexible DSP serial port interface.

AUDIO DATA SAMPLING RATES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. The external master system clock can be applied directly through the DAC MCLK input

pin(s) with no software configuration necessary.

The DAC master clock for WM8522 supports audio sampling rates from 128fs to 768fs, where fs is

the audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The

master clock is used to operate the digital filters and the noise shaping circuits.

In Slave mode the WM8522 has a master clock detection circuit that automatically determines the

relationship between the system clock frequency and the sampling rate (to within +/- 32 master

clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The WM8522

is tolerant of phase variations or jitter on the master clock. Table 6 shows the typical master clock

frequency inputs for the WM8522.

The signal processing for the WM8522 typically operates at an oversampling rate of 128fs. The

exception to this is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the

oversampling rate is 64fs.

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System Clock Frequency (MHz)

SAMPLING RATE (LRCLK) 128fs 192fs 256fs 384fs 512fs 768fs 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48kHz 6.144 9.216 12.288 18.432 24.576

36.864

96kHz 12.288 18.432 24.576

36.864

Unavailable

192kHz

24.576

36.864

Unavailable Unavailable Unavailable Unavailable

Table 6 System Clock Frequencies Versus Sampling Rate

HARDWARE CONTROL MODES

When the MODE pin is held high, the following hardware modes of operation are available.

MUTE AND AUTOMUTE OPERATION

In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite ZERO detect (IZD) has been detected.

DESCRIPTION

0 Normal Operation 1 Mute DAC channels

Floating

Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD not detected, H=IZD detected.

Table 7 Mute and Automute Control

Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards V MID with a time constant of approximately 64 input samples. When MUTE is de-asserted, the output will restart almost immediately from the current input sample.

Figure 9 Application and Release of Soft Mute

WM8522Pre-Production In hardware mode (MODE pin set high) the MUTE pin becomes a bi-directional pin. Therefore if it is

driven low the device will never softmute. If it is driven high then all channels will softmute

immediately.

However if the pin is connected to a high impedance, or left floating, then when all three internal zero

flags are raised the WM8522 will also drive a weak logic high signal on the MUTE pin (output

impedance 10kOhms) which can be used to drive an external device.

It is not possible to perform analogue mute in Hardware mode.

Figure 10 MUTE Logic in Hardware Mode

INPUT FORMAT SELECTION

In hardware mode, CSB/I2S and SCLK/IWL become input controls for selection of input data format

type and input data word length for the DAC.

CSB/I2S SCLK/IWL INPUT DATA MODE

0 0 24-bit right justified

0 1 20-bit right justified

1 0 16-bit I2S

1 1 24-bit I2S

Table 8 Input Format Selection

Note:

In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks

(LRCLK) are high for a minimum of 24 bit clocks (BCLK) and low for a minimum of 24 bit clocks. If

exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a

16 bit data mode.

DE-EMPHASIS CONTROL

In hardware mode, the SDIN/DM pin becomes an input control for selection of de-emphasis filtering

to be applied.

SDIN/DM DE-EMPHASIS

0 Off

1 On

Table 9 De-emphasis Control

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Pre-Production WM8522 DIGITAL AUDIO INTERFACE

MASTER AND SLAVE MODES

The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In

both Master and Slave modes DIN1/2/3 are always inputs to the WM8522.

In Slave mode, LRCLK and BCLK are inputs to the WM8522 DIN1/2/3 and LRCLK are sampled by

the WM8522 on the rising edge of BCLK.

By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 and LRCLK are

sampled on the falling edge of BCLK.

Figure 11 Slave Mode

In Master mode, LRCLK and BCLK are outputs from the WM8522 (Figure 12). LRCLK and BCLK are

generated by the WM8522. DIN1/2/3 are sampled by the WM8522 on the rising edge of BCLK.

By setting control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 are sampled on the

falling edge of BCLK.

Figure 12 Master Mode

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AUDIO INTERFACE FORMATS

Audio data is applied to the internal DAC filters via the Digital Audio Interface. 5 popular interface formats are supported: ? Left Justified mode ? Right Justified mode ? I2S mode ? DSP mode A ?

DSP mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported.

In left justified, right justified and I 2S modes, the digital audio interface receives DAC data on the DIN1/2/3 inputs. Audio data for each stereo channel is time multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the data words.

In left justified, right justified and I 2S modes, the minimum number of BCLKs per LRCLK period is 2 times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirements are met.

In DSP modes A or B, all 6 DAC channels are time multiplexed onto DIN1. LRCLK is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned.

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8522 on the first rising edge of BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right

samples, see Figure 13.

Figure 13 Left Justified Mode Timing Diagram

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RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8522 on the rising edge of BCLK preceding a LRCLK transition. LRCLK are high during the left samples and low during the right

samples, see Figure 14.

Figure 14 Right Justified Mode Timing Diagram

I2S MODE

In I 2S mode, the MSB of DIN1/2/3 is sampled by the WM8522 on the second rising edge of BCLK following a LRCLK transition. LRCLK are low during the left samples and high during the right

samples.

Figure 15 I 2S Mode Timing Diagram

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DSP MODE A

In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8522 on the second

rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2 and 3

data follow DAC channel 1 left data (Figure 16).

Figure 16 DSP Mode A Timing Diagram – DAC Data Input

DSP MODE B

In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8522 on the first BCLK

rising edge following a LRCLK rising edge. DAC channel 1 right and DAC channels 2 and 3 data

follow DAC channel 1 left data (Figure 17).

Figure 17 DSP Mode B Timing Diagram – DAC Data Input

In both DSP modes A and B, DACL1 is always sent first, followed immediately by DACR1 and the

data words for the other 6 channels. No BCLK edges are allowed between the data words. The word

order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right. POWERDOWN MODES

The WM8522 has powerdown control bits allowing specific parts of the WM8522 to be powered off

when not being used. The three stereo DACs each have a separate powerdown control bit,

DACPD[2:0] allowing individual stereo DACs to be powered off when not in use. Setting DACPD[2:0]

will powerdown everything except the reference VMID may be powered down by setting PDWN.

Setting PDWN will override all other powerdown control bits. It is recommended that the DACs are

powered down before setting PDWN.

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SOFTWARE CONTROL INTERFACE OPERATION

The WM8522 is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode.

The control mode is selected by the state of the MODE pin.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

SDIN/DM is used for the program data, SCLK/IWL is used to clock in the program data and CSB/I2S is used to latch the program data. SDIN/DM is sampled on the rising edge of SCLK/IWL. The 3-wire

interface protocol is shown in Figure 18.

Figure 18 3-Wire SPI Compatible Interface 1. B[15:9] are Control Address Bits 2. B[8:0] are Control Data Bits

CSB/I2S is edge sensitive – the data is latched on the rising edge of CSB/I2S.

CONTROL INTERFACE REGISTERS

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect.

BIT

LABEL DEFAULT

DESCRIPTION

0000010 DAC Channel Control

ATC

Attenuator Control Mode:

0: Right channels use right attenuations

1: Right channels use left attenuations

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DAC OUTPUT CONTROL

The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS

BIT LABEL DEFAULT DESCRIPTION PL[3:0] Left Output Right Output 0000 Mute Mute 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 (L+R)/2 Right 1100 Mute (L+R)/2 1101 Left (L+R)/2 1110 Right (L+R)/2 0000010 DAC Control

8:5

PL[3:0]

1001

1111

(L+R)/2

DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS BIT LABEL DEFAULT

DESCRIPTION

0000011 Interface Control

1:0

FMT [1:0]

Interface Format Select: 00 : Right justified mode 01: Left justified mode 10: I 2S mode

11: DSP modes A or B

In left justified, right justified or I 2

S modes, the LRP register bit controls the polarity of LRCLK. If this bit is set high, the expected polarity of LRCLK will be the opposite of that shown in Figure 13, Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between modes A and B. REGISTER ADDRESS BIT LABEL DEFAULT

DESCRIPTION

In left/right/I 2S Modes: LRCLK Polarity (normal) 0 : Normal LRCLK polarity 1: Inverted LRCLK polarity 0000011 Interface Control

LRP

In DSP Mode: 0 : DSP mode A 1: DSP mode B