KSZ8995M中文资料
General Description
The KS8995M is a highly integrated Layer-2 managed switch
with optimized BOM (Bill of Materials) cost for low port count,cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set such as tag/port-based VLAN, QoS (Quality of Service) priority, management, MIB counters, dual MII interfaces and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applica-tions.
The KS8995M contains five 10/100 transceivers with pat-ented mixed-signal low-power technology, five MAC (Media Access Control) units, a high-speed non-blocking switch fabric, a dedicated address look-up engine, and an on-chip frame buffer memory.
All PHY units support 10BaseT and 100BaseTX. In addition,two of the PHY units support 100BaseFX (Ports 4 and 5).All support documentation can be found on Micrel’s web site at https://www.wendangku.net/doc/447859437.html,.
Features
?Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard ?Shared memory based switch fabric with fully non-blocking configuration
? 1.4Gbps high-performance memory bandwidth
?10BaseT, 100BaseTX and 100BaseFX modes (FX in Ports 4 and 5)
?Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII)
?IEEE 802.1q tag-based VLAN (16 VLANs, full-range VID) for DMZ port, WAN/LAN separation or inter-VLAN switch links
?VLAN ID tag/untag options, per-port basis
?Programmable rate limiting 0Mbps to 100Mbps, ingress and egress port, rate options for high and low priority,per-port-basis
?Flow control or drop packet rate limiting (ingress port)?Integrated MIB counters for fully compliant statistics gathering, 34 MIB counters per port
Micrel, Inc. ? 1849 Fortune Drive ? San Jose, CA 95131 ? USA ? tel + 1 (408) 944-0800 ? fax + 1 (408) 944-0970 ? https://www.wendangku.net/doc/447859437.html,
Functional Diagram
Auto Auto Auto Auto Auto KS8995M
Features (continued)
?Enable/Disable option for huge frame size up to 1916 bytes per frame
?IGMP v1/v2 snooping for multicast packet filtering ?Special tagging mode to send CPU info on ingress packet’s port value
?SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configura-tion
?MAC-id based security lock option
?Control registers configurable on-the-fly (port-priority, 802.1p/d/q, AN...)
?CPU read access to MAC forwarding table entries ?802.1d Spanning Tree Protocol
?Port mirroring/monitoring/sniffing:ingress and/or egress traffic to any port or MII
?Broadcast storm protection with percent control–global and per-port basis
?Optimization for fiber-to-copper media conversion ?Full-chip hardware power-down support (register configuration not saved)
?Per-port based software power-save on PHY (idle link detection, register configuration preserved)
?QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based
?802.1p/q tag insertion or removal on a per port basis (egress)
?MDC and MDI/O interface support to access the MII PHY control registers (not all control registers)
?MII local loopback support
?On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table)
?Wire-speed reception and transmission
?Integrated look-up engine with dedicated 1K MAC addresses
?Full duplex IEEE 802.3x and half-duplex back pressure flow control
?Comprehensive LED support
?7-wire SNI support for legacy MAC interface ?Automatic MDI/MDI-X crossover for plug-and-play ?Disable Automatic MDI/MDI-X option
?Low power:
Core:1.8V
I/O:2.5V or 3.3V
?0.18μm CMOS technology
?Commercial temperature range:0°C to +70°C ?Industrial temperature range:–40°C to +85°C ?Available in 128-pin PQFP package Applications
?Broadband gateway/firewall/VPN
?Integrated DSL or cable modem multi-port router ?Wireless LAN access point plus gateway
?Home networking expansion
?Standalone 10/100 switch
?Hotel/campus/MxU gateway
?Enterprise VoIP gateway/phone
?FTTx customer premise equipment
?Managed media converter
Ordering Information
Part Number Temperature Range Package
KS8995M0°C to +70°C128-Pin PQFP
KSZ8995M0°C to +70°C128-Pin PQFP Lead Free KS8995MI–40°C to +85°C128-Pin PQFP
Revision History
Revision Date Summary of Changes
1.0011/05/01Created
1.0111/09/01Pinout Mux1/2, DVCC-IO
2.5/
3.3V, feature list, register spec 11-09
1.0212/03/01Editorial changes, added new register and MIB descriptions. Added paragraph describing TOS registers.
Imported functional descriptions. Formatting.
1.0312/12/01Incorporate changes per engineering feedback as well as updating functional descriptions and adding
new timing information.
1.0412/13/01Changed Rev. and For. Modes to PHY and MAC modes respectively. Added MIIM clarification in “MII
Management Interface” section. Reformatted section sequence. Added hex register addresses. Added
advertisement ability descriptions.
1.0512/18/01Inserted switch forwarding flow charts.
1.0612/20/01Added new KS8995M block diagram, editorial changes, register descriptions changes and cross-
references from functional descriptions to register and strap in options.
1.071/22/01Changed FXSD pins to inputs, added new descriptions to “Configuration Interfaces” section.
Edited pin descriptions.
1.083/1/02Editorial changes in “Dynamic MAC Address table and “MIB Counters.” Updated figure 2 flowchart.
Updated table 2 for MAC mode connections. Separate static MAC bit assignments for read and write.
Edited read and write examples to MAC tables and MIB counters. Changed Table 3 KS8995M signals to
“S” suffix. Changed aging description in Register 2, bit 0. Changed “Port Registers” section and listed all
port register addresses. Changed port control 11 description for bits [7:5]. Changed MIB counter
descriptions.
1.095/17/02Changed MII setting in “Pin Descriptions.” Changed pu/pd descriptions for SMRXD
2. “Register 18,”
changed pu/pd description for forced flow control. “Illegal Frames. ” Edited large packet sizes back in.
“Elecrical Characteristics,” Added in typical supply current numbers for 100 BaseTX and 10 BaseTX
operation. “Register 18,” Added in note for illegal half-duplex, force flow control. “Pin Description,” Added
extra X1 clock input description. “Elecrical Characteristics,” Updated to chip only current numbers.
Added SPI Timing. Feature Highlights.
1.107/29/02“Pin Description,” changed SMRXC and SMTXC to I/O. Input in MAC mode, output in PHY mode MII.
“Elecrical Characteristics,” modified current consumption to chip only numbers. “Half-Duplex Back
Pressure,” added description for no dropped packets in half-duplex mode. Added recommended
operating conditions. Added Idle mode current consumption in “Elecrical Characteristics,” added
“Selection of Isolation Transformers,” Added 3.01k? resistor instructions for ISET “Pin Description”
section. Changed Polarity of transmit pairs in “Pin Description.” Changed description for Register 2, bit 1,
in “Register Description” section. Added “Reset Timing” section.
1.1112/17/02“Register 3” changed 80
2.1x to 802.3x. “Register 6,” changed default column to disable flow control for
pull-down, and enable flow control for pull-up. “Register 29” and “Register 0” indicate loop back is at the
PHY. Added description to register 4 bit 2 to indicate that STPID packets from CPU to normal ports are
not allowed as 1522 byte tag packets. Fixed dynamic MAC address example errors in “Dynamic MAC
Address Table.” Changed definition of forced MDI, MDIX in section “Register 29,”“Register 30” and
“Register 0.” Added “Part Ordering Information.” Added Ambient operating temperature for KS8995MI 1.123/10/03Changed pin 120 description to NC. Changed SPIQ pin description to Otri. Changed logo. Changed
contact information.
Table of Contents
System Level Applications (7)
Pin Description (by Number) (9)
Pin Description (by Name) (15)
Pin Configuration (21)
Introduction (22)
Functional Overview:Physical Layer Transceiver (22)
100BaseTX Transmit (22)
100BaseTX Receive (22)
PLL Clock Synthesizer (22)
Scrambler/De-scrambler (100BaseTX only) (22)
100BaseFX Operation (22)
100BaseFX Signal Detection (22)
100BaseFX Far End Fault (23)
10BaseT Transmit (23)
10BaseT Receive (23)
Power Management (23)
MDI/MDI-X Auto Crossover (23)
Auto-Negotiation (23)
Functional Overview:Switch Core (24)
Address Look-Up (24)
Learning (24)
Migration (24)
Aging (24)
Forwarding (24)
Switching Engine (24)
MAC Operation (24)
Inter-Packet Gap (IPG) (24)
Backoff Algorithm (24)
Late Collision (26)
Illegal Frames (26)
Flow Control (26)
Half-Duplex Back Pressure (26)
Broadcast Storm Protection (26)
MII Interface Operation (26)
SNI Interface Operation (28)
Advanced Functionality (28)
Spanning Tree Support (28)
Special Tagging Mode (29)
IGMP Support (30)
Port Mirroring Support (31)
VLAN Support (31)
Rate Limit Support (32)
Configuration Interface (33)
I2C Master Serial Bus Configuration (35)
SPI Slave Serial Bus Configuration (35)
MII Management Interface (MIIM) (38)
Register Description (39)
Global Registers (39)
Register 0 (0x00): Chip ID0 (39)
Register 1 (0x01): Chip ID1/Start Switch (39)
Register 2 (0x02): Global Control 0 (40)
Register 3 (0x03): Global Control 1 (40)
Register 4 (0x04): Global Control 2 (41)
Register 5 (0x05): Global Control 3 (42)
Register 6 (0x06): Global Control 4 (42)
Register 7 (0x07): Global Control 5 (43)
Register 8 (0x08): Global Control 6 (43)
Register 9 (0x09): Global Control 7 (43)
Register 10 (0x0A): Global Control 8 (43)
Register 11 (0x0B): Global Control 9 (43)
Port Registers (44)
Register 16 (0x10):Port 1 Control 0 (44)
Register 17 (0x11):Port 1 Control 1 (44)
Register 18 (0x12):Port 1 Control 2 (45)
Register 19 (0x13):Port 1 Control 3 (46)
Register 20 (0x14):Port 1 Control 4 (46)
Register 21 (0x15):Port 1 Control 5 (46)
Register 22 (0x16):Port 1 Control 6 (46)
Register 23 (0x17):Port 1 Control 7 (46)
Register 24 (0x18):Port 1 Control 8 (47)
Register 25 (0x19):Port 1 Control 9 (47)
Register 26 (0x1A):Port 1 Control 10 (47)
Register 27 (0x1B):Port 1 Control 11 (47)
Register 28 (0x1C):Port 1 Control 12 (48)
Register 29 (0x1D):Port 1 Control 13 (49)
Register 30 (0x1E):Port 1 Status 0 (49)
Register 31 (0x1F):Port 1 Status 1 (50)
Advanced Control Registers (50)
Register 96 (0x60):TOS Priority Control Register 0 (50)
Register 97 (0x61):TOS Priority Control Register 1 (50)
Register 98 (0x62):TOS Priority Control Register 2 (50)
Register 99 (0x63):TOS Priority Control Register 3 (50)
Register 100 (0x64):TOS Priority Control Register 4 (50)
Register 101 (0x65):TOS Priority Control Register 5 (50)
Register 102 (0x66):TOS Priority Control Register 6 (50)
Register 103 (0x67):TOS Priority Control Register 7 (50)
Register 104 (0x68):MAC Address Register 0 (50)
Register 105 (0x69):MAC Address Register 1 (50)
Register 106 (0x6A):MAC Address Register 2 (50)
Register 107 (0x6B):MAC Address Register 3 (50)
Register 108 (0x6C):MAC Address Register 4 (50)
Register 109 (0X6D):MAC Address Register 5 (50)
Register 110 (0x6E):Indirect Access Control 0 (51)
Register 111 (0x6F):Indirect Access Control 1 (51)
Register 112 (0x70):Indirect Data Register 8 (51)
Register 113 (0x71):Indirect Data Register 7 (51)
Register 114 (0x72):Indirect Data Register 6 (51)
Register 115 (0x73):Indirect Data Register 5 (51)
Register 116 (0x74):Indirect Data Register 4 (51)
Register 117 (0x75):Indirect Data Register 3 (51)
Register 118 (0x76):Indirect Data Register 2 (51)
Register 119 (0x77):Indirect Data Register 1 (51)
Register 120 (0x78):Indirect Data Register 0 (51)
Register 121 (0x79):Digital Testing Status 0 (51)
Register 122 (0x7A):Digital Testing Status 1 (51)
Register 123 (0x7B):Digital Testing Control 0 (51)
Register 124 (0x7C):Digital Testing Control 1 (51)
Register 125 (0x7D):Analog Testing Control 0 (51)
Register 126 (0x7E):Analog Testing Control 1 (52)
Register 127 (0x7F):Analog Testing Status (52)
Static MAC Address (53)
VLAN Address (55)
Dynamic MAC Address (56)
MIB Counters (57)
MIIM Registers (60)
Register 0: MII Control (60)
Register 1: MII Status (61)
Register 2: PHYID HIGH (61)
Register 3: PHYID LOW (61)
Register 4: Advertisement Ability (61)
Register 5: Link Partner Ability (62)
Absolute Maximum Ratings (63)
Operating Ratings (63)
Electrical Characteristics (63)
Timing Diagrams (65)
Selection of Isolation Transformers (72)
Qualified Magnetic Lists (72)
Package Information (73)
System Level Applications
4-port LAN
1-port
WAN I/F
Figure 1.
Broadband Gateway
4-port LAN
Figure 2.Integrated Broadband Router
5-port LAN
Figure 3.Standalone Switch
Pin Description (by Number)
Pin Number Pin Name Type(1)Port Pin Function
1TEST1NC NC for normal operation. Factory test pin.
2GNDA Gnd Analog ground
3VDDAR P 1.8V analog V DD
4RXP1I1Physical receive signal + (differential)
5RXM1I1Physical receive signal - (differential)
6GNDA Gnd Analog ground
7TXM1O1Physical transmit signal - (differential)
8TXP1O1Physical transmit signal + (differential)
9VDDAT P 2.5V analog V DD
10RXP2I2Physical receive signal + (differential)
11RXM2I2Physical receive signal - (differential)
12GNDA Gnd Analog ground
13TXM2O2Physical transmit signal - (differential)
14TXP2O2Physical transmit signal + (differential)
15VDDAR P 1.8V analog V DD
16GNDA Gnd Analog ground
17ISET Set physical transmit output current. Pull-down with a 3.01k? 1%
resistor.
18VDDAT P 2.5V analog V DD
19RXP3I3Physical receive signal + (differential)
20RXM3I3Physical receive signal - (differential)
21GNDA Gnd Analog ground
22TXM3O3Physical transmit signal - (differential)
23TXP3O3Physical transmit signal + (differential)
24VDDAT P 2.5V analog V DD
25RXP4I4Physical receive signal + (differential)
26RXM4I4Physical receive signal - (differential)
27GNDA Gnd Analog ground
28TXM4O4Physical transmit signal - (differential)
29TXP4O4Physical transmit signal + (differential)
30GNDA Gnd Analog ground
31VDDAR P 1.8V analog V DD
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
32RXP5I5Physical receive signal + (differential)
33RXM5I5Physical receive signal - (differential)
34GNDA Gnd Analog ground
35TXM5O5Physical transmit signal - (differential)
36TXP5O5Physical transmit signal + (differential)
37VDDAT P 2.5V analog V DD
38FXSD5I5Fiber signal detect/factory test pin
39FXSD4I4Fiber signal detect/factory test pin
40GNDA Gnd Analog ground
41VDDAR P 1.8V analog V DD
42GNDA Gnd Analog ground
43VDDAR P 1.8V analog V DD
44GNDA Gnd Analog ground
45MUX1NC MUX1 and MUX2 should be left unconnected for normal operation.
46MUX2NC They are factory test pins.
Mode Mux1Mux2
Normal Operation NC NC
Remote Analog Loopback Mode for Testing only01
Reserved10
Power Save Mode for Testing only11 47PWRDN_N Ipu Full-chip power down. Active low.
48RESERVE NC Reserved pin. No connect.
49GNDD Gnd Digital ground
50VDDC P 1.8V digital core V DD
51PMTXEN Ipd5PHY[5] MII transmit enable
52PMTXD3Ipd5PHY[5] MII transmit bit 3
53PMTXD2Ipd5PHY[5] MII transmit bit 2
54PMTXD1Ipd5PHY[5] MII transmit bit 1
55PMTXD0Ipd5PHY[5] MII transmit bit 0
56PMTXER Ipd5PHY[5] MII transmit error
57PMTXC O5PHY[5] MII transmit clock. PHY mode MII.
58GNDD Gnd Digital ground
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
59VDDIO P 3.3/2.5V digital V DD for digital I/O circuitry
60PMRXC O5PHY[5] MII receive clock. PHY mode MII
61PMRXDV Ipd/O5PHY[5] MII receive data valid
62PMRXD3Ipd/O5PHY[5] MII receive bit 3. Strap option:PD (default) = enable flow
control; PU = disable flow control.
63PMRXD2Ipd/O5PHY[5] MII receive bit 2. Strap option:PD (default) = disable back
pressure; PU = enable back pressure.
64PMRXD1Ipd/O5PHY[5] MII receive bit 1. Strap option:PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
65PMRXD0Ipd/O5PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
66PMRXER Ipd/O5PHY[5] MII receive error. Strap option:PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
67PCRS Ipd/O5PHY[5] MII carrier sense/Force duplex mode. See “Register 76” for
port 4 only. PD (default) = Force half-duplex if auto-negotiation is
disabled or fails. PU = Force full-duplex if auto-negotiation is disabled
or fails.
68PCOL Ipd/O5PHY[5] MII collision detect/ Force flow control. See “Register 66” for
port 4 only. PD (default) = No force flow control. PU = Force flow
control.
69SMTXEN Ipd Switch MII transmit enable
70SMTXD3Ipd Switch MII transmit bit 3
71SMTXD2Ipd Switch MII transmit bit 2
72SMTXD1Ipd Switch MII transmit bit 1
73SMTXD0Ipd Switch MII transmit bit 0
74SMTXER Ipd Switch MII transmit error
75SMTXC I/O Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
76GNDD Gnd Digital ground
77VDDIO P 3.3/2.5V digital V DD for digital I/O circuitry
78SMRXC I/O Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
79SMRXDV Ipd/O Switch MII receive data valid
80SMRXD3Ipd/O Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
81SMRXD2Ipd/O Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-
duplex mode; PU = Switch MII in half-duplex mode.
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
82SMRXD1Ipd/O Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
83SMRXD0Ipd/O Switch MII receive bit 0; Strap option: LED Mode
PD (default) = Mode 0; PU = Mode 1. See “Register 11.”
Mode 0Mode 1
LEDX_2Lnk/Act100Lnk/Act
LEDX_1Fulld/Col10Lnk/Act
LEDX_0Speed Fulld 84SCOL Ipd/O Switch MII collision detect
85SCRS Ipd/O Switch MII carrier sense
86SCONF1Ipd Dual MII configuration pin
Pin# (91, 86, 87):Switch MII PHY [5] MII
000Disable, Otri Disable, Otri
001PHY Mode MII Disable, Otri
010MAC Mode MII Disable, Otri
011PHY Mode SNI Disable, Otri
100Disable Disable
101PHY Mode MII PHY Mode MII
110MAC Mode MII PHY Mode MII
111PHY Mode SNI PHY Mode MII 87SCONF0Ipd Dual MII configuration pin
88GNDD Gnd Digital ground
89VDDC P 1.8V digital core V DD
90LED5-2Ipu/O5LED indicator 2. Strap option: Aging setup. See “Aging” section
PU (default) = Aging Enable; PD = Aging disable.
91LED5-1Ipu/O5LED indicator 1. Strap option: PU (default): enable PHY MII I/F
PD:tristate all PHY MII output. See “pin# 86 SCONF1.”
92LED5-0Ipu/O5LED indicator 0
93LED4-2Ipu/O4LED indicator 2
94LED4-1Ipu/O4LED indicator 1
95LED4-0Ipu/O4LED indicator 0
96LED3-2Ipu/O3LED indicator 2
97LED3-1Ipu/O3LED indicator 1
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
98LED3-0Ipu/O3LED indicator 0
99GNDD Gnd Digital ground
100VDDIO P 3.3/2.5V digital V DD for digital I/O
101LED2-2Ipu/O2LED indicator 2
102LED2-1Ipu/O2LED indicator 1
103LED2-0Ipu/O2LED indicator 0
104LED1-2Ipu/O1LED indicator 2
105LED1-1Ipu/O1LED indicator 1
106LED1-0Ipu/O1LED indicator 0
107MDC Ipu All Switch or PHY[5] MII management data clock
108MDIO I/O All Switch or PHY[5] MII management data I/O.
Features internal pull down to define pin state when not driven.
109SPIQ Otri All(1) SPI serial data output in SPI slave mode; (2) Not used in I2C master
mode. See “pin# 113.”
110SPIC/SCL I/O All(1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at
81KHz in I2C master mode. See “pin# 113.”
111SPID/SDA I/O All(1) Serial data input in SPI slave mode; (2) Serial data input/output in
I2C master mode See “pin# 113.”
112SPIS_N Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N
is high, the KS8995M is deselected and SPIQ is held in high impedance
state, a high-to-low transition to initiate the SPI data transfer; (2) Not
used in I2C master mode.
113PS1Ipd Serial bus configuration pin
If EEPROM is not present, the KS8995M will start itself with chip
default (00)...
Pin Config.Serial Bus Configuration
PS[1:0]=00I2C Master Mode for EEPROM
PS[1:0]=01Reserved
PS[1:0]=10SPI Slave Mode for CPU Interface
PS[1:0]=11Factory Test Mode (BIST) 114PS0Ipd Serial bus configuration pin. See “pin# 113.”
115RST_N Ipu Reset the KS8995M. Active low.
116GNDD Gnd Digital ground
117VDDC P 1.8V digital core V DD
118TESTEN Ipd NC for normal operation. Factory test pin.
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
119SCANEN Ipd NC for normal operation. Factory test pin.
120NC NC No Connect
121X1I25MHz crystal clock connection/or 3.3V tolerant oscillator input.
Oscillator should be ±100ppm.
122X2O25MHz crystal clock connection
123VDDAP P 1.8V analog V DD for PLL
124GNDA Gnd Analog ground
125VDDAR P 1.8V analog V DD
126GNDA Gnd Analog ground
127GNDA Gnd Analog ground
128TEST2NC NC for normal operation. Factory test pin.
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Description (by Name)
Pin Number Pin Name Type(1)Port Pin Function
39FXSD4I4Fiber signal detect/factory test pin.
38FXSD5I5Fiber signal detect/factory test pin.
124GNDA Gnd Analog ground
42GNDA Gnd Analog ground
44GNDA Gnd Analog ground
2GNDA Gnd Analog ground
16GNDA Gnd Analog ground
30GNDA Gnd Analog ground
6GNDA Gnd Analog ground
12GNDA Gnd Analog ground
21GNDA Gnd Analog ground
27GNDA Gnd Analog ground
34GNDA Gnd Analog ground
40GNDA Gnd Analog ground
120NC NC No connect
127GNDA Gnd Analog ground
126GNDA Gnd Analog ground
49GNDD Gnd Digital ground
88GNDD Gnd Digital ground
116GNDD Gnd Digital ground
58GNDD Gnd Digital ground
76GNDD Gnd Digital ground
99GNDD Gnd Digital ground
17ISET Set physical transmit output current. Pull-down with a 3.01k? 1%
resistor.
106LED1-0Ipu/O1LED indicator 0
105LED1-1Ipu/O1LED indicator 1
104LED1-2Ipu/O1LED indicator 2
103LED2-0Ipu/O2LED indicator 0
102LED2-1Ipu/O2LED indicator 1
101LED2-2Ipu/O2LED indicator 2
98LED3-0Ipu/O3LED indicator 0
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
97LED3-1Ipu/O3LED indicator 1
96LED3-2Ipu/O3LED indicator 2
95LED4-0Ipu/O4LED indicator 0
94LED4-1Ipu/O4LED indicator 1
93LED4-2Ipu/O4LED indicator 2
92LED5-0Ipu/O5LED indicator 0
91LED5-1Ipu/O5LED indicator 1. Strap option:PU (default): enable PHY MII I/F.
PD:tristate all PHY MII output. See “pin# 86 SCONF1.”
90LED5-2Ipu/O5LED indicator 2. Strap option: Aging setup. See “Aging” section.
(default) = Aging Enable;PD = Aging disable 107MDC Ipu All Switch or PHY[5] MII management data clock.
108MDIO I/O All Switch or PHY[5] MII management data I/O.
1TEST1NC NC for normal operation. Factory test pin.
45MUX1NC MUX1 and MUX2 should be left unconnected for normal operation.
46MUX2NC They are factory test pins.
Mode Mux1Mux2
Normal Operation NC NC
Remote Analog Loopback Mode for Testing only01
Reserved10
Power Save Mode for Testing only11 68PCOL Ipd/O5PHY[5] MII collision detect/Force flow control. See “Register 18.”
For port 4 only. PD (default) = No force flow control. PU = Force flow
control.
67PCRS Ipd/O5PHY[5] MII carrier sense/Force duplex mode See “Register 28.”
For port 4 only. PD (default) = Force half-duplex if auto-negotiation is
disabled or fails. PU = Force full-duplex if auto-negotiation is disabled
or fails.
60PMRXC O5PHY[5] MII receive clock. PHY mode MII.
65PMRXD0Ipd/O5PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
64PMRXD1Ipd/O5PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
63PMRXD2Ipd/O5PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
62PMRXD3Ipd/O5PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
61PMRXDV Ipd/O5PHY[5] MII receive data valid.
66PMRXER Ipd/O5PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
57PMTXC O5PHY[5] MII transmit clock. PHY mode MII
55PMTXD0Ipd5PHY[5] MII transmit bit 0
54PMTXD1Ipd5PHY[5] MII transmit bit 1
53PMTXD2Ipd5PHY[5] MII transmit bit 2
52PMTXD3Ipd5PHY[5] MII transmit bit 3
51PMTXEN Ipd5PHY[5] MII transmit enable
56PMTXER Ipd5PHY[5] MII transmit error
114PS0Ipd Serial bus configuration pin. See “pin# 113.”
113PS1Ipd Serial bus configuration pin
If EEPROM is not present, the KS8995M will start itself with chip
default (00)...
Pin Config.Serial Bus Configuration
PS[1:0]=00I2C Master Mode for EEPROM
PS[1:0]=01Reserved
PS[1:0]=10SPI Slave Mode for CPU Interface
PS[1:0]=11Factory Test Mode (BIST) 47PWRDN_N Ipu Full-chip power down. Active low.
48RESERVE NC Reserved pin. No connect.
115RST_N Ipu Reset the KS8995M. Active low.
5RXM1I1Physical receive signal - (differential)
11RXM2I2Physical receive signal - (differential)
20RXM3I3Physical receive signal - (differential)
26RXM4I4Physical receive signal - (differential)
33RXM5I5Physical receive signal - (differential)
4RXP1I1Physical receive signal + (differential)
10RXP2I2Physical receive signal + (differential)
19RXP3I3Physical receive signal + (differential)
25RXP4I4Physical receive signal + (differential)
32RXP5I5Physical receive signal + (differential)
119SCANEN Ipd NC for normal operation. Factory test pin.
84SCOL Ipd/O Switch MII collision detect.
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
87SCONF0Ipd Dual MII configuration pin
86SCONF1Ipd Dual MII configuration pin
Pin# (91, 86, 87):Switch MII PHY [5] MII
000Disable, Otri Disable, Otri
001PHY Mode MII Disable, Otri
010MAC Mode MII Disable, Otri
011PHY Mode SNI Disable, Otri
100Disable Disable
101PHY Mode MII PHY Mode MII
110MAC Mode MII PHY Mode MII
111PHY Mode SNI PHY Mode MII 85SCRS Ipd/O Switch MII carrier sense
78SMRXC I/O Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
83SMRXD0Ipd/O Switch MII receive bit 0; Strap option: LED Mode
PD (default) = Mode 0; PU = Mode 1. See “Register 11.”
Mode 0Mode 1
LEDX_2Lnk/Act100Lnk/Act
LEDX_1Fulld/Col10Lnk/Act
LEDX_0Speed Fulld 82SMRXD1Ipd/O Switch MII receive bit 1. Strap option:PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
81SMRXD2Ipd/O Switch MII receive bit 2. Strap option:PD (default) = Switch MII in
full-duplex mode; PU = Switch MII in half-duplex mode.
80SMRXD3Ipd/O Switch MII receive bit 3. Strap option:PD (default) = Disable Switch
MII full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
79SMRXDV Ipd/O Switch MII receive data valid
75SMTXC I/O Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
73SMTXD0Ipd Switch MII transmit bit 0
72SMTXD1Ipd Switch MII transmit bit 1
71SMTXD2Ipd Switch MII transmit bit 2
70SMTXD3Ipd Switch MII transmit bit 3
69SMTXEN Ipd Switch MII transmit enable
74SMTXER Ipd Switch MII transmit error
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
110SPIC/SCL I/O All(1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at 81KHz
in I2C master mode. See “pin# 113.”
111SPID/SDA I/O All(1) Serial data input in SPI slave mode; (2) Serial data input/output in
I2C master mode. See “pin# 113.”
109SPIQ Otri All(1) SPI serial data output in SPI slave mode; (2) Not used in I2C master
mode. See “pin# 113.”
112SPIS_N Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N
is high, the KS8995M is deselected and SPIQ is held in high impedance
state, a high-to-low transition to initiate the SPI data transfer; (2) Not
used in I2C master mode.
128TEST2NC No connect for normal operation. Factory test pin.
118TESTEN Ipd No Connect for normal operation. Factory test pin.
8TXP1O1Physical transmit signal + (differential)
14TXP2O2Physical transmit signal + (differential)
23TXP3O3Physical transmit signal + (differential)
29TXP4O4Physical transmit signal + (differential)
36TXP5O5Physical transmit signal + (differential)
7TXM1O1Physical transmit signal - (differential)
13TXM2O2Physical transmit signal - (differential)
22TXM3O3Physical transmit signal - (differential)
28TXM4O4Physical transmit signal - (differential)
35TXM5O5Physical transmit signal - (differential)
123VDDAP P 1.8V analog V DD for PLL
41VDDAR P 1.8V analog V DD
43VDDAR P 1.8V analog V DD
3VDDAR P 1.8V analog V DD
15VDDAR P 1.8V analog V DD
31VDDAR P 1.8V analog V DD
125VDDAR P 1.8V analog V DD
18VDDAT P 2.5V analog V DD
9VDDAT P 2.5V analog V DD
24VDDAT P 2.5V analog V DD
37VDDAT P 2.5V analog V DD
50VDDC P 1.8V digital core V DD
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
Pin Number Pin Name Type(1)Port Pin Function
89VDDC P 1.8V digital core V DD
117VDDC P 1.8V digital core V DD
59VDDIO P 3.3/2.5V digital V DD for digital I/O circuitry
77VDDIO P 3.3/2.5V digital V DD for digital I/O circuitry
100VDDIO P 3.3/2.5V digital V DD for digital I/O circuitry
121X1I25MHz crystal clock connection/or 3.3V tolerant oscillator input.
Oscillator should be ±100ppm.
122X2O25MHz crystal clock connection.
Note:
1.P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect