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中文-NCP1605 DATASHEET

NCP1605

Enhanced, High Voltage and Efficient Standby Mode, Power Factor Controller

The NCP1605 is a controller that exhibits near?unity power factor while operating in fixed frequency, Discontinuous Conduction Mode (DCM) or in Critical Conduction Mode (CRM).

Housed in a SOIC?16 package, the circuit incorporates all the features necessary for building robust and compact PFC stages, with a minimum of external components. In addition, it integrates the skip cycle capability to lower the standby losses to a minimum.

General Features

?Near?Unity Power Factor

?Fixed Frequency, Discontinuous Conduction Mode Operation ?Critical Conduction Mode Achievable in Most Stressful Conditions ?Lossless High V oltage Current Source for Startup

?Soft Skip t Cycle for Low Power Standby Mode ?Switching Frequency up to 250 kHz ?Synchronization Capability

?Fast Line / Load Transient Compensation

?V alley Turn On

?High Drive Capability: ?500 mA / +800 mA

?Signal to Indicate that the PFC is Ready for Operation (“pfcOK” Pin)

?V CC range: from 10 V to 20 V

?Follower Boost Operation

?This is a Pb?Free Device

Safety Features

?Output Under and Overvoltage Protection

?Brown?Out Detection

?Soft?Start for Smooth Startup Operation

?Overcurrent Limitation

?Zero Current Detection Protecting the PFC stage from Inrush Currents

?Thermal Shutdown

?Latched Off Capability

Typical Applications

?PC Power Supplies

All Off Line Appliances Requiring Power Factor Correction

https://www.wendangku.net/doc/4211198249.html,

SOIC?16

D SUFFIX

CASE 751B

Device Package Shipping?

ORDERING INFORMATION

MARKING

DIAGRAM

A= Assembly Location

WL= Wafer Lot

Y= Year

WW= Work Week

= Pb?Free Package

NCP1605

AWLYWWG

(T op View)

CS in

STBY

V control

CS out/ZCD

OSC/SYNC

pfcOK/REF5V

V CC

GND

OVP/UVP

DRV

STDWN

PIN CONNECTIONS

?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specification Brochure, BRD8011/D.

NCP1605DR2G SOIC?16

(Pb?Free)

2500/T ape & Reel

增强高压启动和高效率待机的功率因数校正器

Figure 1.

MAXIMUM RATINGS

Pin Rating Symbol Value Unit 10Power Supply Input V CC?0.3, +20V 10The maximum transient voltage (Note 1)V CC?0.3, +25V 1, 2, 4, 6, 7, 8,

13 and 14

Input Voltage V I?0.3, +9V

3V CONTROL Pin V CONTROL?0.3, V CONTROL MAX

(Note 1)

V 16High Voltage Pin HV?0.3, +500V Power Dissipation and Thermal Characteristics:

Maximum Power Dissipation @ T A = 70°C Thermal Resistance Junction?to?Air

P D

R q JA

550

145

°C/W

Operating Junction T emperature Range T J?40, +125°C

Maximum Junction T emperature T Jmax150°C

Storage T emperature Range T Smax?65 to 150°°C

Lead T emperature (Soldering, 10 s)T Lmax300°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1.“V CONTROL MAX” is the pin clamp voltage

PIN FUNCTION DESCRIPTION

Pin Number

Name

Function

1STBY An external signal (typically, a portion of the feedback signal of the downstream converter or a filtered portion of the SMPS drive pulses) should be applied to Pin 1. When the Pin 3 voltage goes below 300 mV, the circuit enters a burst mode operation where the bulk voltage varies between the regulation voltage and 95.5% of this level.2Brown?Out /

Inhibition

Apply a portion of the averaged input voltage to detect brown?out conditions. If V Pin2 is lower than 0.5 V, the circuit stops pulsing until V Pin2 exceeds 1 V (0.5 V hysteresis).Ground Pin 6 to disable the part.

3V CONTROL /Soft?Start The error amplifier output is available on this Pin. The capacitor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios.

Pin 3 is grounded when the circuit is off so that when it starts operation, the power increases slowly (soft?start).

4Feedback This pin receives a portion of the pre?converter output voltage. This information is used for the

regulation and the “output low” detection (V OUT L) that drastically speed up the loop response when the output voltage drops below 95.5% of the wished level.

5Current Sense

Input This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the maximum coil current and detect the core reset (coil demagnetization).

Current Sense

Output This pin sources the Pin 5 current. Place a resistor between Pin 6 and ground to build the voltage

proportional to the coil current and detect the core reset. The impedance between Pin 6 and ground should not exceed 3 times that of the Pin 5 to ground. You can further apply the voltage from an

auxiliary winding to improve the valley detection of the MOSFET drain source voltage.7Ct

(Ramp)The circuit controls the power switch on?time by comparing the Pin 7 ramp to an internal voltage

(“V ton ”) derived from the regulation block and the sensed “dcycle” (relative duration of the current cycle over the corresponding switching period).

Pin 7 sources a current proportional to the squared output voltage to allow the Follower Boost operation

(optional) where the PFC output voltage stabilizes at a level that varies linearly versus the ac line amplitude. This technique reduces the difference between the output and input voltages, to optimize the boost efficiency and minimize the size and cost of the PFC stage

8Oscillator /synchronization Connect a capacitor or apply a synchronization signal to this pin to set the switching frequency. If the coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the core is reset. Hence, the PFC stage can operate in CRM in the most stressful conditions.9

GND

Connect this pin to the pre?converter ground.

10Drive The high current capability of the totem pole gate drive (+0.5/?0.8 A) makes it suitable to effectively drive high gate charge power MOSFET s.

V CC

This pin is the positive supply of the IC. The circuit starts to operate when V CC exceeds 15 V and turns off when V CC goes below 9 V (typical values). After startup, the operating range is 10 V up to 20 V.12PfcOK / REF5V The Pin 12 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and that hence, it can start operation.

STDWN

Apply a voltage higher than 2.5 V on Pin 13 to permanently shutdown the circuit. This pin can be used to monitor the voltage across a thermistor in order to protect the application from an excessive heating and/or to detect an overvoltage condition.

T o resume operation, it is necessary to decrease the circuit V CC below V CC RST (4 V typically) by for instance, unplugging the PFC stage and replugging it after V CC is discharged.

14OVP / UVP

The circuit turns off when V Pin14 goes below 480 mV (UVP) and disables the drive as long as the pin voltage exceeds 2.5 V (OVP).15NC Creepage distance.

Connect Pin 16 to the bulk capacitor. The internal startup current source placed between Pin 16 and the V CC terminal, charges the V CC capacitor at startup.

一个外部信号乮代表性的如后极的降压变化器的反馈信号丆或者经过过滤的后极SMPS 驱动脉冲)加在PIN1?C 当PIN1电压低于300mV,

电路进入burst 模式丆大电容电压在额定值的95.5--100%

间变动。

施加平均输入电压的部分信号丆假如VPin2低于0.5V?C 电路停止脉冲丆直到电压超过1V?i0.5V 的滞回乯。短路PIN6到地丆屏蔽该部分的功能。

此引脚为误差放大器的输出脚丆电容

连接在此脚和地之间丆调整反馈环路带宽丆通常设置低于20Hz 以达到高PF 值。

Pin3在电路关闭时短路到地丆启动时丆功率会缓慢上乮软启动乯。

此引脚接受转换器输出电压的一部分。此信号用来调节和低输出检测丆(VOUTL)。

当输出电压降低到额定值95.5%?C 环路相应迅速上升。

此引脚检测与电感电流成比例的负电压。此被检测信号限制最大电感电流和监测电感复位乮电感退磁乯。

此引脚是PIN5电流的输出。此引脚

对地放置一电阻来建立电压丆此电压

于电感电流成比例丆检测电感复位。电阻值不能超过PIN5电阻值的3倍。你可以进一步从副主绕组引入一电压丆

增强MOS 的VDS 的谷底检测。

电路控制导通时间丆靠比较PIN7的斜率和内部电压Vton 。Vton 来源于调节模块和

PIN7产生于输出电压平方成比例的电流丆允许工作在跟随模式。既输出电压相对于市电幅值变化。这种技术减小输入输出电压差丆优化boos 效率丆减小体积丆降低成本。

连接一个电容或者施加一个同步

信号丆设置开关频率丆假如电感电流周期比选择的开关周期长丆电路延迟下一个周期直到磁芯复位丆因此丆PFC 可以工作在临界模式丆在大部分受压力情况下。

PIN12电压为高电平

乮5V)当PFC 正常稳定状态丆否则为低。

这个信号通知下游的转换器丆PFC 已经就绪丆因此丆它可以开始工作。

Drv

GND

CSin OSC /NC

STDWN

Figure 51. Block Diagram

V CC

V SYNC

NCP1605 Detailed Operating Description

Introduction

The NCP1605 is a PFC driver designed to operate in fixed frequency, Discontinuous Conduction Mode (DCM). In the most stressful conditions, Critical Conduction Mode (CRM) can be achieved without power factor degradation and the circuit could be viewed as a CRM controller with a frequency clamp (given by the oscillator). Finally, the NCP1605 tends to give the best of both modes without their respective drawbacks. Furthermore, the circuit incorporates protection features for a rugged operation together with some special circuitry to lower the power consumed by the PFC stage in no load conditions. More generally, the NCP1605 functions make it the ideal candidate in systems where cost?effectiveness, reliability, low standby power and high power factor are the key parameters:?Compactness and Flexibility: the controller requires few external components while offering a large variety

of functions. Depending on the selected coil and oscillator frequency you select, the circuit can:

1.Mostly operate in CRM and use the oscillator as a

frequency clamp.

2.Mostly operate in fixed frequency mode and only

run in CRM at high load and low line.

3.Permanently operate in fixed frequency mode

DCM.

In all cases, the circuit provides near?unity power factor. Skip?cycle capability for low power standby: among other applications, the circuit targets power supply where the PFC stage must keep alive even in standby. A continuous flow of pulses is not compatible with no?load standby power requirements. Instead, the controller slices the switching pattern in bunch of pulses to drastically reduce the overall losses. The skip cycle operation is initiated by applying to Pin 1, a signal that goes below 300 mV in standby. Typically, this signal is drawn from the feedback of the downstream converter.

Startup Current Source and large V CC range: meeting low standby power specifications represents a difficult exercise when the controller requires an external, lossy resistor connected to the bulk capacitor. The controller disables the high?voltage current source after startup which no longer hampers the consumption in no?load situations. In addition, the large V CC range (10 V to 20 V after startup), highly eases the circuit biasing. Fast Line / Load Transient Compensation: given the low bandwidth of the regulation block, the output voltage of PFC stages may exhibit excessive over and undershoots because of abrupt load or input voltage variations (e.g. at startup). If the output voltage is too far from the regulation level:

?The NCP1605 disables the drive to stop

delivering power as long as the output voltage

exceeds the Overvoltage Protection (OVP) level.

?The NCP1605 drastically speeds up the

regulation loop when the output voltage is below

95.5% of its regulation level. This function is

allowed only after the PFC stage has started up

not to eliminate the soft?start effect.

PFC OK: the circuit detects when the circuit is in normal situation or if on the contrary, it is in a startup or fault condition. In the first case, Pin 12 is in high state and low otherwise. Pin 12 serves to control the downstream converter operation in response to the PFC state.

Safety Protections: the NCP1605 permanently monitors the input and output voltages, the coil current and the die temperature to protect the system from possible over?stresses and make the PFC stage extremely robust and reliable. In addition to the aforementioned OVP protection, one can list:

?Maximum Current Limit and Zero Current Detection: the circuit permanently senses the

coil current and immediately turns off the

power switch if it is higher than the set current

limit. It also prevents any turn on of the power

switch as long as some current flows through

the coil, to ensure operation in DCM. This

feature also protects the MOSFET from the

excessive stress that could result from the

large in?rush currents that occurs during the

startup phases.

?Undervoltage Protection: the circuit turns off when it detects that the output voltage goes

below 12% of the OVP level (typically). This

feature protects the PFC stage from starting

operation in case of too low ac line conditions

or in case of a failure in the OVP monitoring

network (e.g., bad connection).

?Brown?Out Detection: the circuit detects too low ac line conditions and stop operating in

this case. This protection protects the PFC

stage from the excessive stress that could

damage it in such conditions.

?Thermal Shutdown: an internal thermal

circuitry disables the circuit gate drive and then

keeps the power switch off when the junction

temperature exceeds 150°C typically. The circuit

resumes operation once the temperature drops

below about 100°C (50°C hysteresis).

Output Stage Totem Pole: the NCP1605 incorporates a ?0.5 A / +0.8 A gate driver to efficiently drive most TO220

or TO247 power MOSFETs.

介绍

NCP1605是设计工作在固定频率丆DCM模式的PFC驱动。在大部分受压力情况下丆可以工作在临界模式而不会降低PF值丆这种电路可以看做带频率钳位乮由振荡器决定乯的临界模式控制器。最后丆1605倾向于结合两种模式的有点而舍去缺点。此外丆IC为粗糙的操作集成了保护特性丆一些特殊电路降低PFC在空载时的损耗。更普遍的丆1605的功能使它成为高性价比丆高可靠性丆低待机和高功率因数等重要参数的理想候选者。

简洁和灵活性丗

控制器需要少量的

外部元器件实现大量

的多样的功能。依赖

于选择的电感和震荡

器频率。电路可以丗

1。大部分工作于

CRM?C使用作为频率签位。

2。大部分工作在固定频率

模式丆小部分工作在CRM

在重载和低压。

3。永久工作在固定频率

DCM模式。

在所有情况丆电路

提供几乎完整的功率

因数。

NCP1605

NCP1605 Operation Modes

Like the NCP1601, the NCP1605:?

Features a current sense block that prevents the PFC stage from operating in CCM: as long as the coil current is not null, the power switch is not allowed to turn on. Hence the circuit can only operate in either

Fixed Frequency DCM or CRM.

?Features the capability to exhibit near?unity power factor while operating in any type of Discontinuous Conduction Mode operation: DCM or CRM.

?Auto adapts: if there is some current flowing through

the coil when the clock occurs to initiate a new current cycle, the PFC stage enters CRM. On the other hand,if the clock occurs during dead?times, one obtains a fixed frequency operation DCM. Thanks to its special oscillator/synchronization arrangement, the circuit automatically enters the appropriate mode CRM or

DCM. It is worth noting that jumps between the CRM and modes cause absolutely no degradation: the input current keeps being properly shaped and there is no discontinuity in the power transfer.

Given the dead?time presence, DCM needs a higher peak inductor current compared to CRM for the same delivered power. Hence, the coil is generally designed to have CRM at the most stressful conditions while DCM limits the switching frequency at lower load. The circuit can also transition within an ac line cycle so that:

?CRM reduces the current stress around the sinusoid top.?DCM limits the frequency around the line zero crossing.This capability offers the best of each mode without the drawbacks. The way the circuit modulates the MOSFET on?time allows this facility.

Figure 52. DCM and CRM Operation Within a Sinusoid Cycle

The NCP1605 can jump from DCM to CRM within a sinusoid cycle (and vice versa)

without any discontinuity in the current shaping or the power transfer.

Inductor Current, I L

Current

Time

DCM

Critical Mode

DCM

Input Current, I in

NCP1605 On?time Modulation

Let’s study the ac line current absorbed by the PFC boost.The initial inductor current of each switching cycle is always zero. The coil current ramps up when the MOSFET is on . The slope is (V IN /L) where L is the coil inductance.At the end of the on?time (t1), the coil demagnetization phase starts. The coil current ramps down until this sequence ends when it reaches zero. The duration of this phase is (t2). The system enters then the dead?time (t3) that lasts until the next clock is generated.

One can show (refer to NCP1601 data sheet) that the ac line current is given by:

I in +V in

?t 1(t 1)t 2)

2T L

?(eq. 1)

Where T = (t1 + t2 + t3) is the switching period and V IN is

the ac line rectified voltage.

To the light of this equation, we immediately note that I IN is proportional to V IN if [t1(t1 + t2)/T] is a constant.

NCP1605工作模式

类似1605?C NCP1605,

>特有的电流检测

模块防止PFC 进入CCM 。直到电感电流为零丆功率开关才

导通丆因此丆电路仅工作在固定频率的

DCM 或者CRM 模式。>特有的能力实现近乎完整的功率因数丆

当工作在任何非连续模式DCM 或者CRM.

>自适应丗当时钟

信号触发丆假如有一些电流流过电感丆开始一个新的电流周期丆

PFC 进入CRM 。另一方面丆假如时钟信

号在死区时间触发丆感谢IC 的特殊的oscillator/synchronization

安排丆电路自动进入CRM 或者DCM 。

值得注意丆在CRM 和DCM 间跳动不会导致功率因数退化丆输入电流保持合适的形状丆功率一直连续传输。

给予死区时间丆DCM 需要跟高的峰值电感电流丆相对于CRM?C 对相同的传输功率。因此丆电感通常被设计在大部分CRM 而轻载工作在限定开关频率的DCM 。两种模式在一个工频周期内过渡。

CRM 减少正弦顶端附近的电流应力。

DCM 限制市电过零点附件的频率。

这可以提供两种模式的优点而避免缺点。使用这样的方式调节MOS 的导通时间。

NCP1605导通时间调制

我们学习被PFC boost 吸收市电电流。每个开关周期最初的电感电流总是零。电感电流倾斜上升当MOS 导通时。斜率是(VIN/L)?CL 是电感量。导通时间的末尾乮t1),开始电感退磁周期丆电感电流斜线下降直到这个时序的末尾当电流为零。这个持续阶段为t2。系统接着进入死区时间t3 ?C 持续直到下个周期开始。

可以说明交流市电电流由公式1给出乮参考NCP1601规格书).--------------------公式1---------------------T=t1+t2+t3是开关周期丆Vin 是交流市电整流电压。

审视这个公式丆我们马上注意到Iin 和Vin 成比例假如[t1(t1 + t2)/T]恒定。

Figure 53. PFC Boost Converter

Figure 54. Inductor Current in DCM

The NCP1605 operates in voltage mode. As portrayed by Figure 55, the MOSFET on time t 1 is controlled by the signal V ton generated by the regulation block and the Pin 4 ramp as follows:

t 1+

C pin7@V TON

I pin7

(eq. 2)

The charge current that is sourced by Pin 7

[I pin7

= 60m A/V 2 * (V Pin4)2] is constant at a given input voltage (V Pin4 is proportional to the output voltage). C pin7that is the capacitor connected between Pin 7 and ground is also a constant. Hence, the power factor correction is achieved when the V TON (t 1 + t 2)/T term is constant.The output of the regulation block (V CONTROL ) is linearly changed into a signal (V REGUL ) varying between 0 and 1V . (V REGUL ) is the voltage that is injected into the PWM section to modulate the MOSFET duty?cycle.However, like the NCP1601, the NCP1605 inserts some circuitry that processes (V REGUL ) to form the signal (V TON ) that is used in the PWM section instead of (V REGUL ) (see Figure 56). (V TON ) is modulated in response to the dead?time sensed during the precedent current cycles, that is, for a proper shaping of the ac line current (refer to NCP1601 data sheet). This modulation leads to:V TON +

T @V REGUL t 1)t 2

or :V TON @

t 1)t 2

+V REGUL

(eq. 3)

Given the regulation low bandwidth of the PFC systems,(V CONTROL ) and then (V REGUL ) are slow varying signals.Hence, the (V TON * (t 1 + t 2)/T) term is substantially constant. Provided that in addition, (t1) is proportional to (V TON ), equation (1) leads to: (I in = k * V in ), where k is a constant. More exactly:I in +k @V in

where :k +constant +

?C pin7@V REGUL

pin2?voltage. Hence, the ac line current is properly shaped.One can note that this analysis is also valid in the CRM case. This condition is just a particular case of this functioning where (t 3 = 0), which leads to (t 1 + t 2 = T) and (V TON = V REGUL ). That is why the NCP1605 automatically adapts to the conditions and jumps from DCM and CRM (and vice versa) without power factor degradation and without discontinuity in the power delivery.Remark: Like in the NCP1601, the “V TON processing circuit” is “informed” when there is an OVP condition, not to over?dimension V TON in that conditions. Otherwise, an OVP sequence would be viewed as a dead?time phase by the circuit and V TON would inappropriately increase to compensate it.Similarly, the “V TON processing circuit” is inhibited for a skip sequence not to over?dimension “V TON ” in this case (refer to Figure 56).Figure 55. PWM Circuit and Timing Diagram

Figure 56. V TON Processing Circuit

timing capacitor

PWM

OVP

The integrator OA1 amplifies the error between V REGUL and IN1 so that in average, (V TON *(t1+t2)/T) equates V REGUL .

V REGUL

V ton

Ramp Voltage PWM Outtage

Turns Off MOSFET

V ton

C ramp

I ch

PWM Comparator

Closed When Output Low

1605工作在电压模式。如图55描绘丆MOS

导通时间t1被Vton 信号控制丆Vton 由调节模块产生丆

PIN4斜率如下丗PIN7产生的充电电流乮Ipin7= )在给定的输入电压丆乮VPin4与输出电压成比例乯。

Cpin7是连接在PIN7和地的电容丆也是恒定的。因此丆

当VTON (t1 + t2)/T

恒定丆功率因数得到校正。调节模块输出VCONTROL 线性

变换成在0-1V 间变化的信号VREGUL 。

VREGUL 是注入PWM 部分的电压丆

用来调节MOS 占

空比。然而丆类似1601?C 1605插入

一些电路把

VREGUL 处理形成信号VTON 。

VTON 代替

VREGUL 使用于PWM 部分。乮参考图56?j 。考虑到PFC 系统的低带宽调节丆VCONTROL 和 VREGUL 是缓慢

变化的信号丆因此丆

VTON * (t1 + t2)/T 大致恒定丆另外如

果丆t1与(VTON)

成比例丆公式1导

出(Iin = k * Vin)?C

此处K 是恒定的丆

更精确地丆-----公式-------------

于是输入电流和输

入电压成比例。因

此丆交流电流被合适的塑形。

可以注意到丆这个分析对CRM 也有效。这是种特定情

况丆当t3=0时丆

这可以推导出t1+

t2=T

和VTON = VREGUL

这就是为什么160

5自动适应条件在DCM 和CRM 间跳

动乮反之亦然乯。

不会造成PF 值退

化丆功率传递不会间断。

评论丗类似

1601?C 当有过压情况时丆

VTON 处理线路被

通知丆这种情况下

VTON 不会过规格否则丆过压时序会

被认为是死区时间

阶段丆VTON 会不

恰当地增长补偿。

类似地丆VTON 处

理电路抑制VTON

不过规格在跳跃时序。乮参考图56?j 。

1012

20time (ms)

V i n (V )

0,00

0,501,001,502,002,503,003,50Figure 57. Input Voltage and On?time vs Time (example with F SW = 100 kHz, Pin =150 W, V AC = 230 V, L = 200 m H)

Regulation Block and Low Output Voltage Detection

A transconductance error amplifier with access to the inverting input and output is provided. It features a typical transconductance gain of 200 m S and a maximum capability of ±20 m A. The output voltage of the PFC stage is typically scaled down by a resistors divider and monitored by the inverting input (feedback pin ? Pin 4).The bias current is minimized (less than 500 nA) to allow the use of a high impedance feedback network. The output of the error amplifier is pinned out for external loop compensation (Pin 3). Typically a capacitor in the range of 100nF, is applied between Pin 3 and ground, to set the regulation bandwidth below 20 Hz, as need in PFC applications.

The swing of the error amplifier output is limited within an accurate range:

?It is forced above a voltage drop (V F ) by some circuitry.?It is clamped not to exceed 3.0 V + the same V F voltage drop.

Hence, V Pin3 features a 3 V voltage swing. V Pin3 is then offset down by (V F ) and divided by three before it connects to the “V TON processing block” and the PWM section.Finally, the output of the regulation is a signal (“V REGUL ”of the block diagram) that varies between 0 and 1 V .

Figure 58. Regulation Block

Figure 59. Correspondence between V CONTROL

and V REGUL

1 V

0 V

V F

V REGUL

V CONTROL

3 V + V F

V Provided the low bandwidth of the regulation loop, sharp variations of the load, may result in excessive over and undershoots. Overshoots are limited by the Overvoltage Protection (see OVP section). To contain the undershoots, an internal comparator monitors the feedback (V Pin4) and when V Pin4 is lower than 95.5% of its nominal value, it connects a

200 m A current source to speed?up the charge of the compensation capacitor (Cpin3). Finally, it is like if the comparator multiplied the error amplifier gain by 10.

One must note that this circuitry for undershoots limitation,is not enabled during the startup sequence of the PFC stage but only once the converter has stabilized (that is when the

调节模块和低输出电压监测

一个跨导误差放大器预留反相输入端和

输出端供使用丆拥有典型的200微秒

增益和20微安的能力。PFC 输出电压通常被电阻分压等

比例缩小丆送入反相输入端检测。

偏置电流很小乮小于500纳安乯而允许使用大阻值的

反馈网络。误差放大器输出端外接环

路补偿。乮PIN3)通常使用100nF 的电容丆连接pin3和

地。设置调节带宽低于20HZ ?C 因PFC 应用需要。

因此丆VPin3具有3V 的电压摆动丆VPin3在连接“VTON processing block ”和PWM 部分前被VF 向下偏置丆衰减3倍。最终丆调节输出信号乮框图中的VREGUL?j 在0和1间变化。

“pfcOK” signal of the block diagram, is high). This is because, at the beginning of operation, the Pin 3 capacitor must charge slowly and gradually for a soft?startup. Remark: As shown in block diagram, the circuitry for undershoots limitation is disabled as long as Pin 3 detects standby conditions (V Pin3 < 300 mV). This is to suppress the risk of audible noise in standby thanks to the soft–start that softens the bursts.

On?Time Control for Maximum Power Adjustment

As aforementioned, the NCP1605 processes the error amplifier output voltage to form a signal (V TON) that is used by the PWM section to control the on?time. (V TON) compensates the relative weight of the dead?time sequences measured during the precedent current cycles. During the conduction time of the MOSFET, Pin 7 sources a current that is proportional to the square of the voltage applied to Pin 4 (feedback pin). Practically, as Pin 4 receives a portion of the output voltage (V OUT), I Pin7 is proportional to the square of V OUT.

The MOSFET turns off when the Pin 7 voltage exceeds V TON. Hence, the MOSFET on?time (t1) is given by:

t1+C pin7V TON

k V OUT2

where k is a constant.

The coil current averaged over one switching period is:

t I COIL u T+I IN(t)+V IN t1

2L (t1)t2)

Where I IN(t) and V IN(t) are the instantaneous input current and voltage, respectively, t2 is the core reset time and T is the switching period. Hence, the instantaneous input power is given by the following equation:

P IN(t)+V IN(t)I IN(t)+

C pin7V IN2

2L k V OUT2

V TON(t1)t2)

As aforementioned, we have: V TON (t1 + t2)/T = V REGUL where V REGUL is the signal outputted by the regulation block. Hence, the average input power is:

t P IN u+

C pin7V ac2

2L k V OUT2

V REGUL

The maximum value of V REGUL being 1 V, the maximum power that can be delivered is:

t P IN u MAX+

C pin7V ac2

2L k V OUT2

To the light of the last equations, one can note that the PFC power capability is inversely proportional to the square of the output voltage. One sees that if the power demand is too high to keep the regulation, (V REGUL=1V) and the power delivery depends on the output voltage level that stabilizes to the following value:

V OUT+

C pin71V

OUT ?V ac

Where:

?P OUT is the output power.?And h is the efficiency.

Hence, one obtains the Follower Boost characteristics. The

“Follower Boost” is an operation mode where the

pre?converter output voltage stabilizes at a level that varies

linearly versus the ac line amplitude. This technique aims at

reducing the gap between the output and input voltages to

optimize the boost efficiency and minimize the cost of the

PFC stage (refer to the MC33260 data sheet for more

information, at:

https://www.wendangku.net/doc/4211198249.html,/pub/Collateral/MC33260?D.PDF ).

Remark: the timing capacitor applied to Pin 7 is

discharged and maintained grounded when the drive is low.

Furthermore, the circuit compares the Pin 7 voltage to an

internal reference 50 mV and prevents the PWM latch from

being set as long as V Pin7 is higher than this low threshold.

This is to guarantee that the timing capacitor is properly

discharged before starting a new cycle.

Current Sense and Zero Current Detection

The NCP1605 is designed to monitor a negative voltage

proportional to the coil current. Practically, a current sense

resistor (R CS) is inserted in the return path to generate a

negative voltage proportional to the coil current (V CS). The

circuit uses V CS for two functions: the limitation of the

maximum coil current and the detection of the core reset

(coil demagnetization). To do so, the circuit incorporates

an operational amplifier that sources the current necessary

to maintain the CS pin voltage null (refer to Figure 60). By

inserting a resistor R OCP between the CS pin and R CS, we

adjust the CS pin current as follows:

*[R CS I COIL])[R OCP I pin5]+V pin5[0

Which leads to:

I pin5+

R CS

R OCP

I COIL

In other words, the Pin 5 current is proportional to the coil

current.

I Pin5 is utilized as follows:

?If I Pin5 exceeds 250 m A, an overcurrent is detected and

the PWM latch is reset. Hence, the maximum coil

current is:

(I COIL)max+

R OCP

R CS

250m A

The propagation delay (Ipin5 higher than 250 m A) to

(drive output low) is in the range of 100 ns, typically.

?The Pin 5 current is internally copied and sourced by

Pin 6. Place a resistor (R Pin6) between Pin 6 and ground

to build a voltage proportional to the coil current. The

circuit detects the core reset when V Pin6 drops below

100 mV, typically. The Pin 6 voltage equating:

V pin6+

R pin6@R cs

R cs

@I COIL,

the coil current threshold for zero current detection is: (I COIL)zcd+

R OCP

R pin6@R CS100mV+

100mV

R pin6@250m A

@(I COIL)MAX+400W

R pin6

@(I COIL)

MAX

导通时间按控制为最大功率调整如上述丆1605加工

误差放大器输出电

压形成VTON信号丆

供PWM部分使用

控制导通时间。

VTON补偿测量前

一个电流周期死区

时间的相对重量。

MOS导通期间丆

PIN7输出与PIN4

电压成比例的电流。

实际上丆因PIN4

电压于输出电压

成比例丆IPin7

与输出电压Vout

成比例。

当PIN7电压超过

VTON时MOS关断。

因此丆MOS导通时间

t1由公式给出丗

此段讲跟随模式

优点丆与其它

文章重复。

1605检测与电感

电流成比例的负

电压。实际上丆

电流检测电阻

Rcs 被放置在回

路中丆产生于电

感电流成比例的

负电压乮Vcs),

Vcs有两个用途丆

限制最大电感电

流丟监测电感复

位乮电感退磁乯

为了实现丆电路

集成一运放丆向

外灌电流以维持

CS电压为零。

乮参考图60?j。

通过在CS脚和

Rcs电阻间插入

电阻Rocp?C我们

可以调节CS脚电

流。

换言之丆PIN5电流于电感电流成比例。

Figure 60. Current Sense Block

The CS block performs the overcurrent protection and the zero current detection.

The propagation delay (V Pin6 lower than 100 mV) to (drive output high) is in the range of 300 ns, typically.

The Zero Current Detection:

?Is used to detect the dead?time sequences (“DT” high) and hence, to process (V TON) from the error amplifier output (V CONTROL). In other words, this is an input of the on?time modulation block.

?Prevents the MOSFET from turning on as long as the “DT” and “ZCD” signals are low. This is the case as long as some current flows through the coil. This delaying action on the output stage tends to make the MOSFET turn on at the valley. To further optimize the valley switching, one can apply the voltage of an auxiliary winding to Pin 6 (CS OUT). The voltage is compared to an internal 100 mV reference, so that ZCD turns high only if (V Pin6 < 100 mV).

Remarks:

?A resistor can be placed between Pin 6 and ground to increase the ZCD precision.

?It is worth highlighting that the circuit permanently senses the coil current and that it prevents any turn on of the power switch as long as the core is not reset. This feature protects the MOSFET from the possible excessive stress it could suffer from, if it was allowed to turn on while a huge current flows through the coil. In particular, this scheme effectively protects the PFC stage during the startup phase when huge in?rush currents charge the output capacitor.

?In addition this detection method does not require any auxiliary winding. A simple coil can then be used in the PFC stage.It is recommended to:

1.Keep R OCP equal to or lower than 5 k W

2.Choose R ZCD as high as possible but not bigger

than (3 x R OCP). This is to avoid that the Pin 6

leakage prevents a proper zero current detection.

For instance, if R OCP is 2.2k W, R ZCD should not

exceed 6.6 k W.

3.Place a resistor R DRV between the drive pin and

Pin 6 to ease the circuit detection by creating

some over?riding at the turn on instant. R DRV

should be selected in the range of 3 times R ZCD.

For instance, if R ZCD is 6.2 k W, a 22 k W resistor

can be used for R DRV.

Overvoltage Protection

While PFC circuits often use one single pin for both the Overvoltage Protection (OVP) and the feedback, the NCP1605 dedicates one specific pin for the undervoltage and overvoltage protections. The NCP1605 configuration allows the implementation of two separate feedback networks (see Figure 62):

?One for regulation applied to Pin 4.

?Another one for the OVP function.

可以在PIN6和地

放置一个电阻以

提高ZCD精度。

值得突出的是电

路永久检测电感电流

防止在电感复位前

导通MOS。

这种检测方式不需要辅助绕组。PFC电感简单。

Figure 61. Configuration with One Feedback Network for Both OVP and Regulation

Figure 62. Configuration with Two Separate Feedback Networks

R R ovp1

ovp2

The double feedback configuration offers some up?graded safety level as it protects the PFC stage even if there is a failure of one of the two feedback arrangements.However, if wished, one single feedback arrangement is possible as portrayed by Figure 61. The regulation and OVP blocks having the same reference voltage, the resistance ratio Rout2 over Rout3 adjusts the OVP threshold. More specifically,The bulk regulation voltage is:

V out +R out1)R out2)R out3

out2)R out3

@V ref

The OVP level is:

V ovp +

R out1)R out2)R out3

out2@V ref

The ratio OVP level over regulation level is:

V ovp

V out +1)R out3R out2

For instance, (V OVP = 105% * V out ) leads to the

following constraint: (R out3 = 5% * R out2).

As soon and as long as the circuit detects that the output voltage exceeds the OVP level, the power switch is turned off to stop the power delivery.

Remark: Like in the NCP1601, the “V TON processing circuit” is “informed” when there is an OVP condition, not to over?dimension V TON in that conditions. Otherwise, an OVP sequence would be viewed as a dead?time phase by the circuit and V TON would inappropriately increase to compensate it (refer to Figure 56).

PfcOK / REF5V Signal

The NCP1605 can communicate with the downstream converter. The signal “pfcOK/REF5V is high (5 V) when the PFC stage is in normal operation (its output voltage is stabilized at the nominal level) and low otherwise.More specifically, “pfcOK/REF5V” is low:

?During the PFC stage startup, that is, as long as the output voltage has not yet stabilized at the right level.

The startup phase is detected by the latch “L STUP ” of the block diagram. “L STUP ” is set during each “off” phase so that its output (“STUP”) is high when the circuit enters an active phase. The latch is reset when the error amplifier stops charging its output capacitor, that is,when the output voltage of the PFC stage has reached its

desired regulation level. At that moment, “STUP” falls down to indicate the end of the startup phase.

?In case of a condition preventing the circuit from

operating properly, i.e., during the V CC charge by the high voltage startup current source, in a Brown?out case or when one of the following major faults turns off the circuit:

?Incorrect feeding of the circuit (“UVLO” high when V CC

?Undervoltage Protection

?Latched off of the circuit (when the “STDWN” pin,V Pin13, exceeds 2.5 V).

And “pfcOK/REF5V” is high when the PFC output voltage is properly and safely regulated. “pfcOK/REF5V”should be used to allow operation of the downstream converter.

Standby Management

The NCP1605 automatically skips switching cycles when the power demand drops below a given level. This is accomplished by monitoring the Pin 1 voltage that must receive a voltage below 300 mV in light load conditions.Practically, a portion of the feedback signal of the downstream converter (or some other signal able to indicate that the power demand is low) should be applied to Pin 1.

NCP1605可以和下游的控制器通讯丆当PFC 平台处于正常乮输出电压恒定在正常水平乯丆pfcOK/REF5V 是高电平乮5V) .否则丆为低。更明确的丆pfcOK/REF5V 为低丗

> PFC 启动阶段丆那就是丆直到输出电压达到正确的电平。

启动阶段被框图的门槛Lstup

监测丆

Lstup 被置位在

每个关断阶段丆所以它的输出

乮STUP?j 为高

当电路进入活跃的阶段。门槛被

复位当误差放大

器停止对它的输出电容充电丆

既丆当PFC 输出

电压达到额定值丆此时丆STUP

下降标明启动

阶段的结束。

Figure 63. Signal for Standby Detection

In normal operation, the circuit controls the continuous absorption of the line current necessary for matching the load power demand. When the voltage applied to Pin 1 goes below 300 mV:

?The output pulses are blanked and Pin 3

(“V CONTROL”) is grounded.

?The output of the PFC stage being not fed any more, it drops. When the output voltage goes below 95.5% of the regulation level, the circuit resumes operation until “FLAG1” becomes low (what means that the output voltage has exceeded the regulation level).

?At that moment, if V Pin1 is still below 300 mV, a new skipping phase starts.

In other words, instead of continuously providing the output with a small amount of power, the circuit operates from time to time at a higher power level. As an example and to make it simple, instead of continuously supplying 1% of P MAX, the circuit can provide the load with 10% of P MAX for 10% of the time. The IC enters the so?called skip cycle mode, also named controlled burst operation. This burst operation is much more efficient compared to a continuous power flow as it drastically reduces the number of pulsations and therefore the switching losses associated to them.

正常情况下丆电路连续吸收市电电流丆满足负载需求丆当PIN1电压低于300mV ,

> 输出脉冲消隐丆 PIN3?iVCONTROL?j接地。

> PFC输出不再反馈丆电压跌落。当输出电压低于额定值95%?C

电路重新工作丆直到FLAG1变成低电平乮这意味着输出电压已经超过额定值乯。

> 在这种情况下丆假如PIN1仍低于300mV?C新的跳周期开始。换言之丆代替连续的小额功率提供输出丆电路工作在高效的间歇模式丆

简单举例为丆代替持续的1%的Pmax 供应丆此电路用10%的时间提供10%的Pmax给负载丆IC进入跳周期模式丆也成burst模式丆此种模式有更高效率。

Figure 64. Standby Management

300 mV

95.5% of the Regulation Level

Drive

V OUT L

SKIP

V OUT

V Pin1

V CONTROL

Remark:

?Skip cycle is not allowed during the PFC startup phase to avoid that it interferes with the soft?start. That is why,skip cycle is enabled only when “pfcOK” is high.?Each working phase of the burst mode starts smoothly as

Pin 3 is grounded at the beginning of it. This soft?start capability is effective to avoid the audible noise that could possibly result from such a burst operation.?

The circuit leaves the standby mode when the output voltage goes below 95.5% of its regulation level and V Pin1 is above 330 mV (300 mV + 30 mV hysteresis).

Oscillator / Synchronization Section

The oscillator generates the clock signal to set the PWM latch and turn the MOSFET on. The oscillator frequency is set by the capacitor that is applied to Pin 8. Typically,820pF force about 60 kHz. The maximum allowable oscillator frequency is 250 kHz. The clock frequency can also be driven by an external synchronization signal.This block contains two main parts (refer to Figure 66):?The arrangement that consists of charging/discharging current sources, a switch and a comparator. When used in oscillator mode, a capacitor is connected between Pin 8 and ground. A current source (100 m A) charges the Pin 8 capacitor until its voltage exceeds V oscH. At that moment, the comparator (“COMP_OSC”) turns high and activates the discharge current source (200 m A). As a consequence, Pin 8 actually sinks 100 m A that discharge the oscillator capacitor to V oscL. At that moment, the comparator turns low and initiates a new charge phase. If the circuit is to be externally triggered, the

synchronization signal must cross V oscL and V oscH to

properly turn on and off the “COMP_OSC” comparator.Also the synchronization signal must be low impedance enough not to be distorted by the Pin 8 source and sink currents.

?The “storing circuitry” that contains a latch and some gates. The raising edge of the “COMP_OSC” output sets the “CLOCK Generation” latch to turn high the “CLK”signal. If the timing capacitor of Pin 7 is properly

discharged (V Pin4 <50mV leading to “C T OK” high), the PWM block is ready for a new cycle and “CLK” can force the signal “V SET ” in high state. As a consequence,the PWM latch sets. In addition, “V SET ” resets the

“CLOCK Generation” latch to make it ready for the next oscillator cycle. The two inverters of Figure 66, simply generate some delay to ensure that “V SET ” keeps high long enough to set the PWM latch and reset the “CLOCK Generation” latch (longer delay than that produced by the two gates, may actually be necessary).The oscillator / Synchronization block is designed to set the switching frequency.

However, the coil current can possibly be non zero at the end of a clock period and the circuit would enter Continuous Conduction Mode (CCM) if the MOSFET turned on in that moment. In order to prevent CCM, the “storing circuitry” of the oscillator / synchronization block, memorizes the “COMP_OSC” rising edge (thanks to the “CLOCK Generation” latch) and delays the next MOSFET conduction time until the coil current has totally vanished (that is until the signal “DT” is high ? “DT” is generated by the current sense block so that it is high during the dead?time and low otherwise). In other words, CRM operation is obtained (refer to Figure 65).

启动阶段不允许跳周期丆防止干扰软启动。这就是为

什么丆当pfcok 为高电平时跳周期才激活。

Figure 65. Oscillator Timing Diagram Figure 66. Oscillator / Synchronization Block

(PWM latch

SET input)

Discontinuous Mode

Critical Mode

Clock Clock Edge Set Signal Inductor

Current

Figure 67. The Current Source brings V CC above 15 V and then Turns Off

Auxiliary Winding

9 V

Startup Sequence / V CC Management

At the moment when the PFC stage is plugged to the mains outlet, the internal current source starts charging the V CC capacitor. More generally, the startup current source is enabled whenever V CC drops below V CC STUP (7V ,typically). When V CC exceeds the V CC ON level (typically 15V), the current source turns off and the circuit starts pulsing.

The energy stored by the V CC capacitor serves to feed the controller and some auxiliary supply must take over before V CC drops below V CC OFF (9 V , typically), that is, the level below which the circuit stops pulsing.

Hence, the circuit starts operating when the V CC voltage exceeds 15 V and stops pulsing when V CC drops below 9V .The 6 V hysteresis prevents erratic operation as the V CC crosses the 15 V threshold.

Figure 67 shows the internal arrangement of this structure. One can note that the startup current source is on

during the V CC charging phase and off for the rest of the time. Hence, it spends no power during the PFC stage operation and in particular, in light load conditions. That is why the NCP1605 helps meet the most stringent standby requirements.

Remarks:

?Some circuitry (not represented in Figure 67) limits

the HV pin current below 1 mA if the V CC voltage is nearly below 1 V. This protects the circuit when the V CC pin is accidentally grounded. The full current capability (around 15 mA) is obtained when V CC exceeds about 1 V .

The circuit is also kept off when the startup current source is on to make a clear distinction between the V CC charge phase and the operating sequence (refer to “HVCS_ON” signal on block diagram).

Brown?Out Detection

The brown?out pin receives a portion of the input voltage (V IN ). As V IN is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a voltage proportional to the average value of (V IN ) is applied to the brown?out pin.The brown?out block detects too low input voltage conditions. A hysteresis comparator monitors the Pin 2voltage. Before operation, the PFC stage is off and the input bridge acts as a peak detector. Hence, the voltage applied to Pin 2 is:

V pin2+2?Vac R bo2

R bo1)R bo2

After the PFC stage has started operation, the input voltage becomes a rectified sinusoid and the voltage applied to Pin 2 is:

V pin2+

22?Vac

p R bo2bo1)R bo2

,i.e., about 64% of the previous value. Therefore, the same

line magnitude leads to a V Pin2 voltage that is 36% lower when the PFC is working than when it is off (refer to Figure 69). That is why the NCP1605 features a 50%hysteresis (V BO L = 50% V BO H).

When the circuit starts operation, the input voltage equates the ac line peak.

Hence, the initial threshold of the Brown?Out comparator, must be the upper one (V BO = V BO H = 1 V when the NCP1605 leaves the off mode).

When a brown?out condition is detected, the signal “BO_NOK” turns off the circuit (refer to block diagram).

Figure 68. Brown?Out Block

Figure 69. Typical Input Voltage of a PFC Stage

400

2000

V SIN

2?@Vac

2?@Vac @sin(R t)

Start of PFC Operation

Thermal Shutdown (TSD)

An internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150_C typically. The output stage is then enabled once the temperature drops below about 100_C (50_C hysteresis).

The temperature shutdown keeps active as long as the circuit is not reset, that is, as long as V CC keeps higher than V CC RESET. The reset action forces the TSD threshold to be the upper one (150°C). This ensures that any cold startup will be done with the right TSD level.

Output Drive Section

The output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. The gate drive is kept in a sinking mode whenever the Undervoltage Lockout is active or more generally whenever the circuit is off (i.e., when the “Fault Latch” of the block diagram is high or when the HV current source is on). Its high current capability (?500mA/+800mA) allows it to effectively drive high gate charge power MOSFET.

Reference Section

The circuit features an accurate internal reference voltage (V REF ). V REF is optimized to be ±3% accurate over the temperature range (the typical value is 2.5 V). V REF is

the voltage reference used for the regulation and the overvoltage protection. The circuit also incorporates a precise current reference (I REF ) that allows the Overcurrent Limitation to feature a ±6% accuracy over the temperature range.

OFF Mode

As previously mentioned, the circuit turns off in the following cases:

?When the high voltage, startup current source charges the V CC capacitor.

?When one of the following major faults is detected:?Incorrect feeding of the circuit (“UVLO” high when V CC

?Brown?Out condition.?Undervoltage Protection.

?V Pin13 higher than 2.5 V (“STDWN” of the block diagram turns high).

Generally speaking, the circuit turns off when the conditions are not proper for good operation. In this mode,the controller stops operating. The major part of the circuit sleeps and its consumption is minimized (< 500 m A).

More specifically, when the circuit is in OFF state:?The drive output is kept low

?All the blocks are off except:

1.The UVLO circuitry that keeps monitoring the

V CC voltage and controlling the startup current

source accordingly.

2.The TSD (thermal shutdown)

3.The “STDWN” latch that stores its output state.

4.The Undervoltage Protection (“UVP”).

5.The brown?out circuitry. One must note that the

comparator is reset during the latched?off phase

so that its threshold is the upper one (1 V) when

the circuit enters the active phase (refer to next

“V CC sequences”section).

6.The high voltage, startup current source when the

circuit is in startup phase (that is when V CC is

lower than V CC STUP).?The Pin 3 capacitor is discharged and kept grounded along the OFF time, to initialize it for the next operating sequence, where it must be slowly and gradually charged to offer some soft?start.

?The “pfcOK” pin is grounded.

?The output of the “V TON processing block” is grounded

V CC Sequences

The following table summarizes the state of the circuit in accordance to the V CC level.

V CC Conditions

“OFF” is Low

(no condition forces the circuit off)

“OFF” is High

(due to some protection like the thermal shutdown)

V CC exceeds V CC ON ? the circuit enters the working phase The startup current source is disabled

The circuit is fully active

The startup current source is disabled

The circuit is in OFF state

V CC drops below V CC OFF ? the circuit enters the latched?of f phase The circuit is in OFF state

The brown?out block resets during the

latched?of f phase so that its comparator

threshold is forced to be the upper one (1 V)

The circuit is in OFF state

The brown?out block resets during the latched?off

phase so that its comparator threshold is forced to be

the upper one (1 V)

V CC goes below V CC STUP ? the circuit enters the startup phase The high voltage, startup current source turns

on to charge V CC.

The drive output and the “pfcOK” are in low

state (the circuit is off)

All the circuit blocks are reset except:

The thermal shutdown (TSD) and the

brown?out block that keep operating

The “STDWN” latch.

The high voltage, startup current source turns on to

charge V CC.

The drive output and the “pfcOK” are in low state (the

circuit is off)

All the circuit blocks are reset except:

The thermal shutdown (TSD) and the brown?out

block that keep operating

The “STDWN” latch.

V CC goes below V CC RESET ? the circuit resets The high voltage, startup current source is on.

The whole circuitry is reset including the

“TSD” and the “STDWN” latch. After reset,

the TSD threshold is 150°C and the output of

the “STDWN latch” is low.

The high voltage, startup current source is on.

The whole circuitry is reset including the “TSD” and the

“STDWN” latch. After reset, the TSD threshold is 150°C

and the output of the “STDWN latch” is low.

The figures on the following pages portray the circuit behavior during a startup phase:?In case of normal conditions (Figure70).

?As a function of the brown?out pin voltage (Figure71).

Remarks:

The V CONTROL signal does not necessarily reach its clamp level (3.7 V) depending of the load and of the system time constants. In particular, if the circuit starts operation in light load and if the bulk capacitor is not too large, the output voltage V OUT generally exceeds the regulation level while V CONTROL keeps below its upper limit.

The output voltage exhibits a 100 or 120 Hz ripple (at twice the line frequency). This ripple is also present in the V CONTROL voltage even if it is attenuated due to the regulation low bandwidth. Like that of V OUT , this ripple is not represented in Figure 70, for the sake of the clarity.

Figure 70. Startup Phase in Normal Conditions

V CC

V OUT

V CONTROL

Flag1

Drive Output

pfcOK

Circuit State

OFF

V CC ON

V CC OFF

1 V

V CC STUP

V OUT Regulation Level

V CONTROL MAX = 3.7 V

These re?activations of “Flag1” result from V OUT 100 or 120 Hz ripple (not represented here for the sake of clarity)

Figure 71. Startup and Brown Out Conditions

When the high voltage, startup current source is on, the brown?out is active and its threshold is the upper one (V BO = V BO H = 1 V).

V out Regulation Level

V CC STUP

V CC OFF

1 V

0.5 V

The Circuit is Off ≥ Low Consumption

1 V

V CC ON

OFF

V CC

V OUT

Brown?Out Pin Voltage

Drive Output

Circuit State

pfcOK

Fault Management Block When any of the following faults is detected: brown?out (“BO_NOK”), Undervoltage (“UVP”), shutdown (“STDWN”), Die Overtemperature (“TSD”), the circuit immediately turns off and recovers operation as soon as the fault disappears.

In case of UVLO (V CC too low to allow operation), the circuit keeps off until the end of the next V CC charge phase by the HV startup current source.

The following block diagram details the function.

Figure 72. Fault Management Block

Bulk

BO on

BO off

Single Hiccup V CC

V CCon

Internal

BO ok

V CCoff

Drive

Figure 73.

The above figure shows how the circuit recovers after a brown?out event.

A4931 datasheet 中文+总结

本人使用过程中翻译了本文，水平有限难免有误，欢迎纠正：tyooo@https://www.wendangku.net/doc/4211198249.html, A4931 3-Phase Brushless DC Motor Pre-Driver 三相无刷直流电机前置驱动器 4931-DS, Rev. 4 下载：：https://www.wendangku.net/doc/4211198249.html,/~/media/Files/Datasheets/A4931-Datasheet.ashx 下载翻译：2012-11-15

? ? ? ? ? ? ? ?

本人使用过程中翻译了本文，水平有限难免有误，欢迎纠正： tyooo@https://www.wendangku.net/doc/4211198249.html, A4931 三相无刷直流电机前置驱动器 Absolute Maximum Ratings Thermal Characteristics *For additional information, refer to the Allegro website. Characteristic Symbol Notes Rating Units 供电电压Load Supply Voltage V BB 38 V 电机输出Motor Phase Output S X t w < 500 ns –3 V 霍尔输入 V Hx DC –0.3 to 7 V 逻辑输入电压范围 V IN –0.3 to 7 V 工作环境温度 T A Range M –20 to 105 oC 最大结温度 T J (max) 150 oC 储藏温度 T stg –40 to 150 oC Characteristic Symbol Test Conditions* Rating Units 封装内阻，结点到外面（Junction to Ambient ） R θJA 4-layer PCB based on JEDEC standard 32 oC/W 封装内阻，结点到焊盘（Junction to Exposed Pad ） R θJP 2 oC/W

4511;中文规格书,Datasheet资料

Pomona ? All dimensions are in inches. Tolerances (except noted): .xx = ±.02” (,51 mm), .xxx = ± .005” (,127 mm). All specifications are to the latest revisions. Specifications are subject to change without notice. Registered trademarks are the property of their respective companies. Made in USA 6/9/99 Pomona ACCESS 90173 (800) 444-6785 or (425) 446-6010 SY/EH/LS More drawings available at https://www.wendangku.net/doc/4211198249.html, Page 1 of 1 Model, 3263, 3264, 4511, 4512 Standard Banana Plug With Threaded Stud and Solder Lug Sales: 800-490-2361 Fax: 888-403-3360 Technical Assistance: 800-241-2060 ? Threaded stud for rapid mounting. ? Furnished with hex nut and tin plated solder lug. ? Ideal for connecting power supplies or test equipment to prototype circuit boards. ? Mates to Model #1581 or any standard banana jack. MATERIALS: Banana plug: Spring: Beryllium Copper, Berylco 25 per QQ-C-533, Cond. HT. Plug Body: Brass per QQ-B-626, Alloy 360, ? Hard Solder lug: Material: Copper per QQ-C-576. Finish: Electro-tin plated. Hex Nut, 8-32: Material: Brass per QQ-B-626, Composition 22, ? Hard Finish: Nickel plated. RATINGS: Working Voltage: 5000 VRMS Current: 15 Amperes ORDERING INFORMATION: Model 3263 Parts are packaged ten per bag, unassembled. https://www.wendangku.net/doc/4211198249.html,/

7443550230;中文规格书,Datasheet资料

Bezeichnung :description : Marking = part number Eigenschaften / properties Lerrlaufinduktivit?t/initial inductance Nenn-Induktivit?t /33%Umgebungstemperatur / temperature: +20°C WE-Perm ME 08-01-01ME 06-11-19ME 05-04-16ME 05-03-30ME 05-03-15 Name Datum / date ?nderung / modification Version 1 Version 2Version 3Version 4Version 5Umgebungstemp. / ambient temperature: -40°C - +105°C It is recommended that the temperature of the part does F Werkstoffe & Zulassungen / material & approvals : Elektrische Eigenschaften / electrical properties : SPEICHERDROSSEL WE-HCI POWER-CHOKE WE-HCI Artikelnummer / part number :7443550230 Würth Elektronik eiSos GmbH & Co. KG D-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400 Geprüft / checked ................................................................................................. ..................................................................................Unterschrift / signature Kontrolliert / approved Würth Elektronik .................................................................................. E Testbedingungen / test conditions : HP 34401 A & Fluke 54II für/for I DC; Luftfeuchtigkeit / humidity: Metra HIT 27I für/for R DC WAYNE KERR 3260B für/for L 0; I SAT D Prüfger?te / test equipment : G Eigenschaften / general specifications : not exceed 155°C under worst case operating conditions. Draht / wire: AIEIW-200 Arbeitstemperatur / operating temperature: -40°C - +155°C Basismaterial / base material:Freigabe erteilt / general release: Kunde / customer http://www.we-online.de Datum / date

MT6595datasheet_中文版

MT6595八核智能手机应用处理器简介 1.系统简介 MT6595是一款集成了调制解调和应用处理的基带平台，应用于4G(LTE)智能手机。芯片集成了工作频率高达2.2G赫兹的ARM? Cortex-A17，工作频率高达1.7G赫兹的ARM? Cortex-A7 MPCore TM，ARM? Cortex-R4微处理单元和多标准视频编解码器。MT6595支持LPDDR3，同时也支持从eMMC启动来减小BOM成本。另外芯片还集成了一系列接口来连接摄像机、触摸显示屏、usb3.0和MMC/SD卡。带有NEON引擎的四核ARM? Cortex-A17 MPCore TM和四核Cortex-A7 MPCore TM应用处理器，提供了支持最新的开放式操作系统的处理能力，包括网页浏览，邮件，GPS导航和游戏。所有的这些应用都可以在一个高分辨率的触摸显示器上实现，同时通过3D图形加速器来提高图形显示质量。多标准视频编解码器和先进的音频子系统提供了超酷的多媒体体验，支持流媒体和一系列的解码器和编码器，例如，HEVC 和H.264。音频支持FR,HR, EFR, AMR FR, AMR HR and Wide-Band AMR 声码器，和弦铃声和先进的音频功能，如回声消除，免提操作和有源噪声消除。调制解调器子系统集成了ARM? Cortex-R4, DSP和2G and 3G 处理器，支持LTE Cat 4(150Mbps), Category 24 (42 Mbps) HSDPA 下行链路和Category 7(11 Mbps) HSUPA 上行链路数据速率，Category 14 (2.8Mbps) TD-HSDPA 下行链路Category6(2.2Mbps)TD-HSUPA 上行链路数同时也支持Class 12 GPRS, EDGE. 芯片整体提高了声音、数据和音视频在手机和媒体平板上的同步传输。小面积低功耗也大大降低了PCB的布局资源。 1.1. 平台功能 ●综述两个微处理单元子系统结构 eMMC启动下载 ●应用微处理单元子系统四核ARM? Cortex-A17 MPCore TM,工作频率2.2GHz,2MB二级缓存四核ARM? Cortex-A7 MPCore TM,工作频率1.7GHz,512KB二级缓存支持SIMDv2 / VFPv4 ISA的NEON多媒体处理器 32KB一级指令缓存和32KB一级数据缓存 DVFS技术，从0.8V到1.15V的自适应操作电压 ●调制解调器微处理单元子系统支持双SIM/USIM接口射频和无线相关设备的接口引脚（天线调谐器，功率放大器……） ●外部存储器接口支持4G LPDDR3 双通道，每个通道32bit数据总线宽度存储时钟高达933MHz 支持自刷新/部分自刷新模式低功耗操作存储控制器IO转换可编程支持两级连接存储设备先进的带宽仲裁控制

7448709330;中文规格书,Datasheet资料

description : 33% Umgebungstemperatur / temperature: +20°C Ferrit/ ferrite Betriebstemp. / operating temperature: -40°C - + 125°C Umgebungstemp. / ambient temperature: -40°C - + 85°C It is recommended that the temperature of the part does not exceed 125°C under worst case operating conditions. SST 08-10-06 Name Datum / date ?nderung / modification Version 1 G Eigenschaften / general specifications: Basismaterial / base material:Draht / wire: 2 SFBW; 155°C F Werkstoffe & Zulassungen / material & approvals: E Testbedingungen / test conditions: Luftfeuchtigkeit / humidity: HP 34401 A für/for I DC und/and R DC HP 4274 A für/for L und/and Q D Prüfger?te / test equipment: ............................................... ............................................ Würth Elektronik .................................................................................. Freigabe erteilt / general release: Kunde / customer http://www.we-online.de Datum / date ..................................................................................Unterschrift / signature Kontrolliert / approved Würth Elektronik eiSos GmbH & Co. KG D-74638 Waldenburg · Max-Eyth-Strasse 1 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400 Geprüft / checked POWER-CHOKE WE-DD

744231091;中文规格书,Datasheet资料

5.1 5.0 4.02012-07-17 2012-07-17 2010-11-02 SSt SSt SBa SSt SBa Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 1 74638 Waldenburg Germany Tel. +49 (0) 79 42 945 - 0 https://www.wendangku.net/doc/4211198249.html, A Dimensions: [mm] C Schematic:

F Typical Impedance Characteristics:

H1: Classification Reflow Profile for SMT components: H2: Classification Reflow Profiles Profile Feature Preheat - Temperature Min (T smin ) - Temperature Max (T smax ) - Time (t s ) from (T smin to T smax )Ramp-up rate (T L to T P )Liquidous temperature (T L )Time (t L ) maintained above T L Peak package body temperature (T p )Time within 5°C of actual peak temperature (t p )Ramp-down rate (T P to T L )Time 25°C to peak temperature Pb-Free Assembly 150°C 200°C 60-180 seconds 3°C/ second max.217°C 60-150 seconds See Table H320-30 seconds 6°C/ second max.8 minutes max. refer to IPC/JEDEC J-STD-020D H3: Package Classification Reflow Temperature PB-Free Assembly PB-Free Assembly PB-Free Assembly Package Thickness < 1.6 mm 1.6 - 2.5 mm ≥ 2.5 mm Volume mm3<350260°C 260°C 250°C Volume mm3350 - 2000260°C 250°C 245°C Volume mm3>2000260°C 245°C 245°C refer to IPC/JEDEC J-STD-020D H Soldering Specifications:

0511101056;中文规格书,Datasheet资料

This document was generated on 08/13/2012 PLEASE CHECK https://www.wendangku.net/doc/4211198249.html, FOR LATEST PART INFORMATION Part Number:51110-1056Status:Active Overview:Milli-Grid? Connector System Description: 2.00mm Pitch, Milli-Grid? Crimp Housing, 10 Circuits, with Center Locking Ramp and Side Polarization Keys, Lead-Free Documents:3D Model Product Specification PS-51110-001 (PDF)Drawing (PDF) RoHS Certificate of Compliance (PDF) General Product Family Crimp Housings Series 51110 Application Signal, Wire-to-Board Comments Applicable Wire Range: 24-30 AWG Overview Milli-Grid? Connector System Product Name Milli-Grid?UPC 800753616998Physical Circuits (maximum)10Color - Resin Black Gender Female Glow-Wire Compliant No Lock to Mating Part Yes Material - Resin Polyester Net Weight 0.203/g Number of Rows 2Packaging Type Bag Panel Mount No Pitch - Mating Interface 2.00mm Polarized to Mating Part Yes Stackable Yes Temperature Range - Operating -40°C to +105°C Material Info Reference - Drawing Numbers Product Specification PS-51110-001 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Not Low-Halogen Need more information on product environmental compliance? Email productcompliance@https://www.wendangku.net/doc/4211198249.html, For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 51110Series Mates With 87758 Vertical, Through Hole, Stackable PCB Header, 87759 Vertical, Surface Mount, Stackable PCB Header, 87760 Right Angle, Through Hole, Stackable PCB Header, 87831 Vertical, Through Hole PCB Header, 87832 Vertical, Surface Mount PCB Use With 50394 Crimp Terminals This document was generated on 08/13/2012 PLEASE CHECK https://www.wendangku.net/doc/4211198249.html, FOR LATEST PART INFORMATION https://www.wendangku.net/doc/4211198249.html,/

IMU-FSAS Datasheet(中文)

产品特性

Version 4 -Specifications subject to change without notice. ?2010 NovAtel Inc. All rights reserved. ProPak, Inertial Explorer, RT-20, Waypoint and NovAtel are registered trademarks of NovAtel Inc. SPAN, IMU-FSAS and RT-2 are trademarks of NovAtel Inc. Printed in Canada. D10150 IMU-FSAS August 2010 想了解该产品的更多信息请访问 https://www.wendangku.net/doc/4211198249.html,/assets/Documents/Papers/FSAS.pdf 1 典型值。性能规格如GPS 系统的特点，受US DOD 业务退化，电离层和对流层，卫星几何，基线长度，多径效应和有意或无意的干扰源的影响 2 只有GPS 可用。 3静态收敛后的预计精度 4 当SPAN 的定位模式为RTK 时。 5出口许可限制操作515m/S 6 GNSS 接收机能持续跟踪达4g 7使用IE 后处理如见处理的结果。. Statements related to the export of products are based solely on NovAtel’s experience in Canada, are not binding in any way and exportability may be different with respect to the export regulations in effect in another country. The responsibility for re-export of product from a Customer’s facility is solely the responsibility of the Customer.

744242510;中文规格书,Datasheet资料

4.1 4.0 3.02012-07-17 2012-07-17 2006-02-08 SSt SSt MST SSt SBa Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 1 74638 Waldenburg Germany Tel. +49 (0) 79 42 945 - 0 https://www.wendangku.net/doc/4211198249.html, A Dimensions: [mm]

F Typical Impedance Characteristics:

EXC2668 datasheet 中文版

LED驱动控制专用电路EXC2668一、概述 EXC2668是一种带键盘扫描接口的LED驱动控制专用电路，内部集成有MCU 数字接口、数据锁存器、LED 高压驱动、键盘扫描等电路。本产品性能优良，质量可靠。主要应用于VCR、VCD、DVD、家庭影院、空调、洗衣机等产品的显示屏驱动。通过严格工业级测试标准，采用SOP28 的封装形式。二、特性说明 ? 采用CMOS 工艺 ? VDD： 5V 低功耗 ? 多种显示模式（10 段×7 位～ 11 段×6 位） ? 键扫描（10×2bit） ? 辉度调节电路（占空比8 级可调） ? 串行接口（CLK，STB，DA） ? 振荡方式：RC 振荡 ? 内置上电复位电路 ? 封装形式：SOP28

三、内部功能框图四、管脚定义

管脚功能定义符号管脚名称管脚号说明 OSC 振荡器引脚 1 该脚通过连接一下拉电阻来确定振荡频率 DA 数据输入输出 2 在时钟上升沿输入串行数据，从低位开始。在时钟下降沿输出串行数据，从低位开始，输出为N-ch open drain (注：DA脚芯片内部为DIN、DOUT复用脚) CLK 时钟输入 3 在上升沿读取串行数据，下降沿输出数据 STB 片选 4 在上升或下降沿初始化串行接口，随后等待接收指令。STB 为低后的第一个字节作为指令，当处理指令时，当前其它处理被终止。当STB 为高时，CLK 被忽略 K1~K2 键扫数据输入5,6 输入该脚的数据在显示周期结束后被锁存 SEG1/KS1~ SEG10/KS10 输出（段）8，9，10， 11，12，13， 14，15，16， 17 段输出（复用作键扫描） SEG12/COM7 输出（段/位）18 段/位复用输出 COM1~COM6 输出位19，20，23， 24，26，27 位输出 VDD 逻辑电源7，21 5V±10% GND 逻辑地 22，25，28接系统地

7447714220;中文规格书,Datasheet资料

Bezeichnung : description : A mm B mm C mm D mm E mm Eigenschaften / properties Wert / value Einheit / unit tol. Induktivit?t / inductance DC-Widerstand / DC-resistance DC-Widerstand / DC-resistance Nennstrom / rated Current S?ttigungsstrom / saturation current Eigenres.-Frequenz / self-res.-fequency 33% Umgebungstemperatur / temperature:+20°C Ferrit/ ferrite ALa11-02-17 Name Datum / date 1050 ?nderung / modification Version 1 5,0 max 10,0 ± 0,5 3,0 ± 0,1 7,7 ± 0,3 F Werkstoffe & Zulassungen / material & approvals: G Eigenschaften / general specifications: Betriebstemp. / operating temperature: -40°C - +125°C ........................................................................................... Basismaterial / base material: Draht / wire:Class H Agilent N5776A für/for I DC; WAYNE KERR 3260B für/for L0; I SAT D Prüfger?te / test equipment: @ 20°C 10,0 ± 0,3 It is recommended that the temperature of the part does max. Kunde / customer Luftfeuchtigkeit / humidity: E Testbedingungen / test conditions: GMC Metrahit 27I für/for R DC Agilent E4991A für/for SRF not exceed 125°C under worst case operating conditions. Würth Elektronik .................................................................................. Freigabe erteilt / general release: http://www.we-online.de Datum / date .................................................................................. Unterschrift / signature Kontrolliert / approved Würth Elektronik eiSos GmbH & Co. KG D-74638 Waldenburg · Max-Eyth-Strasse 1 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400 Geprüft / checked DATUM / DATE : 2011-02-17 max. Testbedingungen / test conditions 50 +/-20% Endoberfl?che / finishing electrode:Cu/Ni/Sn C L?tpad / soldering spec.: B Elektrische Eigenschaften / electrical properties: Umgebungstemp. / ambient temperature: -40°C - +85°C 14,5 @ 20°C SPEICHERDROSSEL WE-PD 1050 POWER INDUCTOR WE-PD 1050 μH R DC max L A Mechanische Abmessungen / dimensions: 100 kHz / 1mA R DC typ42 22 I R m? @ 20°C m? typ. 3,6 typ. 3A ?L/L < 10% f res MHz ?T = 40 K typ. I sat A [mm]

744228;中文规格书,Datasheet资料

8.1 8.0 7.02012-07-17 2012-07-17 2004-10-11 SSt SSt MST SSt SBa Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 1 74638 Waldenburg Germany Tel. +49 (0) 79 42 945 - 0 https://www.wendangku.net/doc/4211198249.html, A Dimensions: [mm]

F Typical Impedance Characteristics:

XL2576中文datasheet

特点： ? 宽输入电压范围 3.6-40V ? 有 3.3V ，5V 和可调版本 ? 输出可调范围1.23V-38V ? 最大占空比100% ? 最小饱和压降1.3V ? 3A 输出电流能力 ? 内部优化功率管设计 ? 效益高达90% ? 输出线性好且负载可调 ? TTL 关断能力 ? 内置频率补偿，软启动功能，热关断功能，限流功能短路保护功能 ? 可选封装形式：TO-220，TO-263 应用领域： ? LCD 监控器，LCD 电视 ? 数码像框 ? 机顶盒 ? 调制解调器 ? 通信/网络设备概述 XL2576是一个52KHz 固定频率脉宽调制（降压型）DC/DC 转换器。高效率且高达3A 负载驱动能力，低纹波，极好的线性和负载调节能力，仅需最少外部元。可调输出使用简单，内建频率补偿和固定频率震荡器。脉宽调制控制电路可以线性调节占空比从0到100%。具有使能功能，内置过流和短路保护功能，当发生过流和短路保护时，XL2576工作频率从52KHz 降到31KHz 。内置频率补偿模块使XL2576外部元件最少。图1. XL2576封装类型

引脚设置图2. XL2576引脚结构（顶视图）表格1引脚描述

功能模块图3： XL2576功能块方框图典型应用电路图4.XL2576典型应用电路12V-5V/3A

XLSEMI 无铅产品，只要正面号码带有“E1”后缀，都符合RoHS 标准

最大额定值（注释1）注释1：工作在列表的最大额定值以上会造成器件永久损坏。这是只是强调，并不意味着不可以工作在此条件或任何其他以上条件，长时间在最大额定值条件可能影响器件的可靠性。

XL4201 datasheet中文版

宽输入电压范围 n输出电压从1.25V到37V可调n最小压差0.3V n固定150KHz开关频率 n最大3A开关电流 n内置功率MOS n出色的线性与负载调整率 n内置恒流环路 n内置频率补偿功能 n内置输出短路保护功能 n内置输入过压保护功能 n内置热关断功能 n推荐输出功率小于13W n SOP8-EP封装应用 n车载充电器 n电池充电器 n LCD电视与显示屏 n便携式设备供电 n通讯设备供电 n降压恒流驱动 n显示器LED背光 n通用LED照明描述 XL4201是一款高效降压型DC-DC转换器，可工作在DC8V到40V输入电压范围，低纹波，内置功率MOS。XL4201内置固定频率振荡器与频率补偿电路，简化了电路设计。 PWM控制环路可以调节占空比从0~100%之间线性变化。内置输出过电流保护功能。内部补偿模块可以减少外围元器件数量。图1.XL4201封装

150KHz 40V 3A开关电流自带恒流环路降压型DC-DC转换器 XL4201 引脚配置图2. XL4201引脚配置表1.引脚说明引脚号引脚名称引脚描述 1,6 NC 无连接。 2 SW 功率开关输出引脚，SW是输出功率的开关节点。 3 GND 接地引脚。 4 FB 反馈引脚，通过外部电阻分压网络，检测输出电压进行调整，参考电压为1.25V。 5 CS 输出电流检测引脚（IOUT=0.11V/RCS）。 7 VC 内部电压调节旁路电容，需要在VC与VIN之间并联1uF电容。 8 VIN 输入电压，支持DC8V~40V宽范围电压操作，需要在VIN与GND 之间并联电解电容以消除噪声。背部焊盘为SW

744224;中文规格书,Datasheet资料

6.1 6.0 5.02012-07-17 2012-07-17 2004-10-11 SSt SSt MST SSt SBa Würth Elektronik eiSos GmbH & Co. KG EMC & Inductive Solutions Max-Eyth-Str. 1 74638 Waldenburg Germany Tel. +49 (0) 79 42 945 - 0 https://www.wendangku.net/doc/4211198249.html, A Dimensions: [mm]

F Typical Impedance Characteristics: