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k4s641632h-uc75

SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM

64Mb H-die SDRAM Specification

54 TSOP-II with Pb-Free

(RoHS compliant)

Revision 1.3

August 2004

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Revision History

Revision 1.0 (September, 2003)

? Finalized

Revision 1.1 (October, 2003)

Deleted speed -7C and AC parameter notes 5.

Revision 1.2 (May, 2004)

? Added Note 5. sentense of tRDL parameter

Revision 1.3 (August, 2004)

? Corrected typo.

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM

Rev. 1.3 August 2004

Part No.

Orgainization Max Freq.Interface

Package

K4S640432H-UC(L)7516Mb x 4 133MHz(CL=3)LVTTL

54pin TSOP(II)

K4S640832H-UC(L)758Mb x 8

133MHz(CL=3) K4S641632H-UC(L)604Mb x 16166MHz(CL=3) K4S641632H-UC(L)70143MHz(CL=3) K4S641632H-UC(L)75

133MHz(CL=3)

The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high perfor-mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

? JEDEC standard 3.3V power supply

? LVTTL compatible with multiplexed address ? Four banks operation

? MRS cycle with address key programs -. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

? All inputs are sampled at the positive going edge of the system clock

? Burst read single-bit write operation

? DQM (x4,x8) & L(U)DQM (x16) for masking ? Auto & self refresh

? 64ms refresh period (4K cycle)

? Pb-free Package

? RoHS compliant

GENERAL DESCRIPTION

FEATURES

Ordering Information

4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM

Row & Column address configuration

Organization

Row Address Column Address

16Mx4A0~A11A0-A98Mx8A0~A11A0-A84Mx16

A0~A11

A0-A7

SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Package Physical Dimension

54Pin TSOP(II) Package Dimension

Rev. 1.3 August 2004

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

LWE LDQM

DQi

Samsung Electronics reserves the right to change products or specification without notice.

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

23456789101112131415161718192021222324252627

545352515049484746454443424140393837363534333231302928

PIN CONFIGURATION (Top view)

54Pin TSOP (II)(400mil x 875mil)(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

Pin Name

Input Function

CLK System clock Active on the positive going edge to sample all inputs.

Chip select

Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM

CKE Clock enable

Masks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.

A 0 ~ A 11Address

Row/column addresses are multiplexed on the same pins.Row address : RA 0 ~ RA 11,

Column address : (x4 : CA 0 ~ CA 9, x8 : CA 0 ~ CA 8 , x16 : CA 0 ~ CA 7)BA 0 ~ BA 1Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.

RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.

CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.

WE Write enable

Enables write operation and row https://www.wendangku.net/doc/4311691462.html,tches data in starting from CAS, WE active.

DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when DQM active.

DQ 0 ~ X15Data input/output Data inputs/outputs are multiplexed on the same pins.V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic.

V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.

N.C/RFU

No connection

/reserved for future use

This pin is recommended to be left No Connection on the device.

x16

x8x4x16

V DD DQ0V DDQ DQ1DQ2V SSQ DQ3DQ4V DDQ DQ5DQ6V SSQ DQ7V DD LDQM WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ15V SSQ DQ14DQ13V DDQ DQ12DQ11V SSQ DQ10DQ9V DDQ DQ8V SS

N.C/RFU UDQM CLK CKE N.C A11A9A8A7A6A5A4V SS

V DD

N.C V DDQ N.C DQ0V SSQ N.C N.C V DDQ N.C DQ1V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/AP

A0A1A2A3V DD

V SS N.C V SSQ N.C DQ3V DDQ N.C N.C V SSQ N.C DQ2V DDQ N.C V SS

N.C/RFU DQM CLK CKE N.C A11A9A8A7A6A5A4V SS

V DD DQ0V DDQ N.C DQ1V SSQ N.C DQ2V DDQ N.C DQ3V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ7V SSQ N.C DQ6V DDQ N.C DQ5V SSQ N.C DQ4V DDQ N.C V SS

N.C/RFU DQM CLK CKE N.C A11A9A8A7A6A5A4V SS

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit Voltage on any pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to V SS V DD , V DDQ

-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150

°C Power dissipation P D 1W Short circuit current

I OS

Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage V DD , V DDQ

3.0 3.3 3.6V Input logic high voltage V IH 2.0 3.0V DD +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mA

Input leakage current

I LI

-10

31. V IH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ V IN ≤ V DDQ .

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)

Symbol Min Max Unit Note Clock

C CLK 2.5 4.0pF 1RAS, CAS, WE, CS, CKE, DQM C IN 2.5 5.0pF 2Address C AD

D 2.5 5.0pF 2DQ 0 ~ DQ 3

C OUT

4.0

6.5

1. -75 only specify a maximum value of 3.5pF

2. -75 only specify a maximum value of

3.8pF 3. -75 only specify a maximum value of 6.0pF

Notes :

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S6404(08)32H-TC**

4. K4S6404(08)32H-TL**

5. Unless otherwise noted, input swing IeveI is CMOS(V IH /V IL =V DDQ /V SSQ)

Notes :(Recommended operating condition unless otherwise noted, T A = 0 to 70°C for x4, x8)

Parameter

Symbol

Test Condition

Version Unit Note

75Operating current (One bank active)

I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA

75mA 1

Precharge standby current in power-down mode

I CC2P CKE ≤ V IL (max), t CC = 10ns 1mA

I CC2PS CKE & CLK ≤ V IL (max), t CC = ∞

1Precharge standby current in non power-down mode I CC2N

CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns

Input signals are changed one time during 20ns

I CC2NS

CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞

Input signals are stable 6Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 3mA

I CC3PS CKE & CLK ≤ V IL (max), t CC = ∞

3Active standby current in non power-down mode (One bank active)

I CC3N

CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns

Input signals are changed one time during 20ns

I CC3NS

CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞

Input signals are stable 25

Operating current (Burst mode)I CC4 I O = 0 mA Page burst

4Banks Activated t CCD = 2CLKs 115mA 1Refresh current I CC5t RC ≥ t RC (min)135mA 2Self refresh current

I CC6

CKE ≤ 0.2V

C 1mA 3L

400

DC CHARACTERISTICS

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S641632H-TC**

4. K4S641632H-TL**

5. Unless otherwise noted, input swing IeveI is CMOS(V IH /V IL =V DDQ /V SSQ)

Notes :DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T A = 0 to 70°C for x16 only)

Parameter

Symbol

Test Condition

Version

Unit Note

Operating current (One bank active)

I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA

140115

110mA 1

Precharge standby current in power-down mode

I CC2P CKE ≤ V IL (max), t CC = 10ns 1mA

I CC2PS CKE & CLK ≤ V IL (max), t CC = ∞

1Precharge standby current in non power-down mode I CC2N

CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns

Input signals are changed one time during 20ns

I CC2NS

CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞

Input signals are stable 6Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 3mA

I CC3PS CKE & CLK ≤ V IL (max), t CC = ∞

3Active standby current in non power-down mode (One bank active)

I CC3N

CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10ns

Input signals are changed one time during 20ns

I CC3NS

CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞

Input signals are stable 25

Operating current (Burst mode)I CC4 I O = 0 mA Page burst

4Banks Activated t CCD = 2CLKs 160140135mA 1Refresh current I CC5t RC ≥ t RC (min)160

140

135

mA 2Self refresh current

I CC6

CKE ≤ 0.2V

C 1mA 3L

400

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)

Parameter Value Unit AC input levels (Vih/Vil)

2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall time

tr/tf = 1/1ns Output timing measurement reference level 1.4V

Output load condition

See Fig. 2

3.3V

1200?

870?

Output

30pF

V OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mA

Vtt = 1.4V

50?

Output

30pF

Z0 = 50?

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Symbol Version

Unit Note 607075Row active to row active delay t RRD (min)121415ns 1RAS to CAS delay t RCD (min)182020ns 1Row precharge time t RP (min)182020ns 1Row active time t RAS (min)42

4945

ns 1

t RAS (max)100us Row cycle time

t RC (min)60

6865ns 1Last data in to row precharge t RDL (min)2CLK 2,5Last data in to Active delay

t DAL (min) 2 CLK + tRP

-5Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stop

t BDL (min)1CLK 2Col. address to col. address delay t CCD (min)

1CLK 3Number of valid output data

CAS latency = 32ea

4CAS latency = 2

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Symbol Condition Min Typ

Max Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall time

tfh

Measure in linear region : 1.2V ~ 1.8V

2.0

2.9 5.0

Volts/ns

1,2

1. Rise time specification based on 0pF + 50 ? to V SS , use these values to design to.

2. Fall time specification based on 0pF + 50 ? to V DD , use these values to design to.

3. Measured into 50pF only, use these values to characterize to.

4. All measurements done with respect to V SS .

Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter

Symbol

6070

Unit Note

Min Max Min Max Min Max CLK cycle time CAS latency=3t CC 61000710007.51000ns 1

CAS latency=2--10

CLK to valid output delay CAS latency=3t SAC 56 5.4ns 1,2

CAS latency=2--6

Output data hold time

CAS latency=3t OH 2.533ns 2CAS latency=2

--3CLK high pulse width t CH 2.53 2.5ns 3CLK low pulse width t CL 2.53 2.5ns 3Input setup time t SS 1.52 1.5ns 3Input hold time t SH 110.8ns 3CLK to output in Low-Z t SLZ

1ns

CLK to output in Hi-Z

CAS latency=3t SHZ

56 5.4ns

CAS latency=2

--6

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

I OH Characteristics (Pull-up)

Voltage 133MHz Min 133MHz Max (V)I (mA)I (mA)3.45- -1.683.30- -19.113.00-0.35 -51.872.70-3.75-90.442.50-6.65-107.311.95-13.75-137.91.80-17.75-158.341.65-20.55-173.61.50-23.55-188.791.40-26.2-199.011.00-36.25-241.150.20

-46.5

-351.68

IBIS SPECIFICATION

I OL Characteristics (Pull-down)

Voltage 133MHz Min 133MHz Max (V)I (mA)I (mA)3.4543.92155.823.30--3.0043.36153.721.9541.20148.401.8040.56146.021.6539.60141.751.5038.40136.081.4037.28131.391.0030.08105.840.8526.6493.660.6521.5275.250.40

14.16

49.14

0-100-200-300-400-500-600

0.5

1.5

2.5

3.5

Voltage

m A

250

200

1501005000

0.5

1.5

2.5

3.5

Voltage

m A

133MHz Pull-up

133MHz Pull-down

I OH Min (133MHz)I OH Max (133MHz)

I OL Min (133MHz)I OL Max (133MHz)

SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM

Rev. 1.3 August 2004

V DD Clamp @ CLK, CKE, CS, DQM & DQ

V DD (V)I (mA)0.00.00.20.00.40.00.60.00.70.00.80.00.90.01.0 0.231.2 1.341.4 3.021.6 5.061.8 7.352.0 9.832.212.482.415.302.6

18.31

V SS Clamp @ CLK, CKE, CS, DQM & DQ

V SS (V)I (mA)-2.6-57.23-2.4-45.77-2.2-38.26-2.0-31.22-1.8-24.58-1.6-18.37-1.4-12.56-1.2 -7.57-1.0 -3.37-0.9 -1.75-0.8 -0.58-0.7 -0.05-0.6 0.0-0.4 0.0-0.2 0.0 0.0

0.0

2Voltage

m A

I (mA)

Voltage

m A

I (mA)

Minimum V DD clamp current

(Referenced to V DD )

Minimum V SS clamp current

0-10-20-30-40-30

-2-1-50-60

SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.3 August 2004

SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low)

Command

CKEn-1

CKEn

RAS

CAS

DQM

BA 0,1

A 10/AP

A 11,A 9 ~ A 0

Note

Mode register set H X L L L L X OP code

1,2Refresh

Auto refresh

H H L L L H X X 3Self refresh

Entry L 3Exit

L H L H H H X X

3H X X X 3Bank active & row addr.H X L L H H X V Row address Read &

column address Auto precharge disable H X L H L H X V L Column address 4Auto precharge enable H 4,5Write &

column address Auto precharge disable H X L H L L X V

L Column address

4Auto precharge enable

H 4,5Burst stop H

X L H H L X X 6

Precharge Bank selection H X L L H L X V L X

All banks

X H Clock suspend or active power down

Entry H L H X X X X X

L V V V Exit L H X X X X X Precharge power down mode

Entry

H L H X X X X

L H H H Exit

L H

H X X X X L V V V DQM

H X V X 7

No operation command

H X X X X

1. OP Code : Operand code

A 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.

If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Notes :