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MC13192中文资料

Freescale Semiconductor Technical Data

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

Document Number: MC13192

Rev. 2.9, 08/2005

MC13192/MC13193

Ordering Information

Device Device Marking

Package MC13192MC13193

1319213193

QFN-32QFN-32

1Introduction

The MC13192 and MC13193 are short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13192/MC13193 contain a complete 802.15.4 physical layer (PHY) modem designed for the IEEE ? 802.15.4 wireless standard which supports peer-to-peer, star, and mesh networking.

The MC13192 includes the 802.15.4 PHY/MAC for use with the HCS08 Family of MCUs. The MC13193 also includes the 802.15.4 PHY/MAC plus the ZigBee

Protocol Stack for use with the HCS08 Family of MCUs. With the exception of the addition of the ZigBee Protocol Stack, the MC13193 functionality is the same as the MC13192.

When combined with an appropriate microcontroller (MCU), the MC13192/MC13193 provide a

cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor

MC13192/MC13193

2.4 GHz Low Power Transceiver for the IEEE ? 802.15.4 Standard

Contents

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 34Data Transfer Modes . . . . . . . . . . . . . . . . . . . 35Electrical Characteristics . . . . . . . . . . . . . . . 86Functional Description . . . . . . . . . . . . . . . . 127Pin Connections . . . . . . . . . . . . . . . . . . . . . . 158Applications Information . . . . . . . . . . . . . . . 189

Packaging Information . . . . . . . . . . . . . . . . . 23

Features

can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBee? networking.

For more detailed information about MC13192/MC13192 operation, refer to the MC13192/MC13193 Reference Manual, part number MC13192RM.

Applications include, but are not limited to, the following:

?Remote control and wire replacement in industrial systems such as wireless sensor networks ?Factory automation and motor control

?Energy Management (lighting, HV AC, etc.)

?Asset tracking and monitoring

Potential consumer applications include:

?Home automation and control (lighting, thermostats, etc.)

?Human interface devices (keyboard, mice, etc.)

?Remote entertainment control

?Wireless toys

The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with

5.0 MHz channel spacing per the IEEE 802.15.4 specification. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control.

2Features

?Recommended power supply range: 2.0 to 3.4 V

?16 Channels

?0 dBm nominal, programmable from -27 dBm to 4 dBm typical maximum output power

?Buffered transmit and receive data packets for simplified use with low cost MCUs

?Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode (compatible with IEEE Standard 802.15.4)

?Three power down modes for power conservation:

—<1μA Off current

—1 μA Typical Hibernate current

—35 μA Typical Doze current (no CLKO)

?RX sensitivity of -92 dBm (typical) at 1.0% packet error rate

?Four internal timer comparators available to reduce MCU resource requirements

?Programmable frequency clock output for use by MCU

?Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration.

?Seven general purpose input/output (GPIO) signals

Block Diagrams

?Operating temperature range: -40 °C to 85 °C

?Small form factor QFN-32 Package

—RoHS compliant

—Meets moisture sensitivity level (MSL) 3

—260 °C peak reflow temperature

—Meets lead-free requirements

3Block Diagrams

Figure3 shows a simplified block diagram of the MC13192/MC13193 which is an IEEE Standard 802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY) specification. Figure4 shows the basic system block diagram for the MC13192/MC13193 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.

4Data Transfer Modes

The MC13192/MC13193 has two data transfer modes:

1.Packet Mode — Data is buffered in on-chip RAM

2.Streaming Mode — Data is processed word-by-word

The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary applications, packet mode can be used to conserve MCU resources.

4.1Packet Structure

Figure5 shows the packet structure of the MC13192/MC13193. Payloads of up to 125 bytes are supported. The MC13192/MC13193 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and appended to the end of the data.

Data Transfer Modes

4.2Receive Path Description

In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.

The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 μs period after the packet preamble and stored in RAM.

If the MC13192/MC13193 is in packet mode, the data is processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt.

If the MC13192/MC13193 is in streaming mode, the MCU is notified by an interrupt on a word-by-word basis.

Figure1 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above IEEE 802.15.4 Standard requirements. Figure2 shows energy detection/LQI reported level versus input power. Note that for both graphs the required IEEE

Figure

Data Transfer Modes

4.3Transmit Path Description

For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency.

If the MC13192/MC13193 is in packet mode, data is processed as an entire packet. The data is first loaded into the TX buffer. The MCU then requests that the MC13192/MC13193 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted.

In streaming mode, the data is fed to the MC13192/MC13193 on a word-by-word basis with an interrupt serving as a notification that the MC13192/MC13193 is ready for more data. This continues until the whole packet is transmitted.

Figure3. MC13192 Simplified Block Diagram

Data Transfer Modes

4 bytes 1 byte 1 byte12

5 bytes maximum 2 bytes

Preamble SFD FLI Payload Data FCS

Figure5. MC13192/MC13193 Packet Structure

Electrical Characteristics

5.1

Maximum Ratings

5.2Recommended Operating Conditions

Table 1. Absolute Maximum Ratings

Rating

Symbol Value Unit Power Supply Voltage V BATT, V DDINT

3.6Vdc RF Input Power P max 10dBm Junction Temperature T J 125°C Storage Temperature Range

T stg

-55 to 125

°C

Note:Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables.

Note:Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFIN± = 100 V MM,

PAO± = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF output pins have no ESD protection.

Table 2. Recommended Operating Conditions

Characteristic Symbol

Min Typ Max Unit Power Supply Voltage (V BATT = V DDINT )V BATT, V DDINT 2.0 2.7 3.4Vdc Input Frequency

f in 2.405- 2.480GHz Ambient Temperature Range T A -402585°C Logic Input Voltage Low V IL 0-30% V DDINT V Logic Input Voltage High V IH 70% V DDINT

-V DDINT V SPI Clock Rate f SPI --8.0MHz RF Input Power

P max --10

dBm

Crystal Reference Oscillator Frequency (±40 ppm over operating conditions to meet the 802.15.4 standard.)

f ref

16 MHz Only

Electrical Characteristics 5.3DC Electrical Characteristics

Table3. DC Electrical Characteristics

(V BATT, V DDINT = 2.7 V, T A = 25 °C, unless otherwise noted)

Characteristic Symbol Min Typ Max Unit Power Supply Current (V BATT + V DDINT)

Off

Hibernate

Doze (No CLKO)

Idle

Transmit Mode (0 dBm nominal output power) Receive Mode I leakage

I CCH

I CCD

I CCI

I CCT

I CCR

0.2

1.0

500

1.0

6.0

102

800

μA

Input Current (V IN = 0 V or V DDINT) (All digital inputs)I IN--±1μA Input Low Voltage (All digital inputs)V IL0-30%

V DDINT

Input High Voltage (all digital inputs)V IH70%

V DDINT

-V DDINT V

Output High Voltage (I OH = -1 mA) (All digital outputs)V OH80%

V DDINT

-V DDINT V

Output Low Voltage (I OL = 1 mA) (All digital outputs)V OL0-20%

V DDINT

Electrical Characteristics

5.4AC Electrical Characteristics

NOTE

All AC parameters measured with SPI Registers at default settings except where noted and the following registers over-programmed:Register 08 = 0xFFF7 and Register 11 = 0x20FF

Table 4. Receiver AC Electrical Characteristics

(V BATT , V DDINT = 2.7 V, T A = 25 °C, f ref = 16 MHz, unless otherwise noted.

Parameters measured at connector J6 of evaluation circuit.)

Characteristic Symbol

Min Typ Max Unit Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C)SENS per

--92-dBm Sensitivity for 1% Packet Error Rate (PER) (+25 °C)--92-87dBm Saturation (maximum input level)

SENS max

-10-dBm Channel Rejection for 1% PER (desired signal -82 dBm)

+5 MHz (adjacent channel)-5 MHz (adjacent channel)+10 MHz (alternate channel)-10 MHz (alternate channel)>= 15 MHz -----2531424149-----dB dB dB dB dB Frequency Error Tolerance --200kHz Symbol Rate Error Tolerance

--80

ppm

Table 5. Transmitter AC Electrical Characteristics

(V BATT , V DDINT = 2.7 V, T A = 25 °C, f ref = 16 MHz, unless otherwise noted.

Parameters measured at connector J5 of evaluation circuit.)

Characteristic Symbol

Min Typ Max Unit Power Spectral Density (-40 to +85 °C) Absolute limit --47-dBm

Power Spectral Density (-40 to +85 °C) Relative limit -

47-Nominal Output Power 11SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical).P out

-303

dBm Maximum Output Power 22

SPI Register 12 programmed to 0x00FC which sets output power to maximum.

dBm

Error Vector Magnitude

EVM -2035 %Output Power Control Range (-27 dBm to +4 dBm typical)-31-dB Over the Air Data Rate -250-kbps 2nd Harmonic --42-dBc 3rd Harmonic

-44

dBc

Electrical Characteristics

Figure6. Parameter Evaluation Circuit

Functional Description

6.1

MC13192/MC13193 Operational Modes

The MC13192/MC13193 has a number of operational modes that allow for low-current operation.

Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 6. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics.

6.2Serial Peripheral Interface (SPI)

The host microcontroller directs the MC13192/MC13193, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13192/MC13193 occurs as multiple 8-bit bursts on the SPI. The SPI signals are:

1.Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.

2.SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192/MC1319

3. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK.

NOTE

For Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0.

3.Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.

4.Master In/Slave Out (MISO) - The MC13192/MC13193 presents data to the master on the MISO output.

Table 6. MC13192/MC13193 Mode Definitions and Transition Times

Mode Definition

Transition Time To or From Idle Off All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including IRQ

25 ms to Idle Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained.

20 ms to Idle

Doze

Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator.

(300 + 1/CLKO) μs to Idle Idle Crystal Reference Oscillator On with CLKO output available. SPI active.Receive Crystal Reference Oscillator On. Receiver On.144 μs from Idle Transmit

Crystal Reference Oscillator On. Transmitter On.

144 μs from Idle

Functional Description A typical interconnection to a microcontroller is shown in Figure7.

Figure7. SPI Interface

Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLK core), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory.

6.2.1SPI Burst Operation

The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13192/MC13193 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure8.

Functional Description

6.2.2 SPI Transaction Operation

Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192/MC13193 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to the

MC13192/MC13193 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).Although the SPI bus is capable of sending data simultaneously between master and slave, the

MC13192/MC13193 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13192/MC13193 Reference Manual , part number MC13192RM for more details on SPI registers and transaction types.An example SPI read transaction with a 2-byte payload is shown in Figure 9.

Figure 9. SPI Read Transaction Diagram

Table 7. SPI Timing Specifications

Symbol Parameter

Min Typ

Max

Unit T0SPICLK period

125nS T1Pulse width, SPICLK low 62.5nS T2Pulse width, SPICLK high

62.5

nS T3Delay time, MISO data valid from falling SPICLK

15nS T4Setup time, CE low to rising SPICLK

15nS T5Delay time, MISO valid from CE low 15nS T6Setup time, MOSI valid to rising SPICLK 15nS T7

Hold time, MOSI valid from rising SPICLK

15nS

Pin Connections 7Pin Connections

Table8. Pin Function Description

Pin #Pin Name Type Description Functionality

1RFIN-RF Input LNA negative differential input.

2RFIN+RF Input LNA positive differential input.

3Not Used Tie to Ground.

4Not Used Tie to Ground.

5PAO+RF Output /DC

Input Power Amplifier Positive Output. Open drain. Connect to V DDA.

6PAO-RF Output/DC Input Power Amplifier Negative Output. Open

drain. Connect to V DDA.

7SM Test mode pin. Tie to Ground Tie to Ground for normal

operation

8GPIO41Digital Input/ Output General Purpose Input/Output 4.See Footnote 1

9GPIO31Digital Input/ Output General Purpose Input/Output 3.See Footnote 1

10GPIO21Digital Input/ Output General Purpose Input/Output 2. When

gpio_alt_en, Register 9, Bit 7 = 1, GPIO2

functions as a “CRC Valid” indicator.

See Footnote 1

11GPIO11Digital Input/ Output General Purpose Input/Output 1. When

gpio_alt_en, Register 9, Bit 7 = 1, GPIO1

functions as an “Out of Idle” indicator.

See Footnote 1

12RST Digital Input Active Low Reset. While held low, the IC is

in Off Mode and all internal information is

lost from RAM and SPI registers. When

high, IC goes to IDLE Mode, with SPI in

default state.

13RXTXEN Digital Input Active High. Low to high transition initiates

RX or TX sequence depending on SPI

setting. Should be taken high after SPI

programming to start RX or TX sequence

and should be held high through the

sequence. After sequence is complete,

return RXTXEN to low. When held low,

forces Idle Mode.

14ATTN Digital Input Active Low Attention. Transitions IC from

either Hibernate or Doze Modes to Idle.

15CLKO Digital Output Clock output to host MCU. Programmable

frequencies of:

16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5

kHz, 32.786+ kHz (default),

and 16.393+ kHz.

16SPICLK Digital Clock Input External clock input for the SPI interface.

Pin Connections

17MOSI Digital Input Master Out/Slave In. Dedicated SPI data input.

18MISO Digital Output Master In/Slave Out. Dedicated SPI data output.

19CE Digital Input Active Low Chip Enable. Enables SPI transfers.

IRQ

Digital Output

Active Low Interrupt Request.

Open drain device.

Programmable 40 k ? internal pull-up.

Interrupt can be serviced every 6 μs with <20 pF load.

Optional external pull-up must be >4 k ?.

21VDDD Power Output Digital regulated supply bypass.

Decouple to ground.22VDDINT Power Input

Digital interface supply & digital regulator input. Connect to Battery.

2.0 to

3.4 V. Decouple to ground.23GPIO51Digital Input/Output General Purpose Input/Output 5.See Footnote 1 24GPIO61Digital Input/Output General Purpose Input/Output 6.See Footnote 1 25GPIO71Digital Input/Output General Purpose Input/Output 7.See Footnote 1

26XTAL1Input Crystal Reference oscillator input.

Connect to 16 MHz crystal and load capacitor.

XTAL2

Input/Output

Crystal Reference oscillator output Note:Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13192/MC13193 Reference Manual for details.Connect to 16 MHz crystal and load capacitor.

28VDDLO2Power Input LO2 VDD supply. Connect to VDDA externally.

29VDDLO1Power Input LO1 VDD supply. Connect to VDDA externally.

30VDDVCO Power Output VCO regulated supply bypass.

Decouple to ground.

31VBATT Power Input Analog voltage regulators Input. Connect to Battery.

Decouple to ground.32

VDDA

Power Output

Analog regulated supply Output. Connect to directly VDDLO1 and VDDLO2 externally and to PAO± through a frequency trap.

Note : Do not use this pin to supply circuitry external to the chip.

Decouple to ground.EP

Ground

External paddle / flag ground.

Connect to ground.

The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state.

Table 8. Pin Function Description (continued)

Pin #Pin Name Type

Description

Functionality

Pin Connections

Figure10. Pin Connections (Top View)

Applications Information

8Applications Information

8.1Crystal Oscillator Reference Frequency

The IEEE 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13192/MC13193 transceiver provides onboard crystal trim capacitors to assist in meeting this performance.

The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them:

1.The initial (or make) tolerance of the crystal resonant frequency itself.

2.The variation of the crystal resonant frequency with temperature.

3.The variation of the crystal resonant frequency with time, also commonly known as aging.

4.The variation of the crystal resonant frequency with load capacitance, also commonly known as

pulling. This is affected by:

a)The external load capacitor values - initial tolerance and variation with temperature.

b)The internal trim capacitor values - initial tolerance and variation with temperature.

c)Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package

capacitance and stray board capacitance; and its initial tolerance and variation with

temperature.

Freescale has specified that a 16 MHz crystal with a <9 pF load capacitance is required. The

MC13192/MC13193 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13192/MC13193 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading.

In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps.

Initial tolerance for the internal trim capacitance is approximately ±15%.

Since the MC13192/MC13193 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a

board-by-board basis.

Applications Information A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the IEEE 802.15.4 specification.

8.2Design Example

Figure11 shows a basic application schematic for interfacing the MC13192/MC13193 with an MCU. Table9 lists the Bill of Materials (BOM).

The MC13192/MC13193 has differential RF inputs and outputs that are well suited to balanced printed wire antenna structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna, or other single-ended structures can be used with commercially available chip baluns or microstrip equivalents. PAO+ and PAO- require a DC connection to VDDA (the analog regulator output) through AC blocking elements. This is accomplished through the baluns in the referenced design.

The 16 MHz crystal should be mounted close to the MC13192/MC13193 because the crystal trim default assumes that the listed KDS Daishinku crystal (see Table10) and the 6.8 pF load capacitors shown are used. If a different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of 9 pF or less. A second crystal that has been evaluated and also gives acceptable performance is the Toyocom TSX-10A 16 MHZ TN4-26139 (see Table11).

VDDA is an analog regulator output used to supply only the onboard PA (PAO+ and PAO-) and VDDLO1 and VDDLO2 pins. VDDA should not be used to power devices external to the transceiver chip. Bypassing capacitors are critical and should be placed close to the device. Unused pins should be grounded as shown. The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line wakes up the MC13192/MC13193. RXTXEN is used to initiate receive, transmit or CCA/ED sequences under MCU control. RXTXEN must be controlled by an MCU GPIO with the connection shown. Device reset (RST) is controlled through a connection to an MCU GPIO.

When the MC13192/MC13193 is used in Stream Mode, as with 802.15.4 MAC/PHY software, the

MC13192/MC13193 GPIO1 functions as an “Out of Idle” indicator and GPIO2 functions as a “CRC Valid” / Clear Channel Assessment (CCA) result indicator and are not available for general purpose use.

元器件交易网https://www.wendangku.net/doc/4412771011.html,

Applications Information

Figure11. MC13192/MC13193 Configured With a MCU