用VHDL语言描述和实现乘法累加器设计
设计应完成的功能要求：
（1）乘法累加器的结构如下图所示，5位的被乘数X和5位的乘数Y输入后，暂存在寄存器5位的寄存器A和B中，寄存器A和B的输出首先相乘，得到10位乘积，该乘积通过选择信号sel的控制，可以和10位寄存器C的输出相加，相加结果保存在寄存器C中，实现乘法累加功能；也可以通过sel选择全零和乘积相加，实现乘法功能。寄存器C的输出也是系统输出Z。
：用VHDL语言描述和实现乘法累加器设计
（2）要求乘法器和加法器都采用电路描述，不采用算法描述。
（3）要求寄存器A,B,C具有异步清零功能，全部寄存器采用相同的时钟和清零信号。（4）设计的最终输出是设计报告。
设计报告的内容要求：
（1）设计报告的格式采用标准的深圳大学设计报告格式
（2）设计报告应包括该电路的总体结构图和主要功能模块组成图；
（3）设计报告应根据总体结构图，说明VHDL代码编写的设计思路和基本原理；
（4）设计报告应完成该电路的VHDL代码设计；
（5）设计报告应完成该电路的VHDL仿真分析。
一、实验目的
用VHDL语言描述和实现乘法累加器设计
二、实验内容及步骤
一．总体结构图
设计思路及原理：
首先，寄存器A、B、C具有异步清零功能，rest在clk之前调用，当复位信号rest为1时，寄存器A、B、C复位，当rest为0时，并且在它们同一时钟clk的上升沿到来时，输出将等于输入，起到了数据锁存功能。同时，寄存器的输出Z既是整个结果的输出，也可以被内部引用，因此在定义Z的端口时，把端口类型定义为buffer。
5位的被乘数X和5位的乘数Y输入后，暂存在寄存器5位的寄存器A和B中，通过寄存器A、B的寄存，能够让不同时到达的数据X和Y能够在同一时钟的控制下同时参与运算，寄存器A和B的输出分别为x_temp和y_temp，他们首先相乘，得到10位乘积mul，该乘积通过选择信号sel的控制，当sel为1时，acc=z，即乘积mul可以和10位寄存器C的输出相加，相加结果保存在寄存器C中，实现乘法累加功能；当sel为0时，acc为全零，即选择全零和乘积相加，实现乘法功能。寄存器C的输出也是系统输出Z。
二．功能模块图
1.加法器
2.乘法累加器RTL生成电路图
5bits并行乘法器设计原理和结构
a4 a3 a2 a1 a0
* b4 b3 b2 b1 b0
= a4b0 a3b0 a2b0 a1b0 a0b0
a4b1 a3b1 a2b1 a1b1 a0b1
a4b2 a3b2 a2b2 a1b2 a0b2
a4b3 a3b3 a2b3 a1b3 a0b3
a4b4 a3b4 a2b4 a1b4 a0b4
p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
通过老师的讲解，5bits并行乘法器是由乘法展开式转化成加法来实现的，比如p1 = a1b0+a0b1，p4 = a4b0+a3b1+a2b2+a1b3+a0b4.表达式中用到了与门电路和全加器，所以在全加器的时候有需要进位的地方。比如a1b0+a0b1如果产生了进位，则产生的进位向左边高位a2b0进位，作为a2b0+ a1b1的低位进位。再通过书上（P232）的例子，我们可以画出乘法器的结构图，写出乘法器的实验代码，如图所示与门结果为an，和为s，进位为c。
三．代码设计
--------------------------------乘法累加器-------------------------------------- --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:02:34 06/30/10
-- Design Name:
-- Module Name: mzc - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------- library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MAC is
port(x,y:in std_logic_vector(4 downto 0);
sel,rst,clk:in std_logic;
z:buffer std_logic_vector(9 downto 0));
end MAC;
architecture Behavioral of MAC is
signal x_temp,y_temp:std_logic_vector(4 downto 0);
signal z_out,acc,mul:std_logic_vector(9 downto 0);
component multiplier is
port(a,b:in std_logic_vector(4 downto 0);
prod:out std_logic_vector(9 downto 0));
end component;
component adder_10 is
port(a,b:in std_logic_vector(9 downto 0);
s:out std_logic_vector(9 downto 0));
end component;
begin
x_dff:process(rst,clk)
begin
if(rst = '1')then
x_temp <= "00000";
elsif(clk'event and clk = '1')then
x_temp <= x;
end if;
end process;
y_dff:process(rst,clk)
begin
if(rst = '1')then
y_temp <= "00000";
elsif(clk'event and clk = '1')then
y_temp <= y;
end if;
end process;
z_dff:process(rst,clk)
begin
if(rst = '1')then
z <= "0000000000";
elsif(clk'event and clk = '1')then
z <= z_out;
end if;
end process;
acc <= z when sel = '1'else
(others => '0');
U1:component multiplier port map (x_temp,y_temp,mul);
U2:component adder_10 port map (mul,acc,z_out);
end Behavioral;
------------------------------------------加法器------------------------------------------------ --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:04:21 06/30/10
-- Design Name:
-- Module Name: adder_10 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_10 is
port(a,b:in std_logic_vector(9 downto 0);
s:out std_logic_vector(9 downto 0));
end adder_10;
architecture Behavioral of adder_10 is
signal c:std_logic_vector(9 downto 0);
begin
c(0) <= '0';
U1:s(0) <= a(0) xor b(0) xor c(0);
c(1) <= (a(0) and b(0)) or (a(0) and c(0)) or (b(0) and c(0));
U2:s(1) <= a(1) xor b(1) xor c(1);
c(2) <= (a(1) and b(1)) or (a(1) and c(1)) or (b(1) and c(1));
U3:s(2) <= a(2) xor b(2) xor c(2);
c(3) <= (a(2) and b(2)) or (a(2) and c(2)) or (b(2) and c(2));
U4:s(3) <= a(3) xor b(3) xor c(3);
c(4) <= (a(3) and b(3)) or (a(3) and c(3)) or (b(3) and c(3));
U5:s(4) <= a(4) xor b(4) xor c(4);
c(5) <= (a(4) and b(4)) or (a(4) and c(4)) or (b(4) and c(4));
U6:s(5) <= a(5) xor b(5) xor c(5);
c(6) <= (a(5) and b(5)) or (a(5) and c(5)) or (b(5) and c(5));
U7:s(6) <= a(6) xor b(6) xor c(6);
c(7) <= (a(6) and b(6)) or (a(6) and c(6)) or (b(6) and c(6));
U8:s(7) <= a(7) xor b(7) xor c(7);
c(8) <= (a(7) and b(7)) or (a(7) and c(7)) or (b(7) and c(7));
U9:s(8) <= a(8) xor b(8) xor c(8);
c(9) <= (a(8) and b(8)) or (a(8) and c(8)) or (b(8) and c(8));
U10:s(9) <= a(9) xor b(9) xor c(9);
end Behavioral;
------------------------------------------------乘法器---------------------------------------------------------- --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:05:48 06/30/10
-- Design Name:
-- Module Name: multiplier - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------- library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier is
port(a,b:in std_logic_vector(4 downto 0);
prod:out std_logic_vector(9 downto 0));
end multiplier;
architecture Behavioral of multiplier is
signal s:std_logic_vector(19 downto 0);
signal c:std_logic_vector(23 downto 0);
signal an:std_logic_vector(15 downto 0);
begin
row1:
prod(0) <= a(0) and b(0);
c(0) <= '0';
c(1) <= '0';
c(2) <= '0';
c(3) <= '0';
s(0) <= a(0) and b(1);
s(1) <= a(0) and b(2);
s(2) <= a(0) and b(3);
s(3) <= a(0) and b(4);
row2:
an(0) <= a(1) and b(0);
an(1) <= a(1) and b(1);
an(2) <= a(1) and b(2);
an(3) <= a(1) and b(3);
s(7) <= a(1) and b(4);
prod(1) <= an(0) xor c(0) xor s(0);
c(4) <= (an(0) and c(0)) or (an(0) and s(0)) or (c(0) and s(0));
s(4) <= an(1) xor c(1) xor s(1);
c(5) <= (an(1) and c(1)) or (an(1) and s(1)) or (c(1) and s(1));
s(5) <= an(2) xor c(2) xor s(2);
c(6) <= (an(2) and c(2)) or (an(2) and s(2)) or (c(2) and s(2));
s(6) <= an(3) xor c(3) xor s(3);
c(7) <= (an(3) and c(3)) or (an(3) and s(3)) or (c(3) and s(3));
row3:
an(4) <= a(2) and b(0);
an(5) <= a(2) and b(1);
an(6) <= a(2) and b(2);
an(7) <= a(2) and b(3);
s(11) <= a(2) and b(4);
prod(2) <= an(4) xor c(4) xor s(4);
c(8) <= (an(4) and c(4)) or (an(4) and s(4)) or (c(4) and s(4));
s(8) <= an(5) xor c(5) xor s(5);
c(9) <= (an(5) and c(5)) or (an(5) and s(5)) or (c(5) and s(5));
s(9) <= an(6) xor c(6) xor s(6);
c(10) <= (an(6) and c(6)) or (an(6) and s(6)) or (c(6) and s(6));
s(10) <= an(7) xor c(7) xor s(7);
c(11) <= (an(7) and c(7)) or (an(7) and s(7)) or (c(7) and s(7));
row4:
an(8) <= a(3) and b(0);
an(9) <= a(3) and b(1);
an(10) <= a(3) and b(2);
an(11) <= a(3) and b(3);
s(15) <= a(3) and b(4);
prod(3) <= an(8) xor c(8) xor s(8);
c(12) <= (an(8) and c(8)) or (an(8) and s(8)) or (c(8) and s(8));
s(12) <= an(9) xor c(9) xor s(9);
c(13) <= (an(9) and c(9)) or (an(9) and s(9)) or (c(9) and s(9));
s(13) <= an(10) xor c(10) xor s(10);
c(14) <= (an(10) and c(10)) or (an(10) and s(10)) or (c(10) and s(10));
s(14) <= an(11) xor c(11) xor s(11);
c(15) <= (an(11) and c(11)) or (an(11) and s(11)) or (c(11) and s(11));
row5:
an(12) <= a(4) and b(0);
an(13) <= a(4) and b(1);
an(14) <= a(4) and b(2);
an(15) <= a(4) and b(3);
s(19) <= a(4) and b(4);
prod(4) <= an(12) xor c(12) xor s(12);
c(16) <= (an(12) and c(12)) or (an(12) and s(12)) or (c(12) and s(12));
s(16) <= an(13) xor c(13) xor s(13);
c(17) <= (an(13) and c(13)) or (an(13) and s(13)) or (c(13) and s(13));
s(17) <= an(14) xor c(14) xor s(14);
c(18) <= (an(14) and c(14)) or (an(14) and s(14)) or (c(14) and s(14));
s(18) <= an(15) xor c(15) xor s(15);
c(19) <= (an(15) and c(15)) or (an(15) and s(15)) or (c(15) and s(15));
row6:
c(20) <= '0';
prod(5) <= c(20) xor c(16) xor s(16);
c(21) <= (c(20) and c(16)) or (c(20) and s(16)) or (c(16) and s(16));
prod(6) <= c(21) xor c(17) xor s(17);
c(22) <= (c(21) and c(17)) or (c(21) and s(17)) or (c(17) and s(17));
prod(7) <= c(22) xor c(18) xor s(18);
c(23) <= (c(22) and c(18)) or (c(22) and s(18)) or (c(18) and s(18));
prod(8) <= c(23) xor c(19) xor s(19);
prod(9) <= (c(23) and c(19)) or (c(23) and s(19)) or (c(19) and s(19));
end Behavioral;
四．仿真波形
1.加法器
仿真波形分析：
a和b为10bits输入，s为10bits输出。正如图中所示，当a=0，b=1时，s=1；
当a=3，b=2时，s=5。可以实现10bits加法功能，所以本次编写的10bits逐级进位加法器的VHDL 代码是正确的.
2.乘法器
仿真波形分析：
a和b为5bits输入，prod为5bits输出。如图中仿真波形，当a=0，b=31时，prod=0，而当a=4,b=27时， prod=108，所以本次编写的5bits并行乘法器的VHDL代码是正确的.
3.乘法累加器