Shared Memory Multiprocessor Architectures for

Shared Memory Multiprocessor Architectures

for Software IP Routers

Yan Luo,Laxmi Narayan Bhuyan,Fellow,IEEE,and Xi Chen

The authors are with Computer Science and Engineering,University of California,Riverside,CA92521. {yluo,bhuyan,xichen}@https://www.wendangku.net/doc/4515004570.html,

This research has been supported in part by NSF grant CCR-0105676and CCR-0196102.

Abstract

In this paper,we propose new shared memory multiprocessor architectures and evaluate their performance for future Internet Protocol(IP)routers based on Symmetric Multi-Processor(SMP)and

Cache Coherent Non-Uniform Memory Access(CC-NUMA)paradigms.We also propose a bench-

mark application suite,RouterBench,which consists of four categories of applications representing key

functions on the time-critical path of packet processing in routers.An execution driven simulation

environment is created to evaluate SMP and CC-NUMA router architectures using this RouterBench.

The execution driven simulation can produce accurate cycle-level execution time prediction and reveal

the impact of various architectural parameters on the performance of routers.We ported the FUNET

trace and its routing table for use in our experiments.We?nd that the CC-NUMA architecture provides

an excellent scalability for design of high performance IP routers.Results also show that the CC-NUMA

architecture can sustain good lookup performance even at a high frequency of route updates.

Index Terms

Multiprocessor Architecture,Shared Memory,IP Router,Network Applications,Route Updates.

I.I NTRODUCTION

As link speed continues to grow exponentially,packet processing at network switches and routers is becoming a bottleneck.Assuming an average packet size of1000bits,a multi-gigabit router has to process several million packets per second.This implies that the average packet processing time has to be less than one microsecond,which is impossible for a single processor to achieve.

Different approaches are proposed and deployed to improve the performance of Internet Proto-col(IP)routers,whose performance metric has been mainly the throughput or packets per second. Application Speci?c Integrated Circuits(ASICs)are usually preferred in high-end core routers due to their high performance while tolerating their in?exibility and lack of programmability. The emerging network processors provide programmability and?exibility together with high performance,but are usually targeted to edge routers.Therefore,general purpose multiprocessors are preferred for high-end core routers because of their high performance,programmability and scalability[7],[27].Packet processing in these core routers is accomplished through software, hence they are called software IP routers.

Modern commercial routers such as BBN Multi-Gigabit Router[27]and Cisco12000Series

Gigabit Switch Router[7]employ multiprocessors to process packets.BBN’s MGR[27]incor-

porates a number of centralized Forwarding Engines(FEs)that are reponsible for processing

packets coming from the line cards(LCs).LCs are network interfaces where packets arrive and

depart.Cisco12000series multi-gigabit routers[7]adopt a distributed architecture,in which

each LC has a dedicated FE associated with it.As these commercial routers are deployed,some

questions arise for both industrial and academic community.Among them,the following two

questions are addressed in this paper:

?How to evaluate the software packet processing capability of a multiprocessor router archi-tecture?

?What types of multiprocessor architectures yield the best performance for core routers? The aim of this paper is to evaluate different multiprocessor architectures for software routers,

and to develop techniques to improve performance.Execution time or packet processing latency

in a router is considered as the main performance metric in this paper instead of throughput.Thus

we employ execution driven simulation to predict the performance of IP routers.The advantage

of execution driven simulation is that it can produce accurate cycle level execution time and

reveal the impact of architectural parameters on router performance.We extend Augmint[22]

to perform multiprocessor architecture simulation.We choose Augmint because it runs fast due

to its simple processor architecture model,and it enables us to focus on exploring parallelism at

the packet level.The impact of packet-level parallelism on the router performance is known to

be more profound compared to architectural extensions like instruction-level parallelism(ILP),

branch prediction or speculation[4].

In order to evaluate the router architectures,we propose a benchmark called RouterBench,

which consists of four categories of applications that reside on the time-critical path of packet

processing in a core router.Our benchmark applications are similar to those of the Click

router[16].We quantitatively analyze the computation requirements of the key functions in

RouterBench,and evaluate their execution time on the shared memory multiprocessor router

architectures.

Route updates may happen frequently due to IGP,BGP[28]or other routing protocols.The

routing update messages cause changes to the routing table structures,stall the route lookup

procedure,and degrade the lookup performance.Hence,we also study the impact of such route

updates on the lookup time of multiprocessor routers.

In both BBN’s MGR[27]and Cisco’s12000series routers[7],the common data structure, such as routing table,is replicated in all the processors resulting in a wastage of memory. Also,updating multiple copies of a large data structure is time consuming and needs special hardware support.Shared memory architectures enable multiple processors to share one copy of data structure,e.g.routing table,which not only saves memory space,but also eases updating. The scalability and high performance of shared memory multiprocessor architectures make them salient candidates for router architectures.Hence,we propose to design and test two shared memory architectures in this paper.

The contribution of this paper is the following:

?We propose two shared memory multiprocessor architectures for IP routers based on SMP and CC-NUMA organizations.

?We construct an execution driven multiprocessor simulation framework for evaluating these router architectures consisting of forwarding engines(FEs),line cards(LCs)and a switching fabric.

?We develop a set of benchmark applications that reside on the critical path of packet pro-cessing in the routers.This RouterBench is used to evaluate the multiprocessor architectures under study.

?We study the impact of route updates on the performance of routing table lookup in a multiprocessor router architecture.

This paper is organized as follows.The related research is presented in Section II.We describe the SMP and CC-NUMA router architectures,and introduce a simulation framework in Section III.In section IV,we identify the key functions that a router performs for processing a packet,and propose RouterBench,which is used in the simulation study of multiprocessor router architectures.The simulation results are presented in Section V.In Section VI,we study the impact of route updates on the routing table lookup performance of the CC-NUMA based router.Finally,Section VII concludes the paper.

II.R ELATED W ORK

Wolf and Turner proposed the design of a scalable,high-performance active router[34],where multiple network processors with cache and memory on a single application speci?c integrated

circuit(ASIC)were used.However,a general purpose multiprocessor architecture has advantages over ASIC or specialized processor because it avoids long development process,incurs less design cost,and is programmable.In addition,general purpose processors usually have on-chip caches, which can store frequently-used data structures locally.Hence,BBN MGR[27]is based on DEC Alpha21164general purpose processors.

The performance evaluation of a router should be carried out with appropriate benchmark applications.There exist a few network benchmarks for network processor design and evaluation like CommBench[32],NetBench[18]and PNI benchmark[9],https://www.wendangku.net/doc/4515004570.html,mBench includes a set of header processing applications in traditional networks and payload processing applications in active https://www.wendangku.net/doc/4515004570.html,Bench contains micro-level,packet-level and application-level benchmarks. PNI benchmark covers packet header applications such as packet classi?cation and fowarding, and packet data processing applications such as IPSec.Although these benchmarks cover various applications in the network realm,none of them speci?cally addresses all the workload in an IP router.RFC1812is the classic document that states the requirements of IP Version4routers [2].Karlin et al.[15]summarized the main functions of routers as classi?cation,fowarding and scheduling.Kohler et al.[16]built a functional software router-Click Modular Router where the key functions of an IP router are implemented.

Most of the work in performance evaluation of routers emphasizes the delay in packet trans-mission,and ignores the packet processing latency.Chan et al.presented a modeling framework to optimize the cost and performance of routers with multiple forwarding engines[5].They assumed that route lookup time was exponentially distributed,which did not reveal the real packet processing delay.Papagiannaki et al.[26]measured the single-hop delay from an operational backbone network router,but did not specify the processor computation time,queuing delay,and other contributions to the total delay.Chen et al.[6]studied the buffer and queue management techniques to optimize the Click software router[16]on off-the-shelf multiprocesor PC hardware. In both[6]and[26],the implementations are based on existing hardware,which lack study on investigating the impact of various architecture parameters(such as CPU power,memory size), and on tuning these parameters to optimize the router performance.

Bhuyan et al.[4]were the?rst to measure the packet processing time and architectural impact through an execution driven simulation.They extended the RSIM[25]simulator to evaluate the execution of a routing table lookup algorithm on a multiprocessor router.In this paper,

we further extend the previous research[4]to a complete simulation framework and router workload.We extend Augmint[22]to perform multiprocessor architecture simulation because RSIM spends too much simulation time on architectural detail inside the CPU,such as instruction level parallelism(ILP),branch prediction,speculative execution,etc.It was shown that the impact of these parameters is not that signi?cant compared to multiprocessing[4].Augmint assumes simple processor architectures,but enables us to focus on exploring packet-level parallelism.

III.M ULTIPROCESSOR A RCHITECTURE FOR R OUTERS

A.Existing Multiprocessor Router Architectures

Packet Movement Path

(a)

(b)

(c)

FE: Forwarding Engine

RP: Route Processor

LC: Line Card

Fig.1.Router Architectures.(a)multiple FEs and LCs with shared bus,(b)paralle router architecture with separate LCs and FEs,(c)distributed router architecture with combined LC and FE.

A basic router architecture consists of line cards,a router processor and a backplane switch. Current trend in the router designs is to use multiple packet processing units instead of a single centralized one.High-performance routers can be divided into three organizations shown in Fig.1.The architecture of Fig.1(a)connects multiple FEs and LCs via a high-speed bus.Packet headers can be sent to one of the FEs from an LC to perform route lookup,packet classi?cation and header updates,etc.Such a router is inexpensive in cost,however,since the LCs forward packets to outbound LCs via bus also,the bus could be a bottleneck.The multiprocessor Click

router in[6]is based on such an architecture.A parallel architecture in Fig.1(b)replaces the shared bus with a switching fabric connecting all FEs and LCs.Moreover,a separate Route Processor is incorporated to run Internet routing protocols(such as BGP),accounting and other administrative tasks,which are not time-critical to packet processing.The FEs are responsible for routing table lookup,packet classi?cation and packet header updates,which are time-critical operations.BBN’s Multi-Gigabit Router[27]architecture conforms to Fig.1(b).Fig.1(c)depicts a distributed architecture,where each LC has an FE locally,and all router tasks such as routing table lookup are completed in the local FE.An example of such an architecture is Cisco12000 series multi-gigabit router,in which each LC has a dedicated layer three forwarding engine. There are two additional decisions to be made when designing a high performance multipro-cessor router.The?rst one is the programmability.A programmable architecture has increasing advantages over ASICs because new protocols and router functions can be incorporated.So we consider general-purpose processors as forwarding engines.The second one is the memory usage. The routers can either have all data structures replicated for each processing element,or have a shared data structure.The obvious bene?t of the replicated one is the simultaneous memory access by all the FEs.However,as size of the data structures(such as tree structure for routing table lookup)grows and number of processing elements increases,the memory requirement may easily exceed beyond limit.For example,Cisco12000one-port10-Gigabit Ethernet Line Card has256MB routing table memory[8],which turns out to be4GB for a router with only16LCs. Another drawback of replicated data structures is the dif?culty to update them.For example, whenever there is an update on the routing table,every copy of the data structure for routing table lookup will need to be updated simultaneously.This will increase the hardware complexity or degrade the performance signi?cantly if done sequentially.So a shared memory architecture seems to be a good candidate.A distributed shared memory(DSM)organization can be adopted to provide simultaneous memory access from different processors.This is possible because different processors will access different parts of the shared data structure at any particular time. Shared memory architectures can be divided into two categories,namely,Symmetric Multi-Processors(SMP)and Cache-Coherent Non-Uniform Memory Access(CC-NUMA)multipro-cessors.Their organizations are brie?y described later in this section.In shared memory archi-tectures,a global memory space is shared by all the processors in the system.Each processor has a local cache,which can store recently accessed shared data blocks.In order to study the sharing

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behavior in routers,we executed Radix Tree Routing(RTR)[31]table lookup algorithm on a simulated SMP architecture with 32processors.RTR is a classic route table lookup algorithm for layer three (IP)packet forwarding in routers,which performs route lookup based on a radix tree data structure.We used publicly available FUNET trace and its routing table [24]in this experiment.

Fig.2illustrates the sharing behavior of RTR,where x-axis denotes the number of processors sharing a certain data block,and y-axis is the number of data blocks that x processors share.It can be observed that,the number of data blocks shared by all processors is very high,which means that the degree of sharing in RTR lookup is substantial.These highly shared blocks are actually radix tree root node and its near descendants.They are shared most frequently because every lookup has to begin from these nodes located at the top of the radix tree.As RTR lookup traverses the tree,route lookup on packets with same destination IP address will follow the same path until the lookup ?nishes whereas other lookups may branch to different ways after some point.A continuous stream of packets with same destination IP will be seen in the packet stream because two communicating parties will maintain a connection and send data packets for a period of time.However,these packets may be sent to different FEs for processing.The corresponding FEs will follow the same path on the radix tree,and thus the tree nodes along the path will

CPU

Cache FE

CPU Cache FE CPU Cache

FE LC LC LC LC . . . . . .Centralized Main Memory

Fig.3.SMP Router Architecture

be shared by these FEs.This interesting observation motivates us to propose multiprocessor architectures with shared memory for IP routers.We examine the suitability of both SMP and CC-NUMA multiprocessor architectures in the following sections.

B.SMP Based IP Router

In SMP router architectures,the FEs and LCs are connected through a high speed bus.The centralized shared memory module is also attached to the bus as depicted in Fig.3.This architecture is same as the multiprocessor Click router [6].

An SMP-based router architecture has the following features:

?Each FE has cache memory of one or multiple levels.The SMP router architecture uses uni-form/centralized shared memory,and broadcast/bus-based snoopy cache coherence protocol

[3],[13].

?Centralized shared memory stores routing table and other data structures,which are shared by all the FEs.

?An LC has an on-card memory buffer,where incoming packets (both header and payload)are stored.

?An FE accesses these memory spaces using memory mapped I/O operation,processes the packet header,and writes the port number of the outbound LC into the packet header.

?

LCs transfer the packets to outbound LCs via the same shared bus.The FEs perform header checking,classi?cation,routing table lookup etc.Routing table lookup

LC LC LC LC

Cache

CPU

Memory FE

Cache CPU Memory FE Cache CPU Memory FE Interconnection (Crossbar Switch)

............Distributed Shared

Memory

https://www.wendangku.net/doc/4515004570.html,-NUMA Router Architecture.

process involves loading radix tree nodes from centralized main memory to cache,upon which RTR algorithm is performed.The lookup result and updated packet header are written back (again via bus)to the origin LC.Intuitively the potential problem could be the bottleneck of the centralized memory and bandwidth limit of the bus.The FEs have to compete for the bus to access shared data structures in centralized main memory,and the LCs compete for the bus to transfer packets consisting of both headers and payloads.

https://www.wendangku.net/doc/4515004570.html,-NUMA Based IP Router

The architecture shown in Fig.1(b)avoids the bus problem by putting a crossbar network between the LCs and FEs.A crossbar switch allows all one-to-one connections between the LCs and FEs.Although BBN’s MGR has an organization similar to Fig.1(b),the memory of FEs is not shared,so the routing table is replicated in all the FEs.We propose a CC-NUMA architecture to eliminate the replication by using a shared memory paradigm.

A Cache Coherent Non-Uniform Memory Access (CC-NUMA)router architecture,shown in Fig.4,has the following features.

?Each FE has cache memory that can be of multiple levels.The cache coherence is maintained through a directory-based organization [3],[13].It also has a local memory module,which is part of the global shared memory space.

?Each LC has an on-card memory buffer,which stores the packet (both header and payload).

An FE can access any memory remotely via crossbar.Ideally,an FE should be located at the LC,as considered in[4].However,we chose the organization in Fig.4similar to the BBN’s MGR.

?All FEs and LCs are connected via a crossbar switch fabric,which allows simultaneous multiple connections for high bandwidth.

A CC-NUMA router works as follows.Each FE gets a new packet header from an LC, performs header checking,classi?cation,and routing table lookup etc.Routing table lookup involves loading radix tree nodes from distributed memory to local cache.The packet header is updated using the lookup result,and it is written back to the origined LC.The LCs then initiate packet transfers via the crossbar.

D.Multiprocessor Router Architecture Simulation

To evaluate the performance of the above router architectures,we develop an execution-driven simulator.Augmint[22]is initially a simulation tool for Intel CISC processors,only simulating the instruction execution on the processor side.Its processor simulation is relatively simple, however,it enables us to focus on the multiprocessing of packets.Augmint provides us the ?exibility to add memory module and bus/crossbar module for SMP/CC-NUMA architecture in the backend.We construct a cache memory module with32-byte cache blocks and32KB cache size.It is two-way set-associative,and the cache replacement policy is LRU.We extended Augmint to implement a snoopy cache coherence protocol for SMP and a full-map directory-based protocol for CC-NUMA architecture[3],[13].Memory management policy in CC-NUMA is page-based round robin,so the radix tree data structure is distributed uniformly across the memory modules.We simulate FEs and LCs as independent components as in a real router,and they interact through the interconnection(bus or crossbar switch).

IV.R OUTER B ENCH

To evaluate router architecture performance with appropriate benchmark applications,we need to identify the key functions of routers.RFC1812[2],“Requirements for IP Version4Routers”, states that“an IP router can be distinguished from other sorts of packet switching devices in that a router examines the IP protocol header as part of the switching process.”

updated header

Fig.5.Packet processing?ow.

The processing of IP layer involves IP header validation,routing table lookup,decrementing time-to-live(TTL),fragmentation etc[2],[16],[15].Pro?ling on an example Click sofware router[16]also shows that these tasks take considerable amount of time to execute:header validation,classi?cation and decrementing TTL take12.3%,9.2%and3%of the total execution time,respectively.In addition,packet classi?cation is becoming a mandatory task to support QoS in routers[14].In general,each packet header will go through the processing shown in Fig.5.To capture these key router functions,we propose RouterBench,which consists of the following four categories of applications.

?Classi?cation

?Forwarding

?Queuing

?Miscellaneous

These operations reside on the critical path of the passing packets,which are time-critical,and are key factors of the router overall performance.Therefore we believe that the RouterBench speci?cally identi?es the workload of IP routers and is suitable for evaluating their performance. At this stage,we do not consider other non-time-critical functionalities,such as BGP routing,

logging,and administrative tasks.

The source codes of the RouterBench applications are available for public download at[17].

A.Classi?cation

Packet classi?cation is the primary task for identifying?ows,?ltering data traf?c,QoS[14], etc.Packets can themselves carry an explicit service classi?cation?eld,such as Type of Service (TOS)in IP header[1],[23].A general classi?cation is done with an access list that allows speci?cation of a packet’s source and destination address,protocol,and the protocol port address for TCP or UDP.In some systems such as Click[16],a more generic con?guration mechanism allows any?eld of the packet header to be identi?ed using speci?cation of an offset and a?eld length.

We take the general classi?cation mechanism as our benchmark application,which uses a rule list and can check any?eld of the packet header.In theory there can be unlimited number of rules in a rule list.Since there is no typical rule list described in the literature,we list a set of rules that a typical router would con?gure based on an access list from a campus level router. There are totally336rules declared for the inbound traf?c.An example of a rule is“dst host 138.23.168.40and tcp port80”,which classi?es all the incoming HTTP packets destinated to a server with IP address of138.23.168.40.Figure6shows the cumulative distribution function (CDF)of packet counts on top rules based on the data in our campus level router.The x-axis is the rank of a rule,and y-axis is the cumulative distribution of traf?c that are matched.we ?nd that only31rules out of336of them classi?ed99%of the traf?c,and many of the rules were never encountered by any packet.We thus use the top31rules in our classi?er application. Our classi?cation algorithm,ported from Click router[16],is based on the“hierachical trie”algorithm described in[11].

Hierachical trie structure is an extension of the trie data structures.A trie structure is con-structed by examining one?eld(for example,“source IP”?eld)of the classi?cation rules such that the trie consists of all the different values in this?eld.Each trie node contains an{offset, pre?x,mask}tuple to represent the value in the?eld.Offset speci?es the bits to be examined. Those bits are ANDed with mask and then compared with pre?x to deterimine if there is a match or not.The left and right children of a node can be either another trie node or a leaf node,which indicates that the?nal classi?cation decision can be made here.Then,the hierachical

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cumulative distribution Fig.6.Cumulative distribution of traf?c matched on top rules.

trie is constructed by connecting all the tries based on the rule list.Classi?cation of an incoming packet proceeds from the root node,determines if the packet matches at each node until it reaches a leaf node (decision node).

B.Forwarding

Forwarding packets to their destination hosts is the primary task of a router.To forward a packet,a router has to lookup a route table to determine its outgoing port.A route table lookup algorithm is used to search for a most speci?c route pre?x.Because of Classless InterDomain Routing (CIDR)forwarding becomes a non-trivial problem,and quite a few routing algorithms have been proposed in the literature [29].Among them the Radix Tree Routing (RTR)route lookup algorithm is from the public domain BSD Unix [21]distribution that performs lookup based on a radix tree data structure.It is widely used,and included in both CommBench [32]and NetBench [18].We thus incorporate it as our benchmark for forwarding.

In the RTR algorithm,a route lookup is performed based on the radix tree and starts from the root node.Each tree node (radix node)indicates which bit of the 32-bit destination IP address should be examined.The value of that bit (1or 0)determines which of the children nodes will be the next one to visit.When a leaf node is reached,the destination IP is ANDed with the

route pre?x mask to verify the?nal match.Backtracking is possible if there is not a match in the leaf node.

C.Queuing

Queuing may happen at both the input side and output side of a router.Different queuing policies are proposed to control congestion,guarantee fair sharing of bandwidth,and provide QoS[30],[10],[14].There are two categories of queuing policies:scheduling and dropping. Scheduling policy decides how a number of packet sources,usually queues,can share a single output channel.Dropping policy drops packets when the queue size is beyond certain threshold. We use the following two algorithms in our RouterBench.

1)DRR(De?cit Round Robin):DRR is a De?cit Round Robin fair schedulig algorithm[30] that is commonly used for bandwidth scheduling on network links.DRR assigns a quantum to each queue and serves the queues in a round robin fashion.A queue cannot send a packet if the packet size is larger than the quantum.After a packet is sent,its size is subtracted from the quantum.The reminder of the quantum is added to the quantum for the next round so that the large packet gets a chance to be sent out later.DRR algorithm is implemented in one form or another in currently available routers(e.g.Cisco12000series).

2)RED(Random Early Detection):RED is used to drop packets when there is network congestion.A link is considered congested when there are too many packets in the queue serving that link.RED monitors the average queue size of each output queue.Congestion in the link increases the average size of the queues.If the average size of a queue exceeds the maximum threshold,RED drops a packet with a probability that is proportional to the connection’s share of the throughput,and noti?es the sender about this congestion.RED is?rst proposed by Floyd and Jacobson in[10],and later implemented on various platforms.UCLADew[35]is one of the implementations of RED,and we port it to build our RED benchmark application.

DRR and RED are usually performed on LC instead of FE because FEs are responsible for processing packet headers,while LCs are responsible for queuing management.However,future high performance routers are likely to implement the QoS activities in the FE.Also,when an FE is physically located in an LC,like in Cisco12000routers[7],it has to perform QoS activities.

D.Miscellaneous

There are some other tasks that are executed in the critical path of processing a packet; however,it is not appropriate to put them into the above categories.These functions are included in both BBN MGR and Click router con?gurations.We run pro?ling tool on a Click software router and identify that these functions are consuming a non-negligible amount of time.This miscellaneous category consists of CheckIPHeader,DecTTL and Fragmentation.

1)CheckIPHeader:

?CheckIPHeader veri?es the validity of an IP packet.

?It checks if the packet’s length is reasonable,and that the IP version,header length,packet length,and checksum?elds are valid.

?It also checks if the IP source address is a legal unicast address–the address should not be0.0.0.0or255.255.255.255,or local broadcast addresses as the administrator de?nes.

2)DecTTL:

?DecTTL updates the time-to-live(TTL)?eld of a packet.TTL is used to track the lifetime of a packet in the Internet;a packet should not travel in the Internet for ever in the presence of network routing errors.

?If the TTL value is≤1(i.e.time-to-live has expired),DecIPTTL generates and sends back an Internet Control Message Protocol(ICMP)error noti?cation packet to the sender.

Otherwise it decrements the TTL,and recalculates the checksum.

3)Fragmentation:

?Fragmentation fragments packets to small ones when they are transfered to a network with smaller Maximal Transfer Unit(MTU).Link layer MTU of physical network,connected to the router,determines the size of fragments.For example,a typical MTU is576bytes for the X.25network[19].

?It also recalculates checksum based on new size,and updates the header.

V.S IMULATION R ESULTS AND A NALYSIS

It is desirable to conduct performance evaluation based on real routing table from a backbone router with real packet trace from the same site.The only routing table and trace pair that is publicly available is from FUNET[24].The trace includes near-real IP addresses(the last8

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C y c l e s ChkIPH Classifier RTR DecIPTTL Frag RE

D DRR

Average Processing Time Per Packet Fig.7.Processing time distribution in packet processing path.

bits of an IP are masked to 0),and is acceptable for evaluating the RTR lookup because most route pre?xes are less than 24bits.The FUNET routing table has 41K entries,and the trace ?le contains 100K destination IP addresses.The other functions,such as CheckIPheader,Classi?er,DecTTL and Fragmentation,need other IP header ?elds besides the destination IP.However,FUNET traces do not contain such information.Therefore we use traces from NLANR [20]because they have a full packet header up to TCP layer.On the other hand,NLANR traces have sanitized IP addresses that make them unsuitable for routing table lookup.

A.RouterBench Applications Performance

Fig.7depicts the per-packet execution time of each RouterBench application in a uniprocessor environment,where the processor has one level cache.The cache has 32-byte cache block,32KB cache size and is two-way set-associative.Cache latency and memory access latency are assumed to be 2cycles and 30cycles,respectively.The experimental results show that classi?cation and routing table lookup take up to 56%of the total processing time (2186cycles).CheckIPHeader,DecIPTTL,Fragmentation,RED and DRR share the rest 44%.Classi?cation and route table lookup have comparable execution time complexity.RTR route table lookup takes most of the time,617cycles per packet,and DecIPTTL takes the least,51cycles.The total processing time

for a packet(excluding queuing time)is2186cycles.Assuming memory access cycles do not change with increase in CPU frequency,the above result corresponds to a maximal throughput of 91.5K packets/sec with a200MHz CPU or457K packets/sec with a1GHz CPU.In reality,as we move to faster CPUs,the number of cycles for each memory access will increase proportionately. As a result,the packet processing time will increase and throughput will decrease.In any event,the throughput obtained in a uniprocessor is far below the multi-gigabit link requirement (multi-million packets/sec),and justi?es the need for a multiprocessor architecture in routers. Hence,in the following subsections,we show how multiprocessor architectures can improve the performance of packet header processing applications.

B.Multiprocessor Router Architecture Performance

We individually run each benchmark application on the SMP and CC-NUMA architectures of our execution-driven simulator to get various performance measurements.Table I summarizes default parameters of our architectures.We adopt packet-level parallel processing in the sense that when a packet arrives at a line card,it is sent to a forwarding engine for processing in a round-robin manner.However,they all share the same shared memory.

TABLE I

A RCHITECTURAL P ARAMETERS

SMP CC-NUMA

Cache Size32KB32KB

Cache Block Size32B32B

Cache Associativity2-way2-way

Cache Replacement LRU LRU

Cache Latency2cycles2cycles

Local Memory Access La-

-30cycles

tency

Bus Transaction Time50cycles-

Switch Transaction Time-50cycles

1)SMP Performance:Figure8plots the execution time of various RouterBench applications on an SMP architecture.Except for RTR,the execution time of all other applications in Router-

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C y c l e s no. of processors 12481632

checkipheader classifier rtr decipttl frag Fig.8.RouterBench speedup on SMP architecture.

Bench decreases almost by half as the number of processors doubles.RTR lookup gets speed up until eight processors,after which its execution time increases.

In order to understand the cause of RTR performance trend on SMP,we further break down the RTR lookup execution time in Fig.9.The computation time decreases up to 50%when the number of processors doubles,so does the memory stall time.Memory stall time is the time taken at the centralized memory of Fig.3.The bus contention time is considered separately,which increases with the number of processors.This is because the radix tree is located in the centralized memory and every processor has to request and load the radix tree data structure via the bus when a cache miss occurs.Bus contention becomes the bottleneck in performance,which leads to the increase of total execution time after a certain number of processors.

Fig.10illustrates cache behavior of the RTR lookup algorithm on SMP.There are few write misses since we are not simulating the route update procedure of the radix tree structure.The read misses come from the fact that radix tree structure is allocated in the shared memory,and every processor has to traverse the tree structure to perform lookup.When a processor traverses a node in the tree for the ?rst time,a cache miss occurs.The next visit to the same tree node will usually be a cache hit.The cache miss ratio is relatively low (between 3%and 4.5%)because the

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RTR lookup time detail on SMP Architecture 12481632

average bus contention

Memory stall time computation

Fig.9.RTR lookup time detail on SMP architecture.

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RTR lookup Cache Behavior on SMP Architecture

12481632

read miss ratio

Fig.10.Cache behavior of RTR lookup on SMP architecture.

日落即景五年级作文范文3篇

日落即景五年级作文范文3篇 导语：渐渐的，夕阳收敛起他最后的光芒，还来不及说一声再见，便垂下头去，合上了双眼，静静地睡去了。下面是小编为大家整理的日落即景五年级作文范文，仅供参考，欢迎大家阅读。 日落即景五年级作文范文一“夕阳无限好，只是近黄昏。”日出金光万丈的壮丽景色固然美，但那迟暮的落日，却也有着独特的韵味。 傍晚，太阳收敛了刺眼的光芒，倚靠着西山，像一位老者一样缓缓下移，而在它的四周，那团团绚丽多彩的火烧云，毫不吝啬地向万物释放着自己的美丽。它们带着一抹微笑，挥舞着手中那若隐若现的纱巾，为这片天地增光添彩。淡黄、浅红、淡紫，各种淡雅的色彩在它身上渲染着，却又显得这么和谐。 过了一会儿，太阳渐渐西斜，只剩下了半边脸，在山体的遮掩下，如同一位“犹抱琵琶半遮面”的女子，腼腆而又神秘。虽然“少”了半张脸，但太阳的热情依然无限，风采仍然不减。它慷慨地舞动衣袖，将那昏黄的阳光洒到每一处可以看见的地方。仿佛一位老画家在为大地填涂上落日前的最后一丝色彩。一行大雁排着“人”字从空中掠过，在日光的衬托

下，如同下凡的金色神鸟。 不久后，略显昏暗的天幕已没有了落日的轮廓，可那最后一丝余晖却仿佛不甘就此落幕。它披着一件“霞光裙”，还在这个落日舞台上进行最后的谢幕表演。它将云朵的一边染得金黄，又沿着山体勾勒出一条曲折有致的金线。直到月亮散发着清冷的光芒升起，余晖还是意犹未尽，最后被一群调皮的星星撵下了台…… 或许，夕阳并不是最迷人的，但在我的眼里，它是最独特的。 日落即景五年级作文范文二俗话说：十月的天碗里转，说黑就黑，还不到五点，太阳就要回家看它和月亮的孩子去了。 此时的太阳想立刻回家，它渐渐接近西方的群山。它那圆圆的脸庞，像极了一位慈祥和蔼的父亲。它那耀眼的金色光芒，把西边半个天空照得金灿灿的，把地上的路面、汽车、高楼、树木照得金灿灿的，在刺骨的寒风中给路上的行人送去了一丝丝温暖。西方的天空飘着几小朵云彩，阳光让云彩变成了金色的灿烂的晚霞，西方的天空变成了燃烧着的炉膛。彩云在天空中不断变化着形状，一会儿变成了一匹骏马，奔腾着，身后扬起许多沙子；一会儿又变成了一条大狗，身后还跟着一群小狗，跑着跑着不见了；一会儿又变成了一尊石狮子，静静的蹲在那里。

瑞文标准推理测验简介

瑞文标准推理测验简介 Document serial number【LGGKGB-LGG98YT-LGGT8CB-LGUT-

《瑞文标准推理测验(SPM)》简介瑞文标准推理测验（Raven’s Standard Progressive Matrices，简称SPM）是由英国心理学家瑞文（J. C. Raven）1938年编制的非言语智力测验。它的主要任务是要求被试根据一个大图形中的符号或图案的规律，将适当的图形填入大图形的空缺中，如下图所示。自其问世以来，许多国家对它做了修订，直到现在仍广泛使用，有着重要的理论意义与实用价值。 瑞文推理测验有三种类型：（1）标准推理测验（简称SPM，1938）：适用于8岁到成人被试，有5个黑白系列；（2）儿童彩色渐进测验（Raven’s Color Progressive Matrices，简称CPM，1947），有三个系列；（3）高级推理测验（Raven’s Advanced Progressive Matrices，简称APM，1956），适用于高智力水平者。这三种推理测验在我国已修订发行。 瑞文测验在编制在理论上依据斯皮尔曼的智力二因素理论。该理论认为智力主要有两个因素构成，其一是一般因素，又称“G”因素，它可以渗入所有的智力活动中，每个人都具有这种能力，但在水平上有差异；另一因素是特殊因素，可用“S”表示，这种因素种类多，与特定任务高相关，例如音乐能力、数学、交际能力等。瑞文推理测验测量的是智力的一般因素（“G”因素），尤其与人的问题解决，清晰知觉和思惟，发现和利用自己所需信息，以及有效地适应社会生活的能力有关。

GALA《Young for you》歌词及翻译

1 （中文翻译）嘿，伙计们真酷 你好啊窝囊废我们才真叫酷001_intro...the band is so cool (suddoo/M/wangzi) Hello loser The band is so cool

2 （中文）忧郁的废物002_the blue elephants(suddoo) 我是忧郁的废物 生活在离奇的国度 现实它虚拟恍惚 爱情也飘缈虚无 我是忧郁的废物 迷恋着成长的孤独 拒绝这生命重复 却变得一无是处

3 （中文翻译） 田纳西 田纳西 照耀着我 轻易来到 却不舍离去 我该死 却不会哭 曾经是那么 豪迈不羁 梦着梦 不觉遗憾 把我的心 涂的闪亮 抱紧我 这很好 总而言之 你是我的大海 （你是我的仙女） 在夜里和谁一起跳舞篝火旁河水缓缓流淌你的面如丝绒气贯长虹但除了我你别无所依谁偷走你的时间 让你无法继续走 在停滞中你感觉晕眩之后一切都空空如也003_tennessee(suddoo) Tennessee You shine on me Eazy come Hard to leave I should die But never cry Used to be A magic knight Dream some dreams Not say sorry Paint my heart Let it be lush Hold me tight That's alright Anyway You're my sea (you're my fairy) *Dance with whom at night Fire around,river's gone Velvet face prides you But now you've got only me left *Who's stolen your watch Would like to continue The feeling that made you dizzy Now it's all becomin' empty

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Time in a Bottle - Jim Croce 时光宝瓶- 吉米·克罗斯If I could save time in a bottle 如果时光能用瓶子收藏， The first thing that I'd like to do 我最想做的事情唯有一桩， Is to save every day till eternity passes away, 就是收集每天每日直到永恒消逝， Just to spend them with you. 只为与你共同分享。 If I could make days last forever 如果人生能够万寿无疆， If words could make wishes come true 如果话语能够实现梦想， I'd save every day like a treasure and then 那我就收集每天每日有如珍宝， Again, I would spend them with you 然后与你一同品尝。 But there never seems to be enough time 然而时光似乎总有限量， To do the things you want to do 要做的事情太多太忙， Once you find them 一旦等你有所觉察， I've looked around enough to know 寻寻觅觅，我心中已有主张， You're the one I want to go 人世间唯独是你， Through time with 我愿共度一生的时光。 If I had a box just for wishes 不曾实现的梦想愿望， And dreams that had never come true 假如我有宝盒用来收藏， The box would be empty 这宝盒定会空空荡荡， Except for the memory 里面只有一种记忆， Of how they were answered by you 把你内心的回应存放。

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来了。据说白天的沙漠非常干燥，炎热，只有到太阳下去之后，才是真正的沙漠。 蚂蚁，松鼠，蝎子等小型昆虫，动物才会到这时寻找食物，仙人掌而也是在夜里开花，而在白天，它们有的会躲起来。 这时，有时还会明亮，只不过雾气较大，容易产生海市蜃楼。在沙漠中，落日可能比较漫长，不过也是一道很美丽的风景线。 沙漠落日是我最喜欢的一道美丽的风景线。 如果你在沙漠里，当你在看沙漠落日时，那无疑是一次美丽的画面。 太阳下去了，天色渐渐暗了下去，绚烂的云朵变成深红了，沙漠的雾也逐渐变浓了，沙丘也变得很不清楚。就在这时，太阳收敛了耀眼的光芒，像喝醉了似的，脸上通红。它像一个害羞的姑娘，携来了一块纱巾，遮住了自己红扑扑的脸蛋儿。残阳的余晖映红了天空中的云霞，渐渐地，粉红，紫红，桃红……弥漫着整个天空，像整个展开了一匹绚丽的锦缎，一片片云朵像一个个身披嫁衣的新娘正在

CS测试简介

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SG要求 选择测试注入法规则 测试原理 标准EN61000-4-6定义了传导抗扰度的测试方法. 第一,耦合方法.在EN61000-4-6定义的三种耦合方法,最好的方法是通过耦合/去耦(CDN)直接注入电压,这样插入损耗为零,因此只需要较小的功率. 第二,电缆射频注入测试要求远离EUT的电缆末端上的共模阻抗固定不变.所以,每一种类型的电缆都必须在其远端有一个共模去耦网络或阻抗稳固网络(ISN),以确保这一阻抗,并将任何辅助设备与电缆上的射频电流影响隔离开,并且,使用该网络将射频电压耦合到电缆上. 第三,传导抗扰度测试虽然不需要昂贵的电磁吸波屏蔽室设施,但当几根电缆连接到EUT上时,它能否反映EUT的真实情况还值得怀疑.所以,这种电压注入法不太适合按规定有很多电缆连接到其上的设备. 第四,对传导抗扰度测试的主要限制条件是频率.EUT尺寸远小于测试频率的波长时,射频能量的大部分被暴露在辐射场中的设备电缆所获得,因此传导测试可以反映真实情况.但随着频率的增大,以至于EUT尺寸接近半波长时,则电缆的主导作用减小,并且在较高频率上,场耦合路径与EUT尺寸的结构、内部电路及其电缆相互影响.所以标准EN61000-4-6规定上限频率在80～230MHz(相应设备尺寸约为0.6～2m). 根据电磁辐射环境,测试水平为1V、3V或10V.在设计的测试中，我们选择3V的测试水平。实际施加的信号需用1kHz正弦波进行80%深度的幅度调制.

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胸地唱起了欢送的歌：“喔喔喔，我是一只大公鸡，站在墙头上，送太阳公公回家去！” 这时，太阳把半边脸藏在山后，像一位怕羞的大姑娘似的，含羞地望着无边的大地，不忍离去。可是，好像有一个无情的东西在拉着它，使劲地拉着它往下溜。太阳终于无可奈何地移到山背后，慢慢地沉入地平线。不多时，那多彩的晚霞，也在归林的鸟雀声中收起了余晖。 啊，日落的景象真是无法称赞，使人好像进人了仙境般的世界。 描写日落景色的作文400字篇2傍晚，快要落山的太阳暖暖的照着大地，发出夺目的光芒。慢慢地，太阳变成淡淡的黄球，一会儿，那淡淡的黄球颜色渐渐加深，接着又成了一个略带红色的火球，这时候的太阳已经不那么刺眼了，渐渐地，颜色变的更柔和，更亲切了。 这金色的阳光照在房屋上，给房屋镶嵌了一道金色的房梁；照在奔跑的小孩子脸上，又变得红彤彤的；照在散步的老人身上，白发变成金发，胡须也变的金灿灿的。 不一会儿，那红火渐渐接近了地平线，天边顿时燃起一大片似火的红霞，就如同万面红旗招展。 片刻间，太阳已经接近地平线了。但它好像还要在天边多留一会儿似的，为世界多增添一些光和热。它在五彩云的衬托下，发出了那更美丽、更灿烂的金色光亮。

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see you again歌词（中英文）See You Again - Wiz Khalifa It's been a long day without you my friend 没有老友你的陪伴日子真是漫长 And I'll tell you all about it when I see you again 与你重逢之时我会敞开心扉倾诉所有 We've come a long way from where we began 回头凝望我们携手走过漫长的旅程 Oh I'll tell you all about it when I see you again 与你重逢之时我会敞开心扉倾诉所有 When I see you again 与你重逢之时 Damn who knew all the planes we flew 谁会了解我们经历过怎样的旅程 Good things we been through 谁会了解我们见证过怎样的美好 That I'd be standing right here 这便是我在你眼前出现的原因

Talking to you about another path 与你聊聊另一种选择的可能 I know we loved to hit the road and laugh 我懂我们都偏爱速度与激情 But something told me that it wouldn't last 但有个声音告诉我这美好并不会永恒 Had to switch up look at things different 我们得变更视野 see the bigger picture 转向更为辽阔的天地 Those were the days hard work forever pays 有付出的日子终有收获的时节 Now I see you in a better place 此刻我看到你走进更加美好的未来 How could we not talk about family 当家人已是我们唯一的牵绊 when family's all that we got? 我们怎么能忘却最可贵的真情

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原本穿着花大衣的公鸡，也披上了道道金光;城市里，一座座大楼成了金黄色。很快，太阳就钻进了山里，只露出半张脸儿来，它就像一位害羞的.小姑娘躲进山中，偷偷地望着外边。没过多久，太阳就沉了下云，淹没在群山之中。 太阳把放射出最后一束余晖，天边一片灰暗，只有点点微弱的光亮。夜幕降临，城市里灯光点亮，好像在给最后的一抹斜阳送行。 日落很美，可惜它只是昙花一现，这真是“夕阳无限好，只是近黄昏”。 写日落的作文400字2太阳落山时的景象是多么壮观！我经常去看太阳落山时的景象。 太阳已靠近西山，漂浮在天空的云彩，正在变着颜色，给大地穿上了鲜艳的衣裳。东边，升起了一个月牙，它踮起脚跟。羡慕地望着太阳。这时，夕阳的余辉洒在原野上，大地好像披上了金色的地毯。麦苗似乎在向太阳频频点头，恋恋不舍地高喊：“太阳公公，再见了！”余辉透过树叶，斜射在流动的小河上，闪着夺目的光彩，小河向太阳微笑，好像要高唱一支颂歌，赞扬太阳的功劳。 院子里，鸡、鸭、鹅全身好像都披上了一件金黄的衣裳。大公鸡跳上了墙头，好像“金皇帝”一样，面对夕阳，昂首挺胸地唱起了欢送的歌：“喔喔喔，我是一只大公鸡，站在墙头上，送太阳公公回家去！”

GBT 11049燃烧测试标准介绍

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日落即景作文400字 日落即景作文400字15篇 日落即景作文400字（一）： 天刚入夜，夕阳缓缓西沉，橘红色的天空好似海面，卷起了淡淡的涟漪。 我们来到大蜀山，一路小跑，走上山顶，身上汗流浃背，这才惊觉上衣早已湿透。来到山上，欣赏着这旷世美景。 此时大地似是静悄悄，向远方望去，隐隐约约会看到几团黑影，那是山脚下的建筑物。我站在山顶上的栏杆旁，迎着那日落时清爽的凉风，呼吸着新鲜的空气，衣裙随着风流而摆动，我感觉自我也成为了这世界中的一部分，一切都是那么的完美。 太阳照在大地上，就像是一团火球，树上的树枝纵横交错，知了仍在不停地叫着，它的声音，在这傍晚显得格外孤寂，野花野草在风中摇摆着四肢。渐渐地，天边出现了一大片的红霞，似乎把天都染成了血色，大地就在不知不觉间变成了火红色。 不久，太阳慢慢地向西方退去，转眼间，就像是披了一层红纱，朦朦胧胧的，好似一个戴着面纱的少女，在俯瞰着大地，留恋着这充满温暖的人间。晚霞遍布在这天空当中，它就像是一个舞蹈演员，踏着华尔兹的旋律，跳起了舞蹈，舞步

轻盈，舞姿优美，舞蹈复杂，诉说着心头的喜悦。 过了一会儿，红纱被褪去，取之而代的是厚厚的黑纱，太阳也快要落下去了，黑暗在悄悄地接近，它先是露出了一个头，之后，它整个儿都被黑暗埋没了下去。 此刻的世界，静悄悄的，隐约看到灯火通明的城市，那点点明亮的光，在这黑夜中显得尤为不一样。 知了的叫声有些倦了，我在妈妈的身旁诉耳轻谈，寻着月光向山下走去。 日落即景作文400字（二）： 为了看日落，午时五点，我走向小区最高一栋楼的楼顶。太阳在西边，又大又圆，把最终耀眼的，温暖的光芒洒向大地。 最近天气晴朗，秋高气爽，湛蓝的天空澄澈干净，一尘不染，像一望无际的海。此刻，天空的蓝色已经消褪，变成灰蒙蒙的浅青色。月亮悄悄出来了，挂在东边的天空，一切显得静谧而又完美。 过了一会儿，太阳开始收起它的光芒，缓缓西沉，西天满是红彤彤的醉人的晚霞。远处的塘朗山，塘朗山上的树木，高架天线，都笼罩在肃穆的金色中。不远处的高楼，在夕阳的照耀下，玻璃幕墙反射着粼粼的金色。