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NB4N121KMNR2G;NB4N121KMNG;中文规格书,Datasheet资料

NB4N121K

3.3V Differential 1:21 Differential Fanout Clock Driver with HCSL level Output

Description

The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind.

Inputs can accept differential LVPECL, CML, or LVDS levels. Single?ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper V REFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors.

Output drive current at I REF (Pin 1) for 1X load is selected by connecting to GND. To drive a 2X load, connect I REF to V CC. See Figure 9.

The NB4N121K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take

advantage of the NB4N121K’s performance to distribute low skew clocks across the backplane or the motherboard.

Features

?Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and 400 MHz

?340 ps Typical Rise and Fall Times

?800 ps Typical Propagation Delay

?D tpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair

?Additive Phase RMS Jitter: 1 ps Max

?Operating Range: V CC= 3.0 V to 3.6 V with V EE= 0 V ?Differential HCSL Output Level (700 mV Peak?to?Peak)?Pb?Free Packages are Available

A= Assembly Site

WL= Wafer Lot

YY= Year

WW= Work Week

G= Pb?Free Package

*For additional marking information, refer to

Application Note AND8002/D.

QFN?52

MN SUFFIX

CASE 485M

MARKING DIAGRAM*

https://www.wendangku.net/doc/4117341322.html,

NB4N

121K

AWLYYWWG

Figure 1. Pin Configuration (Top View)

See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

Figure 2. Pinout Configuration (Top View)

I REF GND Q20Q 17

Q 14

Q 13

Q 14

Q 13

Q 16

VTCLK CLK CLK VTCLK V CC Q20Q19Q19Q18Q18

Q 17

Q 16

Q 15

Q 12

V C C

Exposed Pad (EP)

Table 1. PIN DESCRIPTION

Pin Name I/O Description

I REF

Output

Output current programming pin to select load drive. For 1X

configuration, connect I REF to GND, or for 2X configuration, connect I REF to V CC (See Figure 9).

2GND ?Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation.

3, 6

VTCLK,VTCLK

Internal 50 W Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the com-mon termination voltage, and if no signal is applied then the device may be susceptible to self ?oscillation.4CLK LVPECL Input CLOCK Input (TRUE)5CLK LVPECL Input

CLOCK Input (INVERT)

7, 26, 39, 52

V CC ?Positive Supply pins. V CC pins must be externally connected to a power supply to guarantee proper operation.8, 10, 12, 14, 16, 18, 20, 22,24, 27, 29, 31, 33, 35, 37, 40,

42, 44, 46, 48, 50Q[20?0]

HCSL Output

Output (INVERT)

9, 11, 13, 15, 17, 19, 21, 23,25, 28, 30, 32, 34, 36, 38, 41,

43, 45, 47, 49, 51

Q[20?0]HCSL Output Output (TRUE)

Exposed Pad

EP GND

Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat ?sinking conduit for proper thermal operation. (Note 1)

1.The exposed pad must be connected to the circuit board ground.

Table 2. ATTRIBUTES

Characteristic Value Input Default State Resistors None

ESD Protection Human Body Model

Machine Model >2 kV 400 V

Moisture Sensitivity (Note 2)QFN?52Level 1

Flammability Rating Oxygen Index: 28 to 34UL 94 V?0 @ 0.125 in

Transistor Count622

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

2.For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS (Note 3)

Symbol Parameter Condition 1Condition 2Rating Unit V CC Positive Power Supply GND = 0 V 4.6V V I Positive Input GND = 0 V GND ? 0.3 v V I v V CC V V INPP Differential Input Voltage|CLK ? CLKb|V CC V

I OUT Output Current Continuous

Surge 50

100

T A Operating Temperature Range QFN?52?40 to +70°C T stg Storage Temperature Range?65 to +150°C

q JA Thermal Resistance (Junction?to?Ambient) (Note 3)0 lfpm

500 lfpm QFN?52

QFN?52

19.6

°C/W

q JC Thermal Resistance (Junction?to?Case)2S2P (Note 4)QFN?5221°C/W T sol Wave Solder Pb?Free265°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

3.JEDEC standard 51?6, multilayer board ? 2S2P (2 signal, 2 power).

4.JEDEC standard multilayer board ? 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

Table 4. DC CHARACTERISTICS (V CC = 3.0 V to 3.6 V, T A = ?40°C to +70°C Note 5)

Symbol Characteristic Min Typ Max Unit I GND GND Supply Current (All Outputs Loaded)7098120mA

I CC Power Supply Current (All Outputs Loaded)1X

2X 420

780

I IH Input HIGH Current CLKx, CLKx 2.0150m A

I IL Input LOW Current CLKx, CLKx?150?2.0m A DIFFERENTIAL INPUT DRIVEN SINGLE?ENDED (Figures 5 and 7)

V th Input Threshold Reference Voltage Range (Note 6)1050V CC? 150mV

V IH Single?Ended Input HIGH Voltage V th + 150V CC mV

V IL Single?Ended Input LOW Voltage GND V th? 150mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8)

V IHD Differential Input HIGH Voltage1200V CC mV

V ILD Differential Input LOW Voltage GND V CC? 75mV

V ID Differential Input Voltage (V IHD? V ILD)752400mV

V CMR Input Common Mode Range1163V CC? 75

HCSL OUTPUTS (Figure 4)

V OH Output HIGH Voltage600740900mV

V OL Output LOW Voltage?1500150mV NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

5.Input parameters vary 1:1 with V CC. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded

25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to V CC.

6.V th is applied to the complementary input when operating in single ended mode.

Table 5. AC CHARACTERISTICS V CC = 3.0 V to 3.6 V, GND = 0 V; ?40°C to +70°C (Note 7)

Symbol Characteristic

Min

Typ Max Unit V OUTPP

Output Voltage Amplitude (@ V INPPmin ) f in = 133 MHz

f in = 166 MHz f in = 200 MHz 725725725900900900mV

t PLH ,t PHL Propagation Delay to (See Figure 3)

CLK/CLK to Qx/Qx

550800

950ps D t PLH ,D t PHL Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8) (See Figure 3)

100ps t

SKEW

Duty Cycle Skew (Note 9)

Within ?Device Skew, 1X Mode Only (Note 10)Within ?Device Skew, 2X Mode (Note 10)Device ?to ?Device Skew (Note 10)

205080150ps ps ps ps t jit(f )Additive RMS Phase RMS (Note 11) f in =133 MHz to 200 MHz 1

ps V cross Absolute Crossing Magnitude Voltage 250

550mV D V cross Variation in Magnitude of V cross

150

mV t r , t f Absolute Magnitude in Output Risetime and Falltime Qx, Qx

(From 175 mV to 525 mV)

175

340

700

ps D t r, D t f

Variation in Magnitude of Risetime and Falltime (Single ?Ended) Qx, Qx (See Figure 4)

1X 2X

125150

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

7.Measured by forcing V INPP (MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect I REF to GND, or for 2X configuration, connect I REF to V CC . Typical gain is 20 dB.

8.Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges.9.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw ? and Tpw+.10.Skew is measured between outputs under identical transition @ 133 MHz.

11.Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz

Figure 3. AC Reference Measurement

CLK

? V IL (CLK)

V OH (Q) ? V OL (Q)

OH (Q) ? V OL (Q)

Figure 4. HCSL Output Parameter Characteristics

Figure 5. Differential Input Driven

Single?Ended (V th = V REFAC)

Figure 6. Differential Inputs Driven

Differentially

ILD Figure 7. V th Diagram Figure 8. V CMR Diagram

Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation C Lx for Test Only (Representing Receiver Input Loading); Not Added to Application

A IREF 1 k W 50 k

B 25 W

C D

GND

Figure 10. LVPECL Interface

*RTIN, Internal Input Termination Resistor GND

GND

Figure 11. LVDS Interface

*RTIN, Internal Input Termination Resistor

GND

Figure 12. Standard 50 W Load CML

Interface

*RTIN, Internal Input Termination Resistor GND

GND

*RTIN, Internal Input Termination Resistor

Figure 13. LVCMOS/LVTTL Interface

D = V th

Figure 14. HCSL Output Structure

ORDERING INFORMATION

Device

Package Shipping ?NB4N121KMNG QFN ?52 (Pb ?Free)260 Units / Tray NB4N121KMNR2G

QFN ?52 (Pb ?Free)

2000 / Tape & Reel

?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

PACKAGE DIMENSIONS

QFN52 8x8, 0.5P CASE 485M ?01

ISSUE C

NOTES:

1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2.CONTROLLING DIMENSION: MILLIMETERS

3.DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30MM FROM TERMINAL.

4.COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

DIM MIN MAX MILLIMETERS A 0.80 1.00A10.000.05A20.600.80A30.20 REF b 0.180.30D 8.00 BSC D2 6.50 6.80E 8.00 BSC E2 6.50 6.80e 0.50 BSC K 0.20---L

0.300.50

SOLDERING FOOTPRINT*

DIMENSIONS: MILLIMETERS

PKG

RECOMMENDED

?Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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