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ALD1722中文资料

EPAD? OPERATIONAL AMPLIFIER

A DVANCED L INEAR

D EVICES, I NC.

ALD1722E/ALD1722

GENERAL DESCRIPTION

The ALD1722E/ALD1722 is a monolithic rail-to-rail precision CMOS operational amplifier with integrated user programmable EPAD (Electri-cally Programmable Analog Device) based offset voltage adjustment. The ALD1722E/ALD1722 is a direct replacement of the ALD1702 operational amplifier, with the added feature of user-programmable offset voltage trimming resulting in significantly enhanced total system performance and user flexibility. EPAD technology is an exclusive ALD design which has been refined for analog applications where precision voltage trimming is necessary to achieve a desired performance. It utilizes CMOS FETs as in-circuit elements for trimming of offset voltage bias characteristics with the aid of a personal computer under software control. Once pro-grammed, the set parameters are stored indefinitely within the device even after power-down. EPAD offers the circuit designer a convenient and cost-effective trimming solution for achieving the very highest amplifier/system performance.

The ALD1722E/ALD1722 operational amplifier features rail-to-rail input and output voltage ranges, tolerance to over-voltage input spikes of 300mV beyond supply rails, high capacitive loading up to 4000pF, ex-tremely low input currents of 0.01pA typical, high open loop voltage gain,useful bandwidth of 1.5 MHz, slew rate of 2.1 V/μs, and low supply current of 0.8mA.

BENEFITS

?Eliminates manual and elaborate system trimming procedures

?Remote controlled automated trimming ?In-System Programming capability ?No external components

?No internal chopper clocking noise ?No chopper dynamic power dissipation ?Simple and cost effective ?Small package size

?Extremely small total functional volume size

?Low system implementation cost ?Low power

* Contact factory for industrial temperature range

Operating Temperature Range*

-55°C to +125°C 0°C to +70°C 0°C to +70°C

8-Pin 8-Pin

8-Pin

CERDIP Small Outline Plastic Dip Package

Package (SOIC)

Package

ALD1722E DA ALD1722E SA ALD1722E PA ALD1722 DA ALD1722 SA ALD1722 PA

ORDERING INFORMATION

PIN CONFIGURATION

1 2

234

8765

TOP VIEW

DA, PA, SA PACKAGE

VE1-IN +IN VE2OUT N/C

V -

V +APPLICATIONS ?Sensor interface circuits ?Transducer biasing circuits

?Capacitive and charge integration circuits ?Biochemical probe interface ?Signal conditioning ?Portable instruments

?High source impedance electrode amplifiers

?Precision Sample and Hold amplifiers ?Precision current to voltage converter ?Error correction circuits

?Sensor compensation circuits ?Precision gain amplifiers

?Periodic In-system calibration ?

System output level shifter

KEY FEATURES ?EPAD ( Electrically Programmable Analog Device)?User programmable V OS trimmer ?Computer-assisted trimming ?Rail-to-rail input/output

?Compatible with standard EPAD Programmer

?High precision through in-situ circuit precision trimming ?Reduce or eliminate V OS , PSRR, CMRR and TCV OS errors ?System level “calibration” capability ?In-System Programming capable

Electrically programmable to compensate for external component tolerances

?Achieve 0.01pA input bias current and 25μV input offset voltage simultaneously

?Compatible with industry standard pinout

FUNCTIONAL DESCRIPTION

The ALD1722E/ALD1722 uses EPADs as in-circuit ele-ments for trimming of offset voltage bias characteristics. Each ALD1722E/ALD1722 has a pair of EPAD-based cir-cuits connected such that one circuit is used to adjust V OS in one direction and the other is used to adjust V OS in the other direction.

Functional Description of ALD1722E

While each of the EPAD devices is a monotonically adjust-able programmable device, the V OS of the ALD1722E can be adjusted many times in both directions. Once pro-grammed, the set V OS levels are stored permanently, even when the device power is removed.

The ALD1722E provides the user with an operational ampli-fier that can be trimmed with user application-specific pro-gramming or in-system programming conditions. User appli-cation-specific circuit programming refers to the situation where the Total Input Offset Voltage of the ALD1722E can be trimmed with the actual intended operating conditions. The ALD1722E is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. It also has a guaranteed offset voltage program range, which is ideal for applications that require electrical offset voltage programming.

For example, an application circuit may have +6V and -2.5V power supplies, and the operational amplifier input is biased at +0.7V, and the average operating temperature is at 55°C. The circuit can be wired up to these conditions within an environmental chamber, and the ALD1722E can be inserted into a test socket connected to this circuit while it is being electrically trimmed. Any error in V OS due to these bias conditions can be automatically zeroed out. The Total V OS error is now limited only by the adjustable range and the stability of V OS, and the input noise voltage of the operational amplifier. Therefore, this Total V OS error now includes V OS as V OS is traditionally specified; plus the V OS error contribu-tions from PSRR, CMRR, TCV OS, and noise. Typically this total V OS error term (V OST) is approximately ± 25μV for the ALD1722E.

The V OS contribution due to PSRR, CMRR, TCV OS and external components can be large for operational amplifiers without trimming. Therefore the ALD1722E with EPAD trim-ming is able to provide much improved system performance by reducing these other sources of error to provide signifi-cantly reduced V OST.

In-System Programming refers to the condition where the EPAD adjustment is made after the ALD1722E has been inserted into a circuit board. In this case, the circuit design must provide for the ALD1722E to operate in normal mode and in programming mode. One of the benefits of in-system programming is that not only is the ALD1722E offset voltage from operating bias conditions accounted for, any residual errors introduced by other circuit components, such as resistor or sensor induced voltage errors, can also be cor-rected. In this way, the “in-system” circuit output can be adjusted to a desired level eliminating other trimming https://www.wendangku.net/doc/4b17412073.html,ER PROGRAMMABLE Vos FEATURE

Each ALD1722E/ALD1722 has two pins named VE1 and VE2 which are internally connected to an internal offset bias circuit. VE1/VE2 have initial typical values of 1.6 Volt. The voltage on these pins can be programmed using the ALD E100 EPAD Programmer and the appropriate Adapter Mod-ule. The useful programming range of VE1 and VE2 is 1.6 Volt to 3.5 Volts. VE1 and VE2 pins are programming pins, used during programming mode. The Programming pin is used during electrical programming to inject charge into the internal EPADs. Increases of VE1 decrease the offset volt-age while increases of VE2 increase the offset voltage of the operational amplifier. The injected charge is permanently stored and determines the offset voltage of the operational amplifier. After programming, VE1 and VE2 terminals must be left open to settle on a voltage determined by internal bias currents.

During programming, the voltages on VE1 or VE2 are increased incrementally to set the offset voltage of the operational amplifier to the desired V OS. Note that desired V OS can be any value within the offset voltage program-mable ranges, and can be either zero, a positive value or a negative value. This V OS value can also be reprogrammed to a different value at a later time, provided that the useful VE1 or VE2 programming voltage range has not been exceeded. VE1 or VE2 pins can also serve as capacitively coupled input pins.

Internally, VE1 and VE2 are programmed and connected differentially. Temperature drift effects between the two internal offset bias circuits cancel each other and introduce less net temperature drift coefficient change than offset voltage trimming techniques such as offset adjustment with an external trimmer potentiometer.

While programming, V+, VE1 and VE2 pins may be alter-nately pulsed with 12V (approximately) pulses generated by the EPAD Programmer. In-system programming requires the ALD1722E/ALD1722 application circuit to accommo-date these programming pulses. This can be accomplished by adding resistors at certain appropriate circuit nodes. For more information, see Application Note AN1700. Functional Description of ALD1722

The ALD1722 is pre-programmed at the factory under stan-dard operating conditions for minimum equivalent input off-set voltage. The ALD1722 offers similar programmable features as the ALD1722E, but with more limited offset voltage program range. It is intended for standard opera-tional amplifier applications where little or no electrical pro-gramming by the user is necessary.

ABSOLUTE MAXIMUM RATINGS

Supply voltage, V+ 13.2V Differential input voltage range -0.3V to V+ +0.3V Power dissipation 600 mW Operating temperature range PA,SA package 0°C to +70°C

DA package-55°C to +125°C Storage temperature range-65°C to +150°C Lead temperature, 10 seconds +260°C OPERATING ELECTRICAL CHARACTERISTICS

T A= 25o C V S = ±2.5V unless otherwise specified

1722E1722

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Supply Voltage V S±2.0±5.0±2.0±5.0V

V+ 4.010.0 4.010.0V Single Supply Initial Input Offset Voltage1V OS i25504090μV R S≤ 100K?Offset Voltage Program Range2?V OS±5±8±0.5±3mV

Programmed Input Offset V OS25504090μV At user specified Voltage Error3target offset voltage

Total Input Offset Voltage4V OST25504090μV At user specified

target offset voltage

Input Offset Current5I OS0.01100.0110pA T A = 25°C

280280pA0°C ≤ T A≤ +70°C

Input Bias Current5I B0.01100.0110pA T A = 25°C

280280pA0°C ≤ T A≤ +70°C

Input Voltage Range 6V IR-0.3 5.3-0.3 5.3V V+ = +5V; notes 2,5

-2.8+2.8-2.8+2.8V V S = ±2.5V

Input Resistance R IN10141014?

Input Offset Voltage Drift 7TCV OS57μV/°C R S ≤ 100K?

Initial Power Supply PSRR i8585dB R S≤ 100K?Rejection Ratio 8

Initial Common Mode CMRR i9797dB R S≤ 100K?Rejection Ratio 8

Large Signal Voltage Gain A V5025050250V/mV R L =10K?

500500V/mV R L≥ 1M?

V O low0.0020.010.0020.01V R L =1M? V+ = 5V

V O high 4.99 4.998 4.99 4.998V 0°C ≤ T A≤ +70°C Output Voltage Range V O low-2.44-2.35-2.44-2.35V R L =10K?

V O high 2.35 2.44 2.35 2.44V0°C ≤ T A≤ +70°C Output Short Circuit Current I SC88mA

*NOTES 1 through 9, see section titled "Definitions and Design Notes".

OPERATING ELECTRICAL CHARACTERISTICS (cont'd)

T A= 25o C V S = ±2.5V unless otherwise specified

1722E1722

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Supply Current I S0.8 1.50.8 1.5mA V IN = 0V

No Load

Power Dissipation P D 4.07.5 4.07.5mW V S = ±2.5V Input Capacitance C IN11pF

Maximum Load Capacitance C L400400pF Gain = 1

40004000pF Gain = 5

Input Noise Voltage e n2626nV/√ Hz f = 1KHz

Input Current Noise i n0.60.6fA/√ Hz f =10Hz Bandwidth B W 1.0 1.5 1.0 1.5MHz

Slew Rate S R 1.4 2.1 1.4 2.1V/μs A V = +1

R L = 10K?

Rise time t r0.20.2μs R L = 10K?

Overshoot Factor1010%R L = 10K?,

C L = 100pF

Settling Time t s8.08.0μs0.01%

3.0 3.0μs0.1%

A V = -1, R L= 5K?

C L = 50pF

T A= 25o C V S = ±2.5V unless otherwise specified

1722E1722

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Average Long Term Input Offset? V OS0.020.02μV/

Voltage Stability 9? time1000 hrs

Initial VE Voltage VE1 i 1.6 2.6V

VE2i

Programmable VE Range?VE1 1.5 2.00.5V

?VE2

VE Pin Leakage Current i eb-5-5μA

V S= ±2.5V -55°C ≤ T A ≤ +125°C unless otherwise specified

1722E1722

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Initial Input Offset Voltage V OS i0.50.7mV R S ≤ 100K?

Input Offset Current I OS 2.0 2.0nA

Input Bias Current I B 2.0 2.0nA

Initial Power Supply PSRR i8585dB R S ≤ 100K?Rejection Ratio 8

Initial Common Mode CMRR i9797dB R S≤ 100K?RejectionRatio 8

Large Signal Voltage Gain A V10251025V/mV R L≤ 10K?

Output Voltage Range V O low-2.4-2.3-2.4-2.3V R L≤ 10K?

V O high 2.3 2.4 2.3 2.4V

T A= 25o C V S = ±5.0V unless otherwise specified

1722E1722

Parameter Symbol Min Typ Max Min Typ Max Unit Test Conditions

Initial Power Supply PSRR i8585dB R S≤ 100K?Rejection Ratio 8

Initial Common Mode CMRR i9797dB R S ≤ 100K?Rejection Ratio 8

Large Signal Voltage Gain A V250250V/mV R L = 10K?

Output Voltage Range V O low-4.90-4.80-4.90-4.80V R L = 10K?

V O high 4.80 4.93 4.80 4.93

Bandwidth B W 1.7 1.7MHz

Slew Rate S R 2.8 2.8V/μs A V = +1, C L = 50pF

OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE AND TEMPERATURE

SUPPLY VOLTAGE (V)

1000

100

O P E N L O O P V O L T A G E G A I N (V /m V )

±2

±4

±6

±8

OPEN LOOP VOLTAGE AS A FUNCTION OF FREQUENCY

FREQUENCY (Hz)

100

10K

10M

100K

120100806040200-20

O P E N L O O P V O L T A G E G A I N (d B )

90045180

135PHASE SHIFT IN DEGREES

COMMON MODE INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

C O M M O N M O

E I N P U T V O L T A G E R A N G E (V )

±7

±6 ±5 ±4 ±3 ±2 ±100

±1 ±2 ±3 ±4 ±5 ±6 ±7

INPUT BIAS CURRENT AS A FUNCTION

OF AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

100 10

1.00.01

0.1I N P U T B I A S C U R R E N T (p A )

100

-25

125

-50

1000

CHANGE IN INPUT OFFSET VOLTAGE AS A FUNCTION OF CHANGE IN VE1 AND VE2

C H A N G E I N I N P U T O F F S E T V O L T A G E ?V O S (m V )

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-5-4-3-2-101234

5CHANGE IN VE1 AND VE2 (V)

SUPPLY CURRENT AS A FUNCTION

OF SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

2.5

2.01.01.50 0.5S U P P L Y C U R R E N T (m A )

±1±2±3±4±5±6

LARGE - SIGNAL TRANSIENT

RESPONSE

SMALL - SIGNAL TRANSIENT

RESPONSE

OPEN LOOP VOLTAGE GAIN AS A

FUNCTION OF LOAD RESISTANCE

LOAD RESISTANCE (?)

10K

1000K

100K

1000

100

1O P E N L O O P V O L T A G E

G A I N (V /m V )

OUTPUT VOLTAGE SWING AS A FUNCTION OF SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

O U T P U T V O L T A G E S W I N G (V )

±30

±1

±2

±3

±4

±5

±6

±7

±6±

5±4±2

±7

-2500

-2000

-1500

-1000

-500

500

1000

1500

2000

2500

TOTAL INPUT OFFSET VOLTAGE (μV)

10080

0DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE

P E R C E N T A G E O F U N I T S (%)

500

400

300

200

100

0E Q U I V A L E N T I N P U T O F F S E T V O L T A G E D U E T O C H A N G E I N S U P P L Y V O L T A G E (μV )

TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO

CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

COMMON MODE VOLTAGE (V)

0E Q U I V A L E N T I N P U T O F F S E T V O L T A G E D U E T O C H A N G E I N C O M M O N M O D E V O L T

A G E (μV )

EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE

FOR A COMMON MODE VOLTAGE RANGE OF 0.5V

-5

-4

-3

-2

-1

COMMON MODE VOLTAGE (V)

500

400

300

200

100

0E Q U I V A L E N T I N P U T O F F S E T V O L T A G E D U E T O C H A N G E I N C O M M O N M O D E V O L T A G E (μV )

THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE

APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING Examples of applications where accumulated total input offset voltage from various contributing sources is minimized under different sets of user-specified operating conditions

EXAMPLE B

(

)

2500

2000

1500

1000

500

-500

-1000

-1500

-2000

-2500

EXAMPLE C

(

)

2500

2000

1500

1000

500

-500

-1000

-1500

-2000

-2500

EXAMPLE D

(

)

2500

2000

1500

1000

500

-500

-1000

-1500

-2000

-2500

EXAMPLE A

(

)

2500

2000

1500

1000

500

-500

-1000

-1500

-2000

-2500

DEFINITIONS AND DESIGN NOTES:

1. Initial Input Offset Voltage is the offset voltage of the ALD1722E/ALD1722 operational amplifier as shipped from the factory. The device has been pre-programmed and tested for programmability.

2. Offset Voltage Program Range is the range of adjustment of user specified target offset voltage. This is typically an adjust-ment in either the positive or the negative direction of the input offset voltage from an initial offset voltage. The input offset program pins, VE1 or VE2, change the input offset voltage in the negative or positive direction, respectively. User specified target offset voltage can be any offset voltage within this programming range.

3. Programmed Input Offset Voltage Error is the final offset voltage error after programming, when the Input Offset Voltage is at target Offset Voltage. This parameter is sample tested.

4. Total Input Offset Voltage is the same as Programmed Input Offset Voltage, corrected for system offset voltage error. Usu-ally this is an all inclusive system offset voltage, which also includes offset voltage contributions from input offset voltage, PSRR, CMRR, TCVos and noise. It can also include errors introduced by external components, at a system level. Pro-grammed Input Offset Voltage and Total Input Offset Voltage is not necessarily zero offset voltage, but an offset voltage set to compensate for other system errors as well. This parameter is sample tested.

5. The Input Offset and Bias Currents are essentially input protection diode reverse bias leakage currents. This low input bias current assures that the analog signal from the source will not be distorted by it. For applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding.

6. Input Voltage Range is determined by two parallel comple-mentary input stages that are summed internally, each stage having a separate input offset voltage. While Total Input Offset Voltage can be trimmed to a desired target value, it is essential to note that this trimming occurs at only one selected input bias voltage. Depending on the selected input bias voltage relative to the power supply voltages, offset voltage trimming may affect one or both input stages. For the ALD1722E/ALD1722, the switching point between the two stages occur at approximately 1.5V above the negative supply voltage

7. Input Offset Voltage Drift is the average change in Total Input Offset Voltage as a function of ambient temperature. This parameter is sample tested.

8. Initial PSRR and initial CMRR specifications are provided as reference information. After programming, error contribution to the offset voltage from PSRR and CMRR is set to zero under the specific power supply and common mode conditions, and becomes part of the Programmed Input Offset Voltage Error.

9. Average Long Term Input Offset Voltage Stability is based on input offset voltage shift through operating life test at 125 degrees C extrapolated to Ta = 25 degrees C, assuming activation energy of 1.0eV. This parameter is sample tested.ADDITIONAL DESIGN NOTES:

A. The ALD1722E/ALD1722 is internally compensated for unity gain stability using a novel scheme which produces a single pole role off in the gain characteristics while providing more than 70 degrees of phase margin at unity gain frequency. A unity gain buffer using the ALD1722E/ALD1722 will typically drive 400pF of external load capacitance; in the inverting unity gain configu-ration, it can drive up to 800pF of load capacitance.

B. The ALD1722E/ALD1722 has complementary p-channel and n-channel input differential stages connected in parallel to accomplish rail to rail input common mode voltage range. The switching point between the two differential stages is 1.5V above negative supply voltage. For applications such as invert-ing amplifier or non-inverting amplifier with a gain larger than 2.5 (5V operation), the common mode voltage does not make excursions below this switching point. However, this switching does take place if the operational amplifier is connected as a rail-to- rail unity gain buffer and the design must allow for input offset voltage variations.

C. The output stage consists of class AB complementary output drivers. The oscillation resistant feature, combined with the rail-to-rail input and output feature, makes the ALD1722E/ALD1722 an effective analog signal buffer for high source impedance sensors, transducers, and other circuit networks.

D. The ALD1722E/ALD1722 has static discharge protection. However, care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. The user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages to not exceed 0.3V of the power supply voltage levels.

E.VE1 and VE2 are high impedance terminals, as the internal bias currents are set very low to a few microamperes to conserve power. For some applications, these terminals may need to be shielded from external coupling sources. For ex-ample, digital signals running nearby may cause unwanted offset voltage fluctuations. Care during the printed circuit board layout to place ground traces around these pins and to isolate them from digital lines would generally eliminate such coupling effects. In addition, optional decoupling capacitors of 1000pF or greater value can be added to VE1 and VE2 terminals.

F. The ALD1722E/ALD1722 is designed for use in low voltage, micro-power circuits. The maximum operating voltage during normal operation should remain below 10 Volts at all times. Care should be taken to insure that the application in which the devices are used would not experience any positive or negative transient voltages that cause any of the terminal voltages to exceed this limit.

G. All inputs or unused pins except VE1 and VE2 pins should be connected to a supply voltage such as Ground so that they do not become floating pins, since input impedance at these pins is very high. If any of these pins are left undefined, they may cause unwanted oscillation or intermittent excessive current drain. As these devices are built with CMOS technology, normal operating and storage temperature limits, ESD and latchup handling precautions pertaining to CMOS device handling should be observed.