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TAS5766M,TAS5768M

SLAS965A–SEPTEMBER2013–REVISED JUNE2014

TAS576xM2x50W/4ΩPurePath?Smart Amp

1Features?I2C control

?48-pin PowerPAD?HTSSOP or VQFN Package ?PurePath?Smart Amp:

–Optimizes and Protects Dynamic

2Applications

Loudspeakers

?Audio Docks

–Bass Q-compensation and Frequency

?Soundbars

Extension:More Loudness,Bass

Enhancement,Better Clarity and Higher?Laptops

Fidelity.?All-In-One Computers

–Thermal and Excursion Limitation.?Digital TVs

?Stereo Class-D Amplifier With:

3Description

–Wide Power Supply Range:4.5V–26.4V

The TAS576xM PurePath?Smart Amp enhance the –Wide Load Range:2Ω–8Ω;

bass,sound fidelity and provide more loudness and –High output current:2x7.5A

at the same time drive a speaker to its thermal and –Peak output power2x50W/4Ωmechanical limits.

–Continuous Power:2x20W w/o heat sink The TAS576xM contains two BTL class-D –Click and Pop free:Power,Mute and Standby amplifiers–with up to2x50W peak into4Ω.The ON/OFF amplifier is thermally designed to fit with the typical

speaker so it can handle high peaks for the time it –Low Output Noise:<60μVrms@12V supply,

takes the speaker voice-coil to heat up,and then it <90μVrms@24V supply

lowers the average power to safe limits.

–Low THD+N:<0.02%@1W/4Ω,1kHz

The wide supply range of4.5V to26.4V enables the –Thermal,Over-Current and Short-Circuit

use of a wide range of different power supply options Protected from2-cell Li-Ion batteries to fixed24V supply.

?Configurable Digital Audio Processor.

TI's PurePath?Smart Amp technology allow –Down Mixing and Custom EQ with10BiQuads speakers to be driven with more peak power than

?Digital Audio Interface:I2S or TDM input w.their average power rating,without fear of damage to

the speaker through over excursion or thermal-–44.1kHz and48kHz FS

overload.

–Configurable Digital Output

?Multisegment DAC with Excellent Jitter Device Information(1)

Suppression PART NUMBER PACKAGE BODY SIZE(NOM)?Integrated High-Performance Audio PLL HTSSOP(48)12.50mm×6.10mm

TAS5766M

VQFN(48)7.00mm×5.00mm

HTSSOP(48)12.50mm×6.10mm

TAS5768M

VQFN(48)7.00mm×5.00mm

(1)For all available packages,see the orderable addendum at

the end of the datasheet.

4Smart Amplifier Overview

TAS5766M,TAS5768M

SLAS965A–SEPTEMBER2013–REVISED https://www.wendangku.net/doc/552022897.html,

Table of Contents

8.4Device Functional Modes (20)

1Features (1)

8.5Programming (36)

2Applications (1)

9Applications and Implementation (39)

3Description (1)

9.1Application Information (39)

4Smart Amplifier Overview (1)

9.2Typical Applications (39)

5Revision History (2)

10Power Supply Recommendations (46)

6Pin Configuration and Functions (3)

10.1AVDD,DVDD,CPVDD Supply (46)

7Specifications (6)

10.2GVDD Supply (46)

7.1Absolute Maximum Ratings (6)

10.3PVCC,AVCC Power Supply (46)

7.2Handling Ratings (6)

11Layout (47)

7.3Recommended Operating Conditions (6)

11.1Layout Guidelines (47)

7.4Thermal Information (7)

11.2Layout Examples (48)

7.5DC Electrical Characteristics (7)

12Device and Documentation Support (50)

7.6AC Electrical Characteristics (8)

12.1Detailed Register Map Descriptions (50)

7.7Electrical Characteristics (9)

12.2Related Links (73)

7.8Timing Requirements-I2C Bus Timing (10)

12.3Trademarks (73)

7.9Typical Characteristics (11)

12.4Electrostatic Discharge Caution (73)

8Detailed Description (16)

12.5Glossary (73)

8.1Overview (16)

13Mechanical,Packaging,and Orderable

8.2Functional Block Diagram (16)

Information (73)

8.3Feature Description (17)

5Revision History

NOTE:Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original(September2013)to Revision A Page ?Revised data sheet to new format;added Device Information table to first page (1)

?Added TAS5768M device (1)

?Added RMT package option (1)

2Submit Documentation Feedback Copyright?2013–2014,Texas Instruments Incorporated

B S P R

PVCC GVDD GND INNR DACR GND SDA SCL INPR GPIO2INPL PVCC AVCC B S P L

GND VNEG CAPM CPVDD GND CAPP DACL G N D

O U T P R

GND O U T N R

B S N R

B S N L

O U T N L

GND A D R 2

G P I O 3

S C K

B C K

D I N

L R C L K

A D R 1

X S M T /U V P

L D O O

G N D

GAIN/FSW GPIO1DVDD

O U T P L G N D INNL AVDD FAULT TAS5766M,TAS5768M

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SLAS965A –SEPTEMBER 2013–REVISED JUNE 2014

6Pin Configuration and Functions

VQFN (RMT)Package

48-Pin Top View

OUTNR GND OUTPR PVCC GAIN/FSW

BSPR INNR LDOO CAPM GND VNEG CAPP OUTPL CPVDD DVDD LRCLK

GND ADR1XSMT/UVP AVCC OUTNL GND BSNL

BSPL PVCC FAULT

INNL PVCC INPL DACL GND INPR DACR GND SCL GPIO2ADR2GPIO1GPIO3BSNR SDA BCLK DIN PVCC GND AVDD GVDD SCLK TAS5766M,TAS5768M

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HTSSOP (DCA)Package

48-Pin Top View

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Pin Functions

DCA RMT

SYMBOL TYPE(1)DESCRIPTION

PIN No.PIN No.

ADR12645I LSB address select bit for I2C

ADR22039I2nd LSB address select bit for I2C

AVCC4112PI Analog Supply–connect to PVCC

AVDD1433PI Analog Supply

BCLK2342I Audio data bit clock input

Boot strap negative Left channel output,connect to220nF X7R ceramic cap to BSNL4819BST

OUTNL

Boot strap negative Right channel output,connect to220nF X7R ceramic cap to BSNR120BST

OUTNR

Boot strap positive Left channel output,connect to220nF X7R ceramic cap to

BSPL4417BST

OUTPL

Boot strap positive Right channel output,connect to220nF X7R ceramic cap to BSPR522BST

OUTPR

CAPM345Charge pump flying capacitor pin for negative rail

CAPP323Charge pump flying capacitor pin for positive rail

CPVDD312PI Charge pump power supply,3.3V

DACL367O Analog output from DAC left channel,ground centered

DACR1332O Analog output from DAC Right channel,ground centered

DIN2443I Audio data input

DVDD301PI Digital power supply,3.3V

FAULT4011OD General fault reporting,Open Drain,High=normal operation,Low=fault condition GAIN/FSW928I Sets power stage Gain and selects output switching frequency

3,10,15,4,10,14,15,

GND29,33,39,24,25,29,34,G Ground

4648

GPIO11837I/O General purpose digital input and output port

GPIO21938I/O General purpose digital input and output port

GPIO32140I/O General purpose digital input and output port

GVDD827PBY Internal Gate drive supply,connect1uF to GND

INNL389I Negative audio input for Left channel.Internally biased at3V

INNR1130I Negative audio input for Right channel.Internally biased at3V

INPL378I Positive audio input for Left channel.Internally biased at3V

INPR1231I Positive audio input for Right channel.Internally biased at3V

LDOO2847PBY Internal logic supply rail pin for decoupling,1.8V,connect1μF to GND

LRCLK2544I Audio data word clock input

OUTNL4718PO Negative Left channel output

OUTNR221PO Negative Right channel output

OUTPL4516PO Positive Left channel output

OUTPR423PO Positive Right channel output

6,7,42,

PVCC13,26PI 4.5-V to26.4-V Power supply

SCL1736I Input clock for I2C

SCLK2241I System clock input(also referred to as master clock input)

SDA1635I/O Input data for I2C

Thermal

4949G Connect Thermal Pad to Ground

pad

VNEG356PO Negative charge pump rail pin for decoupling–3.3V

XSMT/UVP2746I Soft mute control:Soft mute(Low)/soft un-mute(High)

(1)TYPE:BST=Boot Strap,PO=Power Output,G=General Ground,I=Input,O=Output,I/O=Input or Output,,PBY=Power Bypass,,

PI=Power Input,.

TAS5766M,TAS5768M

SLAS965A–SEPTEMBER2013–REVISED https://www.wendangku.net/doc/552022897.html, 7Specifications

7.1Absolute Maximum Ratings

over operating free-air temperature range(unless otherwise noted)(1)

MIN MAX UNIT Supply Voltage:PVCC,AVCC–0.330V

V CC

AVDD,DVDD,CPVDD–0.3 3.9V

Input Voltage:INPL,INNL,INPR,INNR–0.3 6.3V

V I Input Voltage:GAIN/FSW,FAULT–0.3GVDD+0.3V Digital Input Voltage:DVDD=3.3V–0.3 3.9V

T A Operating free-air temperature–4085°C

Operating Junction temperature,digital die–40125°C

T J

Operating Junction temperature,power die–40150°C (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings

only,which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2Handling Ratings

MIN MAX UNIT

T stg Storage temperature range–40125°C

Human body model(HBM),per ANSI/ESDA/JEDEC JS-–20002000

001,all pins(2)

Electrostatic

V(ESD)(1)V discharge Charged device model(CDM),per JEDEC specification–500500

JESD22-C101,all pins(3)

(1)Electrostatic discharge(ESD)measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2)Level listed above is the passing level per ANSI,ESDA,and JEDEC JS-001.JEDEC document JEP155states that500-V HBM allows

safe manufacturing with a standard ESD control process.

(3)Level listed above is the passing level per EIA-JEDEC JESD22-C101.JEDEC document JEP157states that250-V CDM allows safe

manufacturing with a standard ESD control process.

7.3Recommended Operating Conditions

over operating free-air temperature range(unless otherwise noted)

MIN TYP MAX UNIT

Vcc PVCC,AVCC 4.526.4 Supply Voltage V Vdd AVDD,DVDD,CPVDD3 3.3 3.6

V IH High level input voltage2V

V IL Low level input voltage0.8V

V OL Low level output voltage FAULT,R pullup=100kΩ,PVCC=26V0.8V

PVCC=24V 3.24

PVCC=18V 2.53

R L Minimum load impedance?

PVCC=12V 1.82

PVCC=6V0.91

PVCC=24V 1.8 2.2

PVCC=18V 1.4 1.6 PBTL Minimum load

R L_PBTL?impedance PVCC=12V 1.0 1.2

PVCC=6V0.50.6

Lo Output filter inductance Minimum output filter inductance under short-circuit condition1 4.7μH

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7.4Thermal Information

TAS576xM

RMT(48PINS)DCA(48PINS)

THERMAL METRIC(1)UNIT

2LAYER

4LAYER PCB(2)

PCB(3)

RθJA Junction-to-ambient thermal resistance3030

RθJC(top)Junction-to-case(top)thermal resistance1514

RθJB Junction-to-board thermal resistance613

°C/W

ψJT Junction-to-top characterization parameter0.20.6

ψJB Junction-to-board characterization parameter613

RθJC(bot)Junction-to-case(bottom)thermal resistance 1.90.7

(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.

(2)For the PCB layout see the TAS576xMRMTEVM User Guide.A4layer60x60mm1oc PCB was used

(3)For the PCB layout see the TAS576xMDCAEVM User Guide.A2layer60x60mm1oc PCB was used

7.5DC Electrical Characteristics

All specifications at T A=25°C,AVDD=CPVDD=DVDD=3.3V,f S=48kHz,system clock=512f S and24-bit data,V CC= 12V to24V,R L=4?(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Class-D output offset voltage(measured PV CC=12V,gain set to14dB110mV

differentially)

|VOS|

PV CC=24V,gain set to20dB 1.515mV Input is Bipolar Zero data

Drain-source on-state resistance,measured

R DS(on)VCC=24V,I out=500mA,T J=25°C120m?pin to pin

Gain pin voltage<3V131415dB

G Analog Gain from INxx to OUTxx

Gain pin voltage>3.3V192021dB

t on Turn-on time XSMT=2V 1.5ms

t OFF Turn-off time XSMT=0.8V0.8ms GVDD Gate Drive Supply Voltage IGVDD≤200μA 6.9V

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7.6AC Electrical Characteristics

All specifications at T A=25°C,AVDD=CPVDD=DVDD=3.3V,f S=48kHz,system clock=512f S and24-bit data,V CC=

12V to24V,R L=4?unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

200mV PP ripple at1kHz,gain=20dB,zero input

K SVR Power supply ripple rejection–60dB

signal

THD+N=10%,1kHz,24-V supply,8-Ωload30W

P O Peak output power

THD+N=10%,1kHz,24-V supply,4-Ωload50W

Ra=100k?,Rb=open8

Ra=20k?,Rb=100k?10 Output switch frequency multiple of FS Gain

F sw

set to14dB Ra=39k?,Rb=100k?12

Ra=47k?,Rb=75k?16

Ra=51k?,Rb=51k?8

Ra=75k?,Rb=47k?10 Output switch frequency multiple of FS Gain

F sw

set to20dB Ra=100k?,Rb=39k?12

Ra=100k?,Rb=20k?16

1W,1kHz,4R load,12V supply0.05%

THD+N Total Harmonic Distortion+Noise

1W,1kHz,8R load,24V supply0.05%

20-22kHz,A-weighted,14dB gain,12V supply60μV

V N Output integrated noise

20-22kHz,A-weighted,20dB gain,24V supply85μV

20-22kHz,A-weighted,14dB gain,12V supply103dB SNR Signal to Noise Ratio

20-22kHz,A-weighted,20dB gain,24V supply106dB Crosstalk V O=1V rms,20dB gain,1kHz,4-Ωload–90dB

I P Peak output current1kHz,10ms,3-Ωload,24-V supply7.5A

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7.7Electrical Characteristics

All specifications at T A=25°C,AVDD=CPVDD=DVDD=3.3V,f S=48kHz,system clock=512f S and24-bit data,V CC= 12V to24V,R L=4?(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution162432Bits DATA FORMAT(PCM MODE)

I2S,left justified,right justified Audio data interface format

and TDM Audio data bit length16,24,32-bit acceptable

Audio data format MSB First,2s Complement

f S Samplin

g frequency848kHz CLOCKS

64,128,192,256,384,512, System clock frequency768,1024,1152,1536,2048,or

3072F SCLK,up to50MHz

Clock divider uses fractional divide D>0,P=1 6.720MHz PLL input frequency/SCL Clock

Frequency400kHz)Clock divider uses integer divide D=0,P=1120MHz DIGITAL INPUT/OUTPUT

Logic Family:3.3V LVCMOS compatible

V IH High level input voltage0.7xDV DD V

0.3x

V IL low level input voltage V

DV DD

I IH High level input current V IN=V DD10μA

I IL low level input current V IN=0V–10μA

V OH High level output voltage I OH=–4mA0.8xDV DD V

0.22x

V OL low level output voltage I OL=4mA V

DV DD

DAC DYNAMIC PERFORMANCE,MEASURED ON DACL and DACR

THD+N at–1dB–90dB

Dynamic range109dB

Signal to noise ratio109dB

Channel separation109dB DAC ANALOG OUTPUT,MEASURED ON DACL and DACR

Output voltage 2.1Vrms

Gain error|%|of FSR2%6%

Gain mismatch,channel to channel|%|of FSR1/2%6%

Bipolar zero error|At bipolar zero|15mV POWER SUPPLY REQUIREMENTS

DV DD Digital Supply Voltage3 3.3 3.6V

AV DD Analog Supply Voltage3 3.3 3.6V Charge-pump supply voltage3 3.3 3.6V

f s=48kHz,Input is Bipolar Zero data1215mA

I DD DV DD supply current at3.3V f s=48kHz,Input is1kHz-1dBFS data1215mA

f s=N/A,power Down Mode0.50.8mA

f s=48kHz,Input is Bipolar Zero data1116mA

AVDD/CPVDD supply current at

f s=48kHz,Input is1kHz-1dBFS data2432mA

3.3V

I CC f s=N/A,power Down Mode0.20.4mA

XSMT=2V,no load,PV CC=12V2035mA PVCC Quiescent supply current

XSMT=2V,no load,PV CC=24V3250mA

XSMT=0.8V,no load,P VCC=12V30μA PVCC Quiescent supply current in

I CC(SD)

shutdown mode XSMT=0.8V,no load,PV

=24V50400μA

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7.8Timing Requirements-I2C Bus Timing

PARAMETER CONDITIONS MIN MAX UNIT

Standard100

t SCL SCL clock frequency kHz

Fast400

Standard 4.7

t BUF Bus free time between a STOP and START conditionμs

Fast 1.3

Standard 4.7

t LOW Low period of the SCL clockμs

Fast 1.3

Standard4

t HI High period of th eSCL clockμs

Fast0.6

Standard 4.7

t RS-SU Setup time for(repeated)START conditionμs

Fast0.6

t S-HD Standard4

Hold time for(repeated)START conditionμs

t RS-HD Fast0.6

Standard0.25

t D-SU Data setup timeμs

Fast0.1

Standard00.9

t D-HD Data hold timeμs

Fast00.9

Standard20+0.1C B1

t SCL-R Rise time of SCL signalμs

Fast20+0.1C B0.3

Standard20+0.1C B1 Rise time of SCL signal after a repeated START condition and after an

t SCL-R1μs acknowledge bit Fast20+0.1C

0.3

Standard20+0.1C B1

t SCL-F Fall time of SCL signalμs

Fast20+0.1C B0.3

Standard20+0.1C B1

t SDA-R Rise time of SDA signalμs

Fast20+0.1C B0.3

Standard20+0.1C B1

t SDA-F Fall time of SDA signalμs

Fast20+0.1C B0.3

Standard4

t P-SU Setup time for STOP conditionμs

Fast0.6

C B Capacitive load for SDA and SCL line400pF

t SP Pulse width of spike suppressed Fast50ns

Noise margin at high level for each connected device(including

V NH0.2V DD V hysteresis)

Figure1.Register Access Timing

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7.9Typical Characteristics

All measurements taken at1kHz,unless otherwise noted.Measurements were made using the TAS5766MDCA EVM.

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Typical Characteristics(continued)

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Typical Characteristics(continued)

OUTPR

OUTNR

OUTPL

OUTNL

( SCLK )Optional

LRCLK BCLK DIN DOUT (GPIO3)

DVDD 3.3V

PVCC 4.5 to 26V

FAULT

SCL SDA

ADR2ADR1XSMT /UVP

GPIO1GPIO2

FSW

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8Detailed Description

8.1Overview

The TAS576xM PurePath?Smart Amp enhance the bass,sound fidelity and increased loudness by driving the speaker to its thermal and mechanical limits.

The TAS576xM contains two BTL class-D amplifiers that supply up to 2x 50W peak power into 4Ω.The amplifier is thermally designed to match the typical speaker so it can withstand high peaks for the time it takes the speaker voice-coil to heat up;it then lowers the average power to safe operating limits.

The wide supply range of 4.5V to 26.4V enables the use of different power supply options from 2-cell Li-Ion batteries to fixed 24-V supply.

The Smart Amp is available with two different class-D amplifier modulations:BD-mode in the TAS5766M;and,1SPW-mode in the TAS5768M.

TI's PurePath?Smart Amp technology allows speakers to be driven with more peak power than their average-power rating,without damage to the speaker by voice coil over excursion or thermal overload.

Sophisticated speaker models (electro-mechanical-thermal)are used as a foundation for the protection and enhancement of the system.This is done by modeling the loudspeaker in the on-chip miniDSP and running an adaptive algorithm that modifies the output based on the modeled conditions of the speaker.

TI provides a PurePath?Console (PPC)GUI,including a TI learning board that measures the loudspeaker parameters.The PPC GUI generates the code for download to the device on boot-up.

Smart Amp technology in the TAS576xM uses information from the SOA (Safe Operating Area)characterization details for the loudspeaker,as well as real-world temperature,and uses this data in an adaptive control algorithm in order to control Smart Bass and Smart DRP (Dynamic Range Preservation).The protection side of the algorithm is also used for thermal protection and mechanical voice coil excursion protection.

8.2Functional Block Diagram

Figure 30.TAS576xM Block Diagram

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8.3Feature Description

8.3.1Smart SOA

The"Safe Operating Area"(SOA)for a loudspeaker is based on its electro-mechanical-thermal model. Depending on a speaker's inefficiency,some of the power is dissipated as heat rather than mechanical/acoustic energy.By understanding the characteristics of the speaker,Smart Amp is able to drive the speaker harder, without causing the speaker to thermally overload;or,suffer voice coil over-exclusion and fail.SMART SOA are parameters that are differentiated by a PPC GUI into coefficients that the algorithm uses.

8.3.2Smart BASS

Smart Bass is an intelligent True Bass Alignment algorithm.Smart Bass uses the combination of the speaker model and a desired target response selected by the user to equalize the speaker in the bass region.This target response is critical for the sound character and the user can apply the same target response to very different speakers and get the same sound.

In conventional adaptive Bass Boost Algorithms,designers need to vary the amount of bass boost whenever the output volume is changed.This approach is very much an"open loop"process.Smart Bass is a new proprietary algorithm that combines:True bass extension(in bandwidth and amplitude)and Psycho-acoustic bass extension, with a smart adaptive control.

Smart Bass varies the mix of True Bass extension and Psycho-acoustic bass extension in real time,depending on the loudspeakers position in its SOA.

Smart Bass dynamically switches between True Bass and Psycho-acoustic extension based on a number of parameters such as:

?Capabilities and properties of the speaker,including Q compensation

?Music type

?Volume setting

?Temperature

?User preferences

?Designer preferences

8.3.3Smart Protection

The two main failure mechanisms for loudspeakers are over temperature and over excursion.By modeling the current state of the speaker,Smart Protection adaptively changes various settings in Smart Amplifier to avoid over temperature and over excursion.Design engineers must first provide details of the loudspeaker(driver and enclosure)into the GUI.From there the appropriate coefficients are generated for the algorithm.

8.3.4Implementing a Real World Design

Traditionally,system developers and hardware engineers use graphic equalizers in trial-and-error fashion to boost the bass for each new speaker until the sound is right(or"good enough"in many cases).However,this typically results in a strange combined response with too much phase shift.This process must be repeated every time a new speaker is selected.The Smart Bass concept uses the GUI to select a desired target response takes the speaker out of the equation.By this approach users can obtain a target response with minimum phase warp and time domain ringing which gives a speedy and tight bass.Conversely,users can select a target response that has lots of ringing to give a classical heavy‘oomph’bass.

OUTP

OUTN

OUTP -OUTN Speaker Current

OUTP

OUTN

OUTP -OUTN Speaker Current

OUTP

OUTN

OUTP -OUTN

Speaker Current

PVCC

No Output

Positive Output

Negative Output

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Feature Description (continued)

8.3.5Modulation Schemes 8.3.5.1BD-Modulation

The TAS5766M uses this modulation,it is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load with short speaker wires.Each output is switching from 0volts to the supply voltage.The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the speaker.The duty cycle of OUTPx is greater than 50%and OUTNx is less than 50%for positive output voltages.The duty cycle of OUTPx is less than 50%and OUTNx is greater than 50%for negative output voltages.The voltage across the load sits at 0V throughout most of the switching period,reducing the switching current,which reduces any I 2R losses in the load.

Figure 31.BD-Modulation

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OUTP

OUTN

OUTP -OUTN Speaker Current

OUTP

OUTN

OUTP -OUTN

Speaker Current

OUTP

OUTN

OUTP -OUTN

Speaker Current

PVCC

No Output

Positive Output

Negative Output

TAS5766M,TAS5768M

https://www.wendangku.net/doc/552022897.html,

SLAS965A –SEPTEMBER 2013–REVISED JUNE 2014

Feature Description (continued)

8.3.5.21SPW-Modulation

The TAS5768M uses this modulation,the 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty in THD degradation and more attention required in the output filter selection.In 1SPW mode the outputs operate at ~15%modulation during idle conditions.When an audio signal is applied one output will decrease and one will increase.The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place through the rising output.The result is that only one output is switching during a majority of the audio cycle.Efficiency is improved in this mode due to the reduction of switching losses.The THD penalty in 1SPW mode is minimized by the high performance feedback loop.The resulting audio signal at each half output has a discontinuity each time the output rails to GND.This can cause ringing in the audio reconstruction filter unless care is taken in the selection of the filter components and type of filter used.

Figure 32.1SPW-Modulation

TAS5766M,TAS5768M

SLAS965A–SEPTEMBER2013–REVISED https://www.wendangku.net/doc/552022897.html, 8.4Device Functional Modes

8.4.1Device Protection System

The TAS576xM contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits,overload,over temperature,and under-voltage.The pin signals if an error is detected according to the fault table,TAS576xM Device Protections.

Table1.TAS576xM Device Protections

TRIGGERING CONDITION LATCHED/ FAULT FAULT ACTION

(TYPICAL VALUE)SELF-CLEARING Over Current Output short or short to PVCC or GND Low Output high impedance Self-clearing Over Temperature T J>150°C Low Output high impedance Self-clearing Too High DC offset DC output voltage Low Output high impedance Self-clearing Under Voltage on PVCC PVCC<4.5V High Output high impedance Self-clearing Over voltage on PVCC PVCC>27V High Output high impedance Self-clearing

8.4.1.1Over Current Protection

The TAS576xM has protection from over current conditions caused by a short circuit or over load on the output stage.The fault is reported on the pin as a low state.The amplifier outputs are switched to a high impedance state when the over current is detected.The outputs are automatically re-engaged after a1.3s off time.

8.4.1.2Thermal Protection

Thermal protection on the TAS576xM prevents damage to the device when the internal die temperature exceeds 150°C.There is a15°C hysteresis on this trip point.When the die temperature exceeds the thermal trip point,the device enters into the shutdown state and the outputs are put in high impedance mode.The outputs are automatically re-engaged after a1.3s off time if the temperature is below the trip point.

8.4.1.3DC Protection

DC protection on the TAS576xM prevents damage to the attached speaker when the output DC voltage exceeds 20%of supply voltage.When the voltage exceeds the trip point,the device enters into the shutdown state and the outputs are put in high impedance mode.The outputs are automatically re-engaged after a0.65s off time if the voltage is below the trip point.

8.4.2Reset and System Clock Functions

8.4.2.1Power-On Reset Function

The TAS576xM includes a power-on reset function shown in Figure33.With DVDD>2.8V,the power-on reset function is enabled.After the initialization period,the TAS576xM is set to its default reset state.

Figure33.Power-On Reset Timing,DVDD=3.3V

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