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UC3845中文资料

UC2842/3/4/5

UC3842/3/4/5 Current Mode PWM Controller

FEATURES

?Optimized For Off-line And DC To DC Converters

?Low Start Up Current (<1mA)?Automatic Feed Forward

Compensation

?Pulse-by-pulse Current Limiting ?Enhanced Load Response

Characteristics

?Under-voltage Lockout With Hysteresis

?Double Pulse Suppression ?High Current Totem Pole

Output

?Internally Trimmed Bandgap Reference

?500khz Operation

?Low R O Error Amp DESCRIPTION

The UC1842/3/4/5 family of control ICs provides the necessary features to im-plement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include un-der-voltage lockout featuring start up current less than 1mA, a precision refer-ence trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The out-put stage, suitable for driving N Channel MOSFET s, is low in the off state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applica-tions. The corresponding thresholds for the UC1843 and UC1845 are 8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every other

clock cycle. BLOCK DIAGRAM

A/B

Note 1: A = DIL-8 Pin Number. B = SO-14 Pin Number. Note 2:Toggle flip flop used only in 1844 and 1845.

4/97

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage (Low Impedance Source). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Supply Voltage (I CC <30mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Limiting Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A Output Energy (Capacitive Load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5μJ Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.3V Error Amp Output Sink Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Power Dissipation at T A ≤ 25°C (DIL-8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Power Dissipation at T A≤ 25°C (SOIC-14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725mW Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Note 1:All voltages are with respect to Pin 5.

All currents are positive into the specified terminal.

Consult Packaging Section of Databook for thermal limitations and considerations of packages.

CONNECTION DIAGRAMS

DIL-8, SOIC-8 (TOP VIEW)

N or J Package, D8 Package PLCC-20 (TOP VIEW) Q Package

SOIC-14 (TOP VIEW) D Package

PACKAGE PIN FUNCTION

FUNCTION PIN N/C1 COMP2 N/C3 N/C4 V FB5 N/C6 I SENSE7 N/C8 N/C9 R T/C T10 N/C11 PWR GND12 GROUND13 N/C14 OUTPUT15 N/C16 V C17 V CC18 N/C19 V REF20

PARAMETER

TEST CONDITIONS

UC1842/3/4/5

UC2842/3/4/5UC3842/3/4/5UNITS

MIN

TYP

MAX

MIN

TYP

MAX

Reference Section Output Voltage T J = 25°C, I O = 1mA 4.95

5.00 5.05 4.90

5.00 5.10V Line Regulation 12 ≤ V IN ≤ 25V 620620mV Load Regulation 1 ≤ I 0 ≤ 20mA

625625mV Temp. Stability (Note 2) (Note 7)

0.2

0.40.2

0.4mV/°C Total Output Variation Line, Load, Temp. (Note 2)

4.9

5.1

4.82

5.18

V Output Noise Voltage 10Hz ≤ f ≤ 10kHz, T J = 25°C (Note2)5050μV Long Term Stability T A = 125°C, 1000Hrs. (Note 2)

525525mV Output Short Circuit -30-100

-180

-30

-100

-180

Oscillator Section Initial Accuracy T J = 25°C (Note 6)47

525747

5257kHz Voltage Stability 12 ≤ V CC ≤ 25V

0.21

%Temp. Stability T MIN ≤ T A ≤ T MAX (Note 2)55%Amplitude V PIN 4 peak to peak (Note 2)

1.7

Error Amp Section Input Voltage V PIN 1 = 2.5V

2.45

2.50 2.55 2.42

2.50 2.58V Input Bias Current -0.3-1

-0.3-2

μA A VOL

2 ≤ V O ≤ 4V 65906590dB Unity Gain Bandwidth (Note 2) T J = 25°C 0.710.71MHz PSRR

12 ≤ V CC ≤ 25V

60706070dB Output Sink Current V PIN 2 = 2.7V, V PIN 1 = 1.1V 2626mA Output Source Current V PIN 2 = 2.3V, V PIN 1 = 5V -0.5-0.8-0.5-0.8mA V OUT High V PIN 2 = 2.3V, R L = 15k to ground 5

656V V OUT Low

V PIN 2 = 2.7V, R L = 15k to Pin 8

0.7

1.10.7

1.1V

Current Sense Section Gain

(Notes 3 and 4) 2.853 3.15 2.853 3.15V/V Maximum Input Signal V PIN 1 = 5V (Note 3)

0.9

1 1.1

0.9

1 1.1

V PSRR

12 ≤ V CC ≤ 25V (Note 3) (Note 2)

7070dB Input Bias Current -2-10-2-10μA Delay to Output

V PIN 3 = 0 to 2V (Note 2)150

300150

300ns

ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for -55°C ≤ T A ≤ 125°C for the

UC184X; -40°C ≤ T A ≤ 85°C for the UC284X; 0°C ≤ T A ≤ 70°C for the 384X; V CC =15V (Note 5); R T = 10k; C T =3.3nF, T A =T J.

Note 2:These parameters, although guaranteed, are not 100% tested in production.Note 3:Parameter measured at trip point of latch with V PIN 2 = 0.Note 4:Gain defined as

A = ? V PIN 1

? V PIN 3

, 0 ≤ V PIN 3 ≤ 0.8V

Note 5:Adjust V CC above the start threshold before setting at 15V.

Note 6:Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.

Note 7:Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

Temp Stability =

V REF (max ) ? V REF (min )

T J (max ) ? T J (min )

V REF (max) and V REF (min) are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.

PARAMETER TEST CONDITION

UC1842/3/4/5UC2842/3/4/5UC3842/3/4/5UNITS

MIN

TYP

MAX

MIN

TYP

MAX

Output Section Output Low Level I SINK = 20mA 0.10.40.10.4V I SINK = 200mA 1.5 2.2

1.5

2.2

V Output High Level I SOURCE = 20mA 1313.51313.5V I SOURCE = 200mA

13.512

13.5V Rise Time T J = 25°C, C L = 1nF (Note 2)5015050150ns Fall Time

T J = 25°C, C L = 1nF (Note 2)

15050

150ns

Under-voltage Lockout Section Start Threshold X842/415161714.51617.5V X843/57.88.49.07.88.49.0V Min. Operating Voltage After Turn On X842/4910118.51011.5V X843/5

7.0

7.6

8.2

7.0

7.6

8.2

PWM Section

Maximum Duty Cycle X842/395971009597100%X844/5

5047

50%Minimum Duty Cycle 0

Total Standby Current Start-Up Current 0.510.51mA Operating Supply Current

V PIN 2 = V PIN 3 = 0V

1117

mA V CC Zener Voltage

I CC = 25mA 303430

Note 2:These parameters, although guaranteed, are not 100% tested in production.Note 3:Parameter measured at trip point of latch with V PIN 2 = 0.Note 4:Gain defined as:

A = ? V PIN 1? V PIN 3

; 0 ≤ V PIN 3 ≤ 0.8V.

Note 5:Adjust V CC above the start threshold before setting at 15V.

Note 6:Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.

ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for ?55°C ≤ T A ≤ 125°C for the

UC184X; ?40°C ≤ T A ≤ 85°C for the UC284X; 0°C ≤ T A ≤ 70°C for the 384X; V CC =15V (Note 5); R T = 10k; C T =3.3nF, T A =T J.

ERROR AMP CONFIGURATION

Error Amp can Source or Sink up to 0.5mA

UNDER-VOLTAGE LOCKOUT

CURRENT SENSE CIRCUIT

OSCILLATOR SECTION

During under-voltage lock-out, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents.

A small RC filter may be required to suppress switch transients .

Peak Current (I S ) is Determined By The Formula

I SMAX ≈

1.0V

R S

High peak currents associated with capacitive loads necessi-tate careful grounding techniques. Timing and bypass capaci-tors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sam-ple the oscillator waveform and apply an adjustable ramp to pin 3.

Shutdown of the UC1842 can be accomplished by two meth-ods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the out-put of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling V CC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.

OUTPUT SATURATION CHARACTERISTICS ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE

OPEN-LOOP LABORATORY FIXTURE SHUT DOWN TECHNIQUES

UNITRODE CORPORATION

7 CONTINENTAL BLVD. ? MERRIMACK, NH 03054TEL. (603) 424-2410 ? FAX (603) 424-3460

OFFLINE FLYBACK REGULATOR

SLOPE COMPENSATION

A fraction of the oscillator ramp can be resistively

summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%.

Note that capacitor, C forms a filter with R2 to suppress the leading edge switch spikes.

Power Supply Specifications

1. Input Voltage

95VAC to 130VA (50 Hz/60Hz)2. Line Isolation

3750V 3. Switching Frequency 40kHz 4. Efficiency @ Full Load

70%

5. Output Voltage:

A. +5V, ±5%; 1A to 4A load Ripple voltage: 50mV P-P Max

B. +12V, ±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max

C. -12V ,±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max

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