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MSM5116805C-70JS中文资料

DESCRIPTION

The MSM5116805C is a 2,097,152-word ￥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5116805C achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5116805C is available in a 28-pin plastic SOJ or 28-pin plastic TSOP.

FEATURES

?2,097,152-word ￥ 8-bit configuration

?Single 5 V power supply, ±10% tolerance ?Input : TTL compatible, low input capacitance ?Output : TTL compatible, 3-state ?Refresh : 4096 cycles/64 ms

?Fast page mode with EDO, read modify write capability

?CAS before RAS refresh, hidden refresh, RAS -only refresh capability ?Multi-bit test mode capability ?Package options:

28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27)(Product : MSM5116805C-xxJS)28-pin 400 mil plastic TSOP (TSOPII28-P-400-1.27-K)(Product : MSM5116805C-xxTS-K)

(TSOPII28-P-400-1.27-L)(Product : MSM5116805C-xxTS-L)

xx indicates speed rank.

PRODUCT FAMILY

MSM5116805C-70

70 ns 130 ns

90 ns 440 mW

550 mW Family

Access Time (Max.)Cycle Time (Min.)Standby (Max.)

Power Dissipation MSM5116805C-50t RAC

50 ns 35 ns t AA

25 ns 20 ns t CAC

13 ns 20 ns

t OEA

13 ns MSM5116805C-6060 ns 110 ns 495 mW 30 ns 15 ns 15 ns Operating (Max.) 5.5 mW

? Semiconductor MSM5116805C

PIN CONFIGURATION (TOP VIEW)

345910111213DQ2DQ3DQ4A10R A0A1A2A32625242019181716DQ7DQ6DQ5A8A7A6A5A42DQ127DQ81V CC 28V SS 28-Pin Plastic SOJ

3459101112132625242019181716227128262524201918171634591011121327228128-Pin Plastic TSOP

(K Type)28-Pin Plastic TSOP

(L Type)

6WE 23CAS 232368A11R 21A9R 21218687RAS 22OE 22227714

V CC 15V SS

1515

14DQ2DQ3DQ4A10R A0A1A2A3DQ1V CC WE A11R RAS V CC DQ7DQ6DQ5A8A7A6A5A4DQ8V SS CAS A9R OE V SS

DQ2DQ3DQ4A10R A0A1A2A3DQ1V CC WE A11R RAS V CC

DQ7DQ6DQ5A8A7A6A5A4DQ8V SS CAS A9R OE V SS Pin Name Function A0 - A8,Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ8

Data Input/Data Output OE Output Enable WE Write Enable V CC Power Supply (5 V)V SS

Ground (0 V)

A9R - A11R Note :

The same power supply voltage must be provided to every V CC pin, and the same GND voltage level must be provided to every V SS pin.

? Semiconductor MSM5116805C

BLOCK DIAGRAM

V CC

DQ1 - DQ8

CAS

A0 - A8

RAS V SS

A9R - A11R

? Semiconductor MSM5116805C

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Voltage on Any Pin Relative to V SS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature

V IN , V OUT Symbol I OS P D *T opr T stg

–0.5 to V CC + 0.5

5010 to 70–55 to 150

Rating mA W °C °C

Parameter

V Unit Voltage on V CC Supply Relative to V SS V CC –0.5 to 7V Recommended Operating Conditions

*: Ta = 25°C

Power Supply Voltage Input High Voltage Input Low Voltage

V CC Symbol V SS V IH V IL

5.00——

Typ.Parameter

4.502.4–0.5*2

Min. 5.50V CC + 0.5*1

0.8

Max.(Ta = 0°C to 70°C)

V Unit V V V

Notes :*1.The input voltage is V CC + 2.0 V when the pulse width is less than 20 ns (the pulse width

is with respect to the point at which V CC is applied).

*2.The input voltage is V SS – 2.0 V when the pulse width is less than 20 ns (the pulse width

is with respect to the point at which V SS is applied).Capacitance

Input Capacitance

(A0 - A8, A9R - A11R)

Input Capacitance (RAS , CAS , WE , OE )Output Capacitance (DQ1 - DQ8)

C IN1Symbol C IN2C I/O

577

Max.pF Unit pF pF

Parameter

(V CC = 5 V ±10%, Ta = 25°C, f = 1 MHz)

———

Typ.

? Semiconductor MSM5116805C

DC Characteristics

Notes : 1.I CC Max. is specified as I CC for output open condition.

2.The address can be changed once or less while RAS = V IL .

3.The address can be changed once or less while CAS = V IH .

I OH = –5.0 mA Output High Voltage I OL = 4.2 mA

Output Low Voltage 0 V ￡ V I ￡ 6.5 V;All other pins not Input Leakage Current

under test = 0 V DQ disable Output Leakage Current 0 V ￡ V O ￡ V CC RAS , CAS cycling,Average Power t RC = Min.Supply Current (Operating)RAS , CAS = V IH

Power Supply RAS , CAS Current (Standby)RAS cycling,Average Power CAS = V IH ,

Supply Current t RC = Min.(RAS -only Refresh)RAS = V IH ,Power Supply CAS = V IL ,

Current (Standby)DQ = enable Average Power CAS before RAS Supply Current (CAS before RAS Refresh)RAS = V IL ,Average Power CAS cycling,

Supply Current t HPC = Min.

(Fast Page Mode)

V OH V OL I LI

I LO I CC1I CC2

I CC3I CC5I CC6

I CC7≥ V CC –0.2 V RAS cycling,Parameter Condition

MSM5116805C-50MSM5116805C-60MSM5116805

C-70(V CC = 5 V ±10%, Ta = 0°C to 70°C)

Symbol

Min.

2.40

–10

–10———

—

Max.V CC 0.4

1010021

100

Min.2.40

–10

–10———

—

Max.V CC 0.4

109021

Min.2.40

–10

–10———

—

Max.V CC 0.4

10802

Unit V V

m A

mA mA mA

Note 1, 2

1, 2

1, 3

? Semiconductor MSM5116805C

AC Characteristics (1/2)

Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time

Fast Page Mode Read Modify Write Cycle Time

Access Time from RAS Access Time from CAS

Access Time from Column Address Access Time from CAS Precharge CAS to Data Output Buffer Turn-off Delay Time Transition Time RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO)RAS Hold Time

CAS Pulse Width CAS Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time

Column Address to RAS Lead Time

Access Time from OE

OE to Data Output Buffer Turn-off Delay Time Refresh Period RAS Hold Time referenced to OE

RAS Hold Time from CAS Precharge t RC t RWC

t HPC t HPRWC t RAC t CAC t AA t CPA t CEZ t T t RP t RAS t RASP

t RSH t CAS t CSH t RCD t RAD t CRP t ASR t RAH t ASC t CAH t RAL

t OEA t OEZ t REF t ROH t RHCP Output Low Impedance Time from CAS t CLZ CAS Precharge Time (Fast Page Mode with EDO)t CP Parameter

MSM5116805C-60MSM5116805

C-70MSM5116805C-50(V CC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13

Symbol

Note 4, 5, 64, 54, 647, 856474

3Max.————60153035—1550—10,000

100,000

——10,000—4530——————

151564—Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

ns ns ms ns ns Min.841102058————001305050777351195070725

—0—730Max.————50132530—1350—10,000

100,000

——10,000—3725——————

131364——Min.1241603078————001507070131013451412501001335

—0—1340Max.————70203540—2050—10,000

100,000

——10,000—5035——————

202064——Min.1041352568————001406060101010401412501001030

—0—1035—Data Output Hold After CAS Low

WE to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time t DOH t WEZ t REZ 7, 87—1515ns ns ns 500—1313500—2020500OE Hold Time from CAS (DQ Disable)t CHO ns 5—5—5—

? Semiconductor MSM5116805C

AC Characteristics (2/2)

Write Command Pulse Width Write Command to CAS Lead Time Write Command to RAS Lead Time Data-in Set-up Time

CAS to WE Delay Time

RAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Hold Time (CAS before RAS )CAS Active Delay Time from RAS Precharge Data-in Hold Time

Write Command Hold Time OE Command Hold Time OE to Data-in Delay Time Write Command Set-up Time RAS to CAS Set-up Time (CAS before RAS )WE to RAS Precharge Time (CAS before RAS )WE Hold Time from RAS (CAS before RAS )RAS to WE Set-up Time (Test Mode)CAS Precharge WE Delay Time

RAS to WE Hold Time (Test Mode)

t WP t CWL t RWL t DS t CWD t RWD t AWD t CSR t CHR t RPC t DH t WCH t OEH t OED t WCS t WRP t WRH t WTS t CPWD t WTH

MSM5116805C-60MSM5116805

C-70MSM5116805C-50(V CC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13

Parameter

Symbol

Max.101010ns ns ns 101010101010Note 111010101110

1010

Min.1010100347949510510101015054Max.ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns Min.7770306742510577713047Max.

Min.1013130449459510513131320064———————————————————

————————————————————

—Read Command Set-up Time Read Command Hold Time

Read Command Hold Time referenced to RAS t RCS t RCH t RRH

99———ns ns ns 000———000———000WE Pulse Width (DQ Disable)t WPE 10ns 710———OE Precharge Time

t OEP 10ns 710———OE Command Hold Time

t OCH 10ns 710———

? Semiconductor MSM5116805C Notes: 1. A start-up delay of 200 μs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device

operation is achieved.

2.The AC characteristics assume t T = 2 ns.

3.V IH (Min.) and V IL (Max.) are reference levels for measuring input timing signals.

Transition times (t T) are measured between V IH and V IL.

4.This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

5.Operation within the t RCD (Max.) limit ensures that t RAC (Max.) can be met.

t RCD (Max.) is specified as a reference point only. If t RCD is greater than the specified

t RCD (Max.) limit, then the access time is controlled by t CAC.

6.Operation within the t RAD (Max.) limit ensures that t RAC (Max.) can be met.

t RAD (Max.) is specified as a reference point only. If t RAD is greater than the specified

t RAD (Max.) limit, then the access time is controlled by t AA.

7.t CEZ (Max.), t REZ (Max.), t WEZ (Max.) and t OEZ (Max.) define the time at which the

output achieves the open circuit condition and are not referenced to output voltage

levels.

8.t CEZ and t REZ must be satisfied for open circuit condition.

9.t RCH or t RRH must be satisfied for a read cycle.

10.t WCS, t CWD, t RWD, t AWD and t CPWD are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If t WCS ≥ t WCS (Min.), then

the cycle is an early write cycle and the data out will remain open circuit (high

impedance) throughout the entire cycle. If t CWD ≥ t CWD (Min.) , t RWD ≥ t RWD (Min.),

t AWD ≥ t AWD (Min.) and t CPWD ≥ t CPWD (Min.), then the cycle is a read modify write

cycle and data out will contain data read from the selected cell; if neither of the above

sets of conditions is satisfied, then the condition of the data out (at access time) is

indeterminate.

11.These parameters are referenced to the CAS leading edge in an early write cycle, and

to the WE leading edge in an OE control write cycle, or a read modify write cycle.

12.The test mode is initiated by performing a WE and CAS before RAS refresh cycle.

This mode is latched and remains in effect until the exit cycle is generated.

The test mode specified in this data sheet is a 2-bit parallel test function. CA8 is not

used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high

level. If any internal bits are not equal, the DQ pin will indicate a low level.

The test mode is cleared and the memory device returned to its normal operating

state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.

13.In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the

specified value. These parameters should be specified in test mode cycle by adding the

above value to the specified value in this data sheet.

? Semiconductor

MSM5116805C

Write Cycle (Early Write)

RAS

CAS

V IH V IL ––

V OH V OL ––

Address

V IH V IL ––WE

V IH V IL ––OE

V IH V IL ––

"H" or "L"

RAS

CAS

V IH V IL ––

Address

V IH V IL ––WE

V IH V IL ––

E2G0100-17-41M TIMING WAVEFORM

Read Cycle

? Semiconductor MSM5116805C

Read Modify Write Cycle

RAS

CAS

V IH V IL ––

V I/OH V I/OL ––

Address

V IH V IL ––WE V IH V IL ––OE

V IH V IL ––

? Semiconductor

MSM5116805C

Fast Page Mode Read Cycle (Part-1)

Fast Page Mode Read Cycle (Part-2)

V IH RAS

Address

CAS

V IL V IH V IL V IH V IL V IH V IL V IH V IL V OH V OL

––

––––V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V OH V

OL "H" or "L"

* : Same Data,

? Semiconductor

MSM5116805C

Fast Page Mode Write Cycle (Early Write)

Fast Page Mode Read Modify Write Cycle

––

––––––V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL

"H" or "L"

–

––

V IH RAS

Address

CAS

––

V IL V IH V IL V IH V IL V IH V IL V IH V IL V I/OH V I/OL

? Semiconductor MSM5116805C

RAS -Only Refresh Cycle

CAS before RAS

Refresh Cycle

V IH V IL RAS

CAS

V IH V

IL V IH V IL WE

V V "H" or "L"

OL OH DQ

Note: OE

, Address = "H" or "L"

V IH V IL RAS

CAS

V IH V IL V IH V IL Address

"H" or "L"

Note: WE , OE = "H" or "L"V OH V OL DQ

? Semiconductor MSM5116805C

Hidden Refresh Read Cycle

Hidden Refresh Write Cycle

––

––––––V IH RAS

Address

CAS

––––V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V

IL "H" or "L"

RAS

CAS

Address

V IH V IL ––V IH V IL ––V IH V IL ––V IH V IL –

–

"H" or "L"

V IH V IL ––

V OH V OL ––

? Semiconductor MSM5116805C Test Mode Initiate Cycle

V IH

V IL

RAS

CAS V IH

V IL

"H" or "L" V OH

V OL

V IH

V IL

Note:OE, Address = "H" or "L"

WE DQ

? Semiconductor MSM5116805C

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

SOJ28-P-400-1.27

Package material Lead frame material Pin treatment

Solder plate thickness Package weight (g)Epoxy resin 42 alloy

Solder plating 5 m m or more 1.30 TYP.

Mirror finish

? Semiconductor MSM5116805C

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage.

TSOP II 28-P-400-1.27-K

Package material Lead frame material Pin treatment

Solder plate thickness Package weight (g)Epoxy resin 42 alloy

Solder plating 5 m m or more 0.51 TYP.

Mirror finish