TI TMS320F28xx 硬件电路设计指导手册
Application Report
SPRAAS1B–August2011 Hardware Design Guidelines for TMS320F28xx and
TMS320F28xxx DSCs Pradeep Shinde
ABSTRACT
TMS320F28xx and F28xxx digital signal controllers(DSCs)include multiple complex peripherals running at fairly high-clock frequencies.They are commonly connected to low level analog signals using an onboard analog-to-digital converter(ADC).This application report is organized as a guide for system level hardware design,parts selection,and schematics design to board layout and helps in avoiding those hardware errors that become costly and time consuming when detected during the system level-debugging phase of the project,using the prototype of the custom board of the project.The issues related to clock generation,JTAG,power supply,interfacing of peripherals with special attention to analog inputs to ADC,general-purpose input/output(GPIO)connections,testing and debug,electromagnetic interference(EMI)and electromagnetic compatibility(EMC)considerations,etc.,are discussed.Each section explains signal routing and layout tips.
Contents
1Introduction (2)
2Typical System and Challenges (2)
3Handling of Different Hardware Building Blocks (4)
4Schematics and Board Layout Design (23)
5EMI/EMC and ESD Considerations (27)
6Conclusion (29)
7References (30)
List of Figures
1Typical TMS320F28xx/28xxx System (3)
2Options for Clock Input (4)
3Typical Crystal Circuit (5)
4Connecting External Oscillator to F280x/F28xxx (6)
5XRS Connection With Watchdog Module (7)
6JTAG Header to Interface Target to a Scan Controller (8)
7JTAG Pin Connections(for a single F28x based system) (9)
8Emulator Connections for Multiprocessor System (10)
9Emulator Daisy-Chain Connections (10)
10ADC Pin Connections for TMS320F28xxx (12)
11Analog Input Impedance Model(F28xxx) (13)
12Typical Buffer/Driver Circuit for ADCIN (13)
13F281x ADC External Reference Schematics (15)
14Typical CAN Transceiver Schematic (17)
15Typical RS-232Transceiver Schematic (17)
16Separate Digital and Analog Supplies (19)
17Suggested Crystal Oscillator Layout (24)
C2000,Code Composer Studio are trademarks of Texas Instruments.
eZdsp is a trademark of Spectrum Digital,Inc.
All other trademarks are the property of their respective owners.
Introduction https://www.wendangku.net/doc/5815650014.html, 18Suggestions for Circuit Separation (25)
19Digital and Analog Grounds and Common Area (26)
20Poor and Correct Way of Bending Traces in Right Angle (27)
List of Tables
114-Pin JTAG Header Signal Descriptions (8)
2Boot-Mode Selection for TMS320F281x Devices (21)
3Boot-Mode Selection for TMS320F280x/F280xx Devices (22)
4Boot-Mode Selection for TMS320F2823x and TMS320F2833x Devices (22)
1Introduction
Digital signal processing(DSP)devices currently have higher central processing unit(CPU)performance (clock rates over100MHz)and integration of advanced high-speed peripherals.Great strides have been made in DSP power reduction through CMOS process technology.These advances have increased the complexity of the DSP board design,which provide more analog challenges than a simple digital design.
Some of the examples of these challenges are:board traces can become transmission lines,floating
unused device pins can consume unnecessary power,and different core and input/output(I/O)voltages need power management techniques.
The TMS320F28xx and TMS320F28xxx are members of the C2000?DSP generation used for
embedded control applications.The current products run at a CPU frequency up to150MHz;future
devices in the family may push this frequency upwards.The CPU frequencies of these devices fall in the radio frequency range.There is also a need to create a design that is debug friendly.How can designers access pins on the Ball Grid Array(BGA)packages?What can system designers do at the design stage to help isolate pieces of the board for debug?And even after the board design is completed,there is a need to have a methodical approach for system debug.
This application report discusses the topics starting from clock circuit,JTAG,interfacing with typical
external devices,power supply and related requirements,thermal considerations,debugging,layout and EMI.The parts selection is also discussed as applicable.Various questions sent by TI’s customers to the Central Support Team formed a good base for this document.
NOTE:The current revisions of all device-specific data manuals take precedence over the
information/data in this report.
2Typical System and Challenges
A typical C2000-based control or data acquisition system is shown in Figure1.Normally,it is powered
from the AC mains output;however,in some applications it is powered from a battery.Typically,the DSC is surrounded by power management circuits,reset/clock generator,signal conditioning circuits(for analog inputs using op-amps),driver circuits for control output with pulse width modulation(PWM),user interface, transceivers on serial communication ports,external memory,or other devices with parallel interface over XINTF or serial Flash over inter-integrated circuit(I2C),and other supporting circuitry.
2Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs SPRAAS1B–August2011
https://www.wendangku.net/doc/5815650014.html, Typical System and Challenges
A External interface(XINTF)is available on the F2812and F2833x devices only
B The maximum number of signals for any interface is device dependent.
Figure1.Typical TMS320F28xx/28xxx System
TMS320F28xx/F28xxx devices include various onboard peripheral blocks.Though these peripherals save adding external interface parts and make it flexible to meet the system level requirements for different
applications,it is challenging to design the hardware to operate all these peripherals and the DSC to
achieve the highest performance with optimum reliability.Therefore,designing a custom board,which
should work as desired on the first attempt,is a real challenge.
With the CPU frequency up to150MHz,there are many internal functional blocks onboard operating at various frequencies.Any signal above10MHz can create a signal integrity issue if proper care is not
taken during schematics and layout design.In addition,there are low-level analog signals on the same board.EMI/EMC and electrical noise issues should be considered before starting the board design.
Overall design must be debug friendly.
NOTE:This report considers the families TMS320F281x,F280x,F280xx and F2833x which are
active parts at the time of publication.Future revisions will include the data on newer parts.
CPU Clock (SYSCLKOUT)
3Handling of Different Hardware Building Blocks
The following sections discuss each building block of the entire design.
3.1Clocking Circuit
The F28x devices offer two options for clock generation:using an onboard crystal oscillator or feeding the external clock to the XCLKIN pin.The frequency of this basic input clock,using an internal oscillator,is in the range of 20MHz –35MHz.The on-chip phase-locked loop (PLL)can be set to multiply the input clock to provide a wide variety of system clock frequencies.Each time you write to the PLLCR register to configure the PLL multiplier,the PLL will take 131,072cycles to lock.While the PLL is in the process of locking,the device frequency may experience a large swing at the start and end of the locking process.These two potentially abrupt frequency transitions may cause power rail fluctuations.Careful design of the power-supply is needed in order to prevent these transitions from impacting the device operation.Once the PLLCR register is written to,it is recommended that a tight loop be executed until the PLL relocks to the new frequency.Once the PLLCR is written to,writing to the PLLCR again,even with the same multiplier will cause these frequency swings and potential power supply swings.The frequency of the external clock fed to the CLKIN pin can be as high as the maximum frequency at which the CPU can operate (SYSCLKOUT).The CPU can operate within the wider range of that frequency.Further clock signals for all the peripherals are derived from the CPU clock.
In general,the highest possible frequency for the clock signal is selected to achieve maximum execution speed.However,the other aspect is power consumption because it increases linearly with the CPU clock frequency.For more information regarding the current/power consumption graphs,see the Electrical Specifications sections in the TMS320F2810,TMS320F2811,TMS320F2812,TMS320C2810,
TMS320C2811,TMS320C2812,Digital Signal Processors Data Manual (SPRS174),TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801,and TMS320F2801x DSPs Data Manual (SPRS230),TMS320F28044Digital Signal Processor (SPRS357),and the TMS320F28335,TMS320F28334,TMS320F28332Digital Signal Controllers (DSCs)Data Manual (SPRS439).
A The F281x parts have a common pin for the X1and XCLKIN signals.
Figure 2.Options for Clock Input
4Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs
SPRAAS1B –August 2011
C(Load) =
C1 x C2C1 + C2
3.1.1Internal (Crystal/Resonator)vs.External Oscillator
The first consideration for the clock generation circuit is whether to use the on-chip oscillator (crystal or resonator)or an external clock source,from an external oscillator or any other source in the system.A primary concern of this choice is often cost;a crystal and its few associated components used with the internal oscillator are usually cheaper than an external oscillator.Therefore,using a crystal,along with the internal device oscillator circuit may be a good option,unless the same clock must be provided to other devices in the system.Since making any additional connections to the crystal circuit is not recommended,the only choice would be to use F28xx clock output (XCLKOUT)signal or to generate it using a PWM block to clock other devices in the system.However,the DSP is not usually run at the crystal frequency,so if other devices in the system require this same clock,using an external oscillator is simpler and generally the preferred approach.
3.1.1.1Using Crystal/Resonator as Clock Source
The on-chip oscillator circuit of all the F28xx/F28xxx devices enables a crystal/resonator connected to the X1and X2pins.The X1pin is referenced to the core digital power supply (V DD ).The X2pin is the internal oscillator output.The crystal is connected across the X1and X2pins.If the X2pin is not used,it must be left open.The F281x devices have a common pin for the X1and XCLKIN signals.
Figure 3shows the external circuitry and connections required for using the internal oscillator,along with the equation defining the relationship between the manufacturer ’s specified crystal load capacitance C LOAD ,formed by two external capacitors C1and C2.The external clock mode control inputs specify whether the internal oscillator is enabled or disabled.When the internal oscillator is used,choose the clock-mode selection that enables the internal oscillator.
Figure 3.Typical Crystal Circuit
The effective load capacitance,C LOAD ,appears to the crystal circuit as the series combination of C1and C2.Correct C LOAD is important for proper operating frequency.Crystals are available with a variety of C LOAD values.However,the internal DSC oscillator will not start and run reliably with too high or too low of a C LOAD value.For more information,check the specifications from the crystal vendor ’s data sheets.It is
recommended to select a fundamental mode parallel resonant type crystal having a C LOAD of around 12pF and ESR of 30to 60?.
The actual discrete values required for C1and C2are generally up to 5pf below the calculated load capacitance due to PCB traces and the DSC input pin's stray capacitances;the board layout is quite important.If precise frequency control is required,the exact discrete capacitor values can be determined by varying the capacitor values and performing precision frequency measurements using a frequency counter.
NOTE:It is recommended that you have the resonator/crystal vendor characterize the operation of
their device with the DSC chip.The resonator/crystal vendor has the equipment and
expertise to tune the tank circuit.The vendor can also advise you regarding the proper tank component values for proper start-up and stability over the entire operating range.
External Clock Signal (Toggling 0-V )
DDIO XCLKIN
X1
X2
NC
a) Using a 3.3 V External Oscillator
DD b) Using a 1.8 V/1.9 V External Oscillator
3.1.1.2Using External Oscillator
To select a proper external oscillator,consider the specifications such as frequency,stability,aging,voltage sensitivity,rise and fall time,duty cycle,and signal levels.Some designs may have to consider clock jitter.Note that only F280x and F28xxx devices can accept an external clock signal having an
amplitude of V DD (1.8V/1.9V)or 3.3V.The clock signal for F281x parts should toggle between 0and V DD .Connect the output of the external oscillator to the F280x and F28xxx parts as shown in Figure 4,based upon the level.It is important to connect X1or XCLKIN to ground as shown.If they are left open,the frequency of CLKOUT will be incorrect and the DSC may not work properly.
Figure 4.Connecting External Oscillator to F280x/F28xxx
The F281x devices select the external clock oscillator part that toggles between 0-V DD (0–1.8V/1.9V).
NOTE:If you are using a 3.3V external oscillator for an F281x system,use a 3.3V to 1.8V/1.9V
voltage translator device equivalent to TI ’s SN74LVC1G14-SN74LVC1G14Single Schmitt-Trigger Inverter Data Sheet (SCES218).
3.1.2Loss of Input Clock -Limp Mode
The PLL still issues a limp-mode clock if the input clock,OSCCLK,is removed or absent.The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1MHz -5MHz.Limp mode is not specified to work from power-up,but only after input clocks have been present.In PLL bypass mode,the limp mode clock from the PLL is automatically routed to the CPU if the input clock is removed or
absent.The watchdog counter stops decrementing with the failure of the input clock and does not change with the limp-mode clock.These conditions could be used by the application firmware to detect the input clock failure and initiate a necessary shut-down procedure for the system.
NOTE:Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSC is held in reset should the input clocks ever fail.For example,an R-C circuit can be used to trigger the XRS pin of the DSC,should the capacitor ever get fully charged.An I/O pin can be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged.Such a circuit would also help in detecting failure of the Flash memory and the V DD3VFL rail.
3.1.3XCLKOUT
The output clock signal,derived from SYSCLKOUT,is available on XCLKOUT as a general-purpose clock source,which can be used for external wait-state generation.It also serves as a Test Point to check the CPU clock frequency and to ensure that the PLL is working properly.At reset,XCLKOUT =SYSCLKOUT/4;but it can be set the same as or ?of SYSCLKOUT.
The XCLKOUT signal is active when reset is active.Since XCLKOUT should reflect SYSCLKOUT/4when reset is low,you can monitor this signal to detect if the device is being properly clocked during debug.There is no internal pullup or pulldown on the XCLKOUT pin.The drive strength of this pin is 8mA.If XCLKOUT is not being used,it can be turned off by setting the CLKOFF bit to 1in the XINTF Configuration Register (XINTCNF2).This is an output pin of the CMOS device and should not be terminated to ground even if it is not used.
6Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs
SPRAAS1B –August 2011
Internal 3.2Reset and Watchdog
The XRS pin facilitates the device reset (in)and watchdog reset (out)signals.A warm reset pulse-width is specified as eight times the oscillator clock (OSCCLK)period;however,the power on reset ’s pulse-width has to be much longer to account for the time required for V DD to reach 1.5V (to enhance Flash reliability)and the oscillator start-up period of 10mS (nominal).You may prefer to keep this duration in excess of 100ms to overcome any other related delays.
During power down,the XRS pin must be pulled low at least 8μs prior to V DD reaching 1.5V to enhance Flash reliability.
Whenever the 8-bit watchdog up counter has reached its maximum value,the watchdog module
generates an output pulse 512oscillator clocks wide.Note that the WDRST signal outputs the reset signal over the XRS pin.The output buffer of this pin is an open-drain with an internal pullup (100uA,typical);it is recommended that the open-drain device drive this pin.Figure 5illustrates a block diagram of the watchdog module.
Figure 5.XRS Connection With Watchdog Module
For the XRS pin,simple R-C filters are often adequate.However,ESD protection diodes like CM1215from California Micro devices are even better.For more information,see https://www.wendangku.net/doc/5815650014.html,/products/dds.php?product=cm1215.
3.3Debug interface/JTAG and EMU Signals
For target-level debug interface,all F28xx/F28xxx devices use five of the standard IEEE Standard
1149.1–1990,IEEE Standard Test Access Port and Boundary-Scan Architecture (JTAG)signals (TRST,TCK,TMS,TDI,and TDO)and two of the TI extensions (EMU0and EMU1).
TMS TDI PD (V )CC TDO TCK_RET TCK EMU0
TRST GND No Pin (Key)GND GND GND EMU1
Header dimensions:
Pin-to-pin spacing: 0.100 in. (X,Y)Pin width: 0.025 in. square post Pin length: 0.235 in. nominal
The pin assignment for the JTAG header is defined in Figure 6.
Figure 6.JTAG Header to Interface Target to a Scan Controller
As shown in Figure 6,the header requires more than the five JTAG signals and TI extensions.It also
requires a test clock return signal (TCK_RET),target supply (V CC ),and ground (GND).TCK_RET is a test clock out of the scan controller and into the target system.The target system uses TCK_RET if it does not supply its own test clock,in which case TCK simply would not be used In many target systems.TCK_RET is connected to TCK and used as the test clock.
The drive strength of TDO,EMU0and EMU1pins is 8mA.
The JTAG connector should be placed within 6inches or less (preferably 2")from the corresponding pins on the DSC.If this is not possible,signal buffers should be added.The pin descriptions are shown in Table 1.
Table 1.14-Pin JTAG Header Signal Descriptions
Emulator Signal Descriptions State
Target State
EMU0Emulation pin 0I I/O EMU1Emulation pin 1I
I/O
GND Ground
PD (V CC )
Presence detect.This signal indicates that the emulation cable is connected I
O
and that the target is powered up.PD should be tied to V CC in the target system.
TCK Test clock.TCK is a clock source from the emulation cable pod.This signal O I can be used to drive the system test clock.
TCK_RET Test clock return.Test clock input to the emulator.This signal can be a I O buffered or unbuffered version of TCK.TDI Test data input O I TDO Test data output I O TMS Test mode select O I TRST
Test reset
O
O
8Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs
SPRAAS1B –August 2011
Figure7.JTAG Pin Connections(for a single F28x based system)
3.3.1Daisy Chaining With JTAG Ports of Other Devices on the Board
If your board contains more than one device with JTAG ports,a single JTAG connector can be shared between them.
While the connection to the JTAG header may be the same,the scan chains used for emulation purposes are different from those used for boundary scan.Various serial scan chains,through which the information can be scanned,are internal to the processor.The emulator card controls which scan chain is used and what information is contained in each scan chain.Traditionally referred to as the Scan Manager,this
function assumes the task of controlling all information scanned into and out of the various processors in the scan chain.Furthermore,it directs this information to and from the various debugger windows.
A basic rule to remember is that all data must be scanned serially through all devices while connecting a
common JTAG connector to multiple ports.
One method is shown in Figure8.
Figure8.Emulator Connections for Multiprocessor System
Another configuration is to connect the ports in daisy-chain fashion,as shown in Figure9.
A Target clock and target clock return connections not shown
Figure9.Emulator Daisy-Chain Connections
When debugging systems that have more than one TI device defined,you are required to use the parallel debug manager(PDM),which provides a method of synchronous debugging of your multiprocessor
application.If you have configured a multiprocessor system within CC_Setup,the PDM is automatically invoked when you start CC_App.
For additional information on the emulation features see Emulation Fundamentals for TI's DSP Solutions (SPRA439),the Emulation Features section in TMS320C28x DSP CPU and Instruction Set Reference
Guide(SPRU430),and the Designer Considerations for Using the XDS510Emulator section in the
TMS320F/C24x DSP Controllers CPU and Instruction Set Reference Guide(SPRU160).
10Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs SPRAAS1B–August2011
3.3.2Important Careabout With JTAG and EMU Pins
Important issues are discussed in this section.The signal description section of every C2000platform of data sheets describe the termination requirements on these pins.Whether you plan to use JTAG interface or not,you need to be sure that these signals will not interfere when the systems are running in the field.
The first thing to note is the function of the TRST pin,which is a JTAG test reset pin.
NOTE:The TRST pin when driven high,gives control of the device operations to the scan system
(emulator).This pin has an internal pulldown and should never be pulled high.The internal
pulldown is not very strong so that it will not load the scan system.In a noisy environment,
this pin can pick up a strong noise signal,putting the device in test mode.It is highly
recommended to add an external pulldown resistor.The value of this resistor is based on the
drive strength of the debugger pods used.A2.2-k?resistor generally offers adequate
protection.
Many simple looking designs have the presence of electrical noise.For example,driving a little larger load creates a voltage spike on supply rails.The I/O and core power supply can have a good amount of ripple and noise;otherwise,the board layout may not be noise friendly.Any spike picked up by the TRST pin will put the device in test mode and it will appear as if the DSC were suddenly hung while running the
application code.To avoid this situation,terminate the TRST pin as mentioned in the note above.
Similar to the TRST pins,termination on EMU0and EMU1pins are important.The data sheets
recommend pulling these pins high using a resistor between2.2k to4.7k?s.You should make sure that the value you select will not load the debugger pod.If there is presence of higher noisy conditions,the value of the PD resistor on the TRST pin could be lowered further.
Add bypass caps(0.01μF)to the critical JTAG signals,which are TRST,EMU0,and EMU1.
3.4Interrupts and GPIOs Pins and Onboard Peripherals
The following sections discuss the precautions required while interfacing GPIO/interrupt pins and
onboard-peripherals.
3.4.1GPIO Pins
The GPIO pins are multiplexed for two or more signals;each GPIO pin could be used to implement digital I/O or peripheral I/O.To help the routing of signals or if you need to use the pin for a different multiplexed option,some of the peripheral signals are multiplexed at two different sets of pins.
The drive strength(sink/source current)of the output buffer on GPIO pins is typically4mA(unless
otherwise noted).The maximum toggling frequency of the GPIO pin is20MHz for the F281x devices and 25MHz for the F280x/F28xxx devices.
Note that at reset,the GPIO pins are defined as input(default condition).A commonly asked question is what to do with unused GPIO pins?All of the F28x devices are built around CMOS technology.Therefore, the rules and care,as applied for CMOS input(high impedance)or output,are applicable.The options are either configured as outputs and left unconnected or define them as input with proper termination on the
pin.A pullup or pulldown resistor(1k?to10k?)to V
CC or GND puts them in defined state.Any input that
is allowed to float can bias the input buffer in a linear mode in which excessive power supply current can be drawn;in most cases,this is undesirable.Theoretically,non-critical inputs could be defined as output and left floating in the interests of not wasting power;however,it is generally a good idea to keep them in default input mode and tie them off.
When tying off unused inputs,several different approaches can be used.If multiple inputs require being pulled up,this can be done(depending on input current)with a single resistor as long as the resistor value is low enough(do not forget Ohm's Law).This is also assuming none of these inputs ever get driven low. Note that if too many inputs are pulled high with a weak resistor,the result can be that a solid logic level is not maintained.If this level is not maintained,the device may interpret that one or more of the pins are in a logic low state.This has caused serious problems in many systems.
Any input that is normally pulled high but sometimes must be driven low,for a system test or other reasons,should be pulled up with its own resistor(unless you want to drive all these inputs low).
ADCLO ADCREFP and ADCREFM should not be loaded by external circuitry
ADC Analog Power Pin (1.8 V)ADC Analog Power Pin (1.8 V)ADC Analog Ground Pin ADC Analog Ground Pin ADC Analog Power Pin (3.3 V)ADC Analog Ground Pin ADC Analog Power Pin (3.3 V)ADC Analog I/O Ground Pin
ADC 16-Channel ADC Ground any inputs required to be tied to logic zero unless the input needs to be forced high,for a system test or other https://www.wendangku.net/doc/5815650014.html,e a strong pulldown if the input is normally low but sometimes needs to be forced high.If you are sure that a particular GPIO pin will never be used,a good practice is to pull it to ground.Also,note that some pins have internal pullups/pulldowns controlled by software,and may not be
initialized to the desired state after reset.The register bits that control these functions should always be properly initialized in software,if necessary.3.4.1.1
Driving High Value Load
Use the appropriate buffer devices if you need to drive the load on the GPIO pins in excess of their ±4mA capacity.Examples of this load are DC relay,LEDs,etc.Consider the following TI parts:?±24mA output drive:SN54AC241,SN74AC241
SN54AC241,SN74AC241Octal Buffers/Drivers With 3-State Output Data Sheet (SCAS513)?High voltage,high-current load:ULN2xxx transistor arrays (50V,500mA typical)
ULN2001A,ULN2002A,ULN2003A,ULN2004A,ULQ2003A,ULQ2004A,High-Voltage High-Current Darlington Transistor Array Data Sheet (SLRS027)3.4.2
Analog-to-Digital Converter (ADC)
The ADC peripheral requires few external components for biasing of internal band gap reference and filtering noise on reference voltage signals.The schematic in Figure 10shows these parts and their connections.
A TAIYO YUDEN LMK212BJ225MG-T or equivalent
B External decoupling capacitors are recommended on all power pins.
C
Analog input pins must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 10.ADC Pin Connections for TMS320F28xxx
Make sure that these components values are correct and that they are placed close to the respective pins.
12Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs
SPRAAS1B –August 2011
Source Signal
Typical Values of the Input Circuit Components:Switch Resistance (R ):Sampling Capacitor (C ):Parasitic Capacitance (C )Source Resistance (R )
on h p s 1 k 1.64 pF 10 pF 50ΩΩ
V IN
3.4.2.1Driving ADC Input Pins
The front end circuits of the ADC block is two sets of an 8-channel multiplexer followed by sample and hold circuits.Note that each input analog signal sees the load from the ADCIN pin as shown in Figure 11.C h is the sample capacitor and R on is the ON resistance of the multiplexer path.C p is the parasitic capacitance associated with the ADCIN pin.
Figure 11.Analog Input Impedance Model (F28xxx)
It is a good practice to use an op-amp driver circuit for signal conditioning of input analog signals and as a buffer.The op-amp isolates the ADC,acts as a low-impedance source to charge the sample capacitor,and can be configured as a unity gain buffer or level shifter.It provides low/stable output impedance and protects the ADC inputs.Figure 12shows a commonly used ADC driver circuit configuration for DC and low-frequency signals.
Figure 12.Typical Buffer/Driver Circuit for ADCIN
Though external R IN and C IN form a low-pass filter,they actually serve as a flywheel in the presence of the current pulses created by the ADC ’s input circuitry.R IN isolates the ADC from the amplifier;however,during sampling,C IN acts as a reservoir and helps in signal stability.The optimum capacitor value is 20–30pF (CIN >=10*CSH)and the resistor value is selected to meet the speed or bandwidth requirement;but it should not typically exceed 100?.
V PS is the residue from the previous sample.Ideally,it would be zero,but in reality if you are sampling back to back,it approaches the previously sampled value.R SW is the on-resistance of MUX.During
acquisition,S1is closed -S2is open.The sampling capacitor C SH (1.64pF)is charged through the switch resistor R SW (1K Ω)and R IN for the period S1is closed;this period is controlled by ACQ_PS (derived from ADC Clock)setting.This action of charging the capacitor is shown in the following equation:
Vc (t)=Vin ×(1–e t )
For the internal RC circuit,formed by R
SW and C
SH
,this settling time is9ns,much smaller than the
minimum sampling window of40ns at12.5MSPS.However,this time period is much longer for the external RC circuit.Also consider the additional trace capacitance and pin's parasitic capacitance while calculating the time constant of RC circuit.It should be met by a higher value for ACQ_PS and/or a lower sampling frequency that meet the system requirements.
NOTE:It is necessary to maintain the analog input voltage applied to the ADCIN pins within
0V–3.0V range.These analog signals pass through the multiplexer network first.Any
voltage above V
DDA +0.3V or below V
SS
–0.3V will bias the multiplexer in an undesired way,
giving the wrong values for other channels.To achieve accurate values,the sample
capacitor should be charged to within?LSB of the final value.
Here are a few suggestions for the low-noise/low-offset,single-supply op-amp to drive the ADC input
circuit.
?OPA4376-OPA376,OPA2376,OPA4376Precision,Low Noise,Low Quiescent Current,Operational Amplifier Data Sheet(SBOS406)
?OPA4343-OPA343,OPA2343,OPA4343Single-Supply,Rail-to-Rail Operational Amplifiers microAmplifiers Series(SBOS090)
?TLV2474-TLV2470,TLV2471,TLV2472,TLV2473,TLV2474,TLV2475,TLV247xA Family of600μA/CH2.8MHz Rail-to-Rail Input/Output High-Drive Operational Amplifiers With Shutdown(SLOS232) For additional information on the ADC peripheral,see An Overview of Designing Analog Interface With TMS320F28xx/28xxx DSCs(SPRAAP6).
3.4.2.2Reference Voltage–Internal vs.External
All the ADC blocks of the F28xx/F28xxx devices have internal bandgap reference voltage source.The
only reason for going for external voltage source is the temperature stability.The temperature coefficient of the internal voltage source is50PPM/°C.
If your end product requires good ADC accuracy over a wider temperature variation,you need to select an external reference voltage source that requires lower value temperature coefficient.While doing so,it is important that you use a low output impedance op-amp buffer so that signal is stable during the
conversions.Do not connect this node to any other input or load circuit on the design.It is important that noise on the reference input pins be less than100μV.
?Connecting an external voltage reference for the F280x,F280xx and F2833x devices:The ADC blocks of these parts require a single reference voltage input to be connected between the ADCREFIN and
ADCLO pins.Based on customer application requirements,the ADC logic can be supplied by an
external voltage reference.The F280x ADC accepts2.048V,1.5V,or1.024V on the ADCREFIN pin.
You also need to set a two-bit field of the ADC Reference Select Register(ADCREFSEL)according to the voltage level of the external source to enable the external reference and determine the reference
source selected.
The voltage of2.048V was chosen to match the industry standard reference components;1.5V and
1.024V are alternatives.
NOTE:Selecting any of the three voltage levels(for external reference)does not change the analog
input voltage range.It remains0V–3.0V irrespective of the reference voltage level.
?Connecting an external voltage reference for F281x devices:The F281x family parts require two inputs for the ADC reference:ADCREFP and ADCREFM.The voltage difference ADCREFP–ADCREFM
should be1.00±0.05V.
14Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs SPRAAS1B–August2011
F
(A)
ADCREFP
0.47μAVCC_3V
1 KΩ
F
(A)
ADCREFM
Figure 13shows a typical schematic for connecting the external reference voltages for F281x devices.
A
Do not load ADCREFF and ADCREFM pins with any other circuitry.Connect the appropriate value,low ESR filter capacitors to these pins.
Figure 13.F281x ADC External Reference Schematics
The recommended Texas Instruments voltage reference parts are REF3120(10PPM typical,20PPM max)and REF5020(3PPM max).
REF3112,REF3120,REF3125,REF3130,REF3133,REF314015ppm/°C Max,100μA,SOT23-3Series Voltage Reference Data Sheet (SBVS046)
REF5020,REF5025,REF5030,REF5040,REF5045,REF5050Low-Noise,Very Low Drift,Precision Voltage Reference Data Sheet (SBOS410)3.4.2.3
ADC Calibration
Like all ADCs,the inherent gain and offset errors are associated with the F28xx/F28xxx ADCs.Some applications may require corrections to improve the accuracy,i.e.,improving ENOB.
The F281x ADC has a maximum offset error of ±80LSB and a maximum gain error of ±200LSB.The maximum values for both gain and offset error for F280x/F280xx parts are ±60LSB.The newer F2833x parts have improved these specifications to an offset error of ±15LSB and a gain error of ±30LSB.Furthermore,F280x/F280xx and F2833x parts include the ADC Offset Trim Register (ADCOFFTRIM),which is useful to correct the offset error.For the ADC on F2833x,this register also helps in getting the complete input voltage range of 0V –3V,after offset correction.This family also includes the
ADC_cal()routine programmed into the OTP memory by the factory.The Boot ROM automatically calls the ADC_cal()routine to initialize the ADCREFSEL and ADCOFFTRIM registers with device-specific calibration data.
For more information on calibration procedures,see F2810,F2811,and F2812ADC Calibration
(SPRA989)(for F281x)and TMS320280x and TMS3202801x ADC Calibration (SPRAAD8)(for F280xx).These application reports also include the schematics of additional circuitry and associated code.3.4.2.4
Unused ADC Input Pins
Make sure that all unused ADC inputs are terminated to the analog ground (V SS1AGND /V SS2AGND );these pins are always defined as input .Having high-input impedance if left open,these pins can pick up noise signals and affect the performance of other inputs to the ADC through the multiplexer.
3.4.2.5ADC Connections if the ADC is Not Used
It is recommended to keep the connections for the analog power pins -even if the ADC is not used.The following is a summary of how the ADC pins should be connected if the ADC is not used in an application:?V DD1A18/V DD2A18–Connect to V DD ?V DDA2,V DDAIO –Connect to V DDIO
?V SS1AGND /V SS2AGND ,V SSA2,V SSAIO –Connect to V SS ?ADCLO –Connect to V SS
?ADCREFIN –Connect to V SS
?ADCREFP/ADCREFM –Connect a 100-nF cap to V SS
?ADCRESEXT –Connect a 22-k ?resistor (very loose tolerance)to V SS ?ADCINAn,ADCINBn -Connect to V SS
When the ADC is not being used,disable the clock to the ADC module to save power.3.4.3
Control Peripherals -PWM,CAP,QEP and Event Manager
The event manager of the F281x devices and the ePWM,eCAP,and eQEP blocks of the F280xx/F28xxx devices account for generating and/or interfacing the PWM and pulse signals for various control
applications.As mentioned previously,corresponding GPIO pins are set to select required interface via the GPIO MUX Register (GPxMUX).The current sink/source capacity of these pins is ±4mA for most F28x parts.You need to add an appropriate high-power circuit to enhance this capacity to drive the load and remember that at reset these GPIO pins are defined as input with the internal pullups enabled,except for the pins providing PWM output for which they are disabled.This condition remains for a short duration until the ports are initialized.Normally,there is no need for any external PU/PD resistor,unless it is mandatory for your schematic design.
The switching power circuits and other interface circuits for these peripherals are dependent on the goals of each design.This part of your circuit (and board)switches fairly high power,so pay close attention to the placement of these parts and the related board layout.3.4.4
Serial Communication Ports (McBSP,I2C,SPI,SCI and CAN)
I2C and serial peripheral interface (SPI)are board-level interfaces that are connected to other devices on the board or system.These signals normally run directly.Pay close attention to the drive capability and trace length,which depends on the selected frequency of these signals.SCLA and SDAA pins of the I2C link are required to be pulled high using ~5K Ωresistors.
However,serial communications interface (SCI)and controller area network (CAN)interfaces are used to connect to different systems running under another processor.These ports require specialized transceiver parts to transform the signal into the required electrical signaling (single-ended RS232or differential for CAN and RS422/RS485),so that they can interface with the ports on the other devices per defined
protocol.The CAN ports will not show any activity on the CANRX or CANTX pins during the transmission unless this port is connected to an active port on the other end through respective transceivers.
16Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs
SPRAAS1B –August 2011
End Terminator
Figure14.Typical CAN Transceiver Schematic
C33
0.1μF
Figure15.Typical RS-232Transceiver Schematic
To select these parts for your design,go to the TI website:https://www.wendangku.net/doc/5815650014.html,→Interface.
3.4.5Interfacing the XINTF
F2812and F2833x devices are supported with this non-multiplexed asynchronous bus to add an external parallel device.This interface is primarily used to expand system memory;generally RAM.These memories can be fast,running at or near the processor speed,or slow,many times slower than the processor speed,and can be asynchronous like SRAM,ROM,or Flash.When interfacing to memory,reference the device-specific data sheet to make note of the timing requirements from both a DC and an AC perspective and the loading conditions such as whether buffers will be required to ensure at speed access.Other devices that can be present on the parallel bus are first-in-first-out (FIFOs),digital logic and parallel A/D and D/As.If the parallel device is slower than the processor speed the software wait states may be generated,or in the case of a very slow memory or other parallel device,whether a hardware ready signal (XREADY)must be used to allow the slow memory to interface seamlessly to the fast processor.
Place the devices connected to the XINTF close to the DSC so that these bus signals run over short
traces.Some designs may require connecting multiple memory devices to the XINTF.A good approach to evaluate the capacitive loading is to do IBIS model analysis for the 281x/2833x and memory devices.This analysis is the best way to evaluate the design.
The XINTF is designed with a high-performance buffer to support a 35pf load.For more information
regarding the drive strength for all pins,see the device-specific data sheet.Make sure the address,data,and control signals are balanced with a minimum pf load.Consider faster memories or longer wait states to account for slew on the control signals.
3.5Power Supply
The F28xx/F28xxx devices have multiple power supply pins.This includes:?CPU core supply (V DD )?I/O supply (V DDIO )
?ADC analog supply pins (V DDA2,V DDAIO )
?ADC core supply (V DD1A18,V DD2A18)–for F280x/280xx ?Flash programming voltages (V DD3VFL )?Supply ground (V SS ,V SSIO )
?ADC analog ground (VSSA2,VSSAIO)
?ADC analog/core ground (V SS1AGND ,V DD2AGND )
All the power supply pins must be connected for proper operation.All these devices have multiple supply pins for the core,I/O,and ADC/analog supplies.All such pins must be connected to the proper supply voltage for proper operation.Do not leave any of the supply pins unconnected.The voltage level for I/O pins is 3.3V;whereas,the core supply voltage is either 1.8V or 1.9V.For more information,see the Electrical Specifications section of the device-specific data manuals.They also have Flash programming supply pins.These pins have to be connected to 3.3V rail,particularly for in-circuit flashing applications.
3.5.1Digital I/O and Analog 3.3V Supplies
For proper operation of the A/D converters,a noise-free analog supply is a must.Any noise on the analog supply voltage rail severely degrades the performance of the converter,leading to inaccurate and/or unstable converted counts.Digital circuits,especially CMOS circuits,draw more current while switching.When a node is switched from one logic level to the other,the capacitance associated with that node must be charged or discharged;current must be drawn from the supply to do this.On the other hand,static circuitry draws significantly smaller amounts of current.Therefore,for a complex digital circuit like any digital signal controller,the current drawn is highly irregular;this type of current draw leads to a lot of noise on the supply rail.
18Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs
SPRAAS1B –August 2011
Analog Ground Analog Supply
Digital Ground
Digital Supply
Figure 16.Separate Digital and Analog Supplies
If the analog circuitry is powered from a power supply like that mentioned above,there may be significant performance degradation.For example,the conversion results obtained from an analog-to-digital converter may bounce around,even though the voltage at the input of the ADC remains constant.To
avoid ill-effects of noise that are usually present on the digital supply rail,it is necessary to power the ADC from a separate analog power supply (see Figure 16).This also applies to other analog circuits,normally using op-amps,comparators,etc.3.5.2
Generating Analog Supply From the Digital Supply
For most of the applications,the current drawn by the analog circuitry is small compared to the digital parts and it is okay to have a single voltage regulator capable to provide enough current for both type of parts.However,you need to isolate the analog supply from the noisy digital supply rail.The simplest form of circuit for generating an analog supply from the digital rail is to use passive components such as inductors to filter out the noise components.The inductors act as low pass filters,letting the DC power supply component through,but choking the noise,which is usually at a fairly high https://www.wendangku.net/doc/5815650014.html,ing Ferrite beads is a better choice over a standard inductor.Ferrite beads have negligible parasitic capacitance;the electrical characteristics are similar to inductor.This part has a low DC resistance (DCR)(<0.1Ω)to keep the voltage drop at the lowest number.A suggestion for this part is Murata BLM21PG,which can be downloaded from the following URL:
http://search.murata.co.jp/Ceramy/CatalogAction.do?sHinnm=BLM21P221SG &sNHinnm=BLM21PG221S N1&sNhin_key=BLM21PG221SN1B &sLang=en &sParam=blm21.
In a noise-critical environment,another possibility is to use separate regulators to power the analog and digital circuitry.Close attention must be paid to the ground connection in this circumstance,since the ground connections can couple noise from the digital-to-analog circuits.
In both setups,pay attention to the regulator compensation specifications.Many regulators have sufficient compensation to ensure significant gain roll-off for the noise frequencies.However,it is always a good idea to ensure that the particular regulator you are using has internal compensation,or plan to add external compensation.This makes sure that the regulator does not oscillate.3.5.3
Core Voltage Regulator
For more information regarding the correct values of the voltage and maximum current consumption,see the Electrical Specifications section of the device-specific data manual.Note that devices like F281x are specified at 1.9V for CPU frequency of 150MHz,but 1.8V for up to 135MHz.
3.5.4Power Sequencing
For all F280x/F28xxx devices,no requirements are placed on the power up/down sequence of the various power pins to ensure the correct reset state for all the modules.However,if the 3.3V transistors in the level shifting output buffers of the I/O pins are powered prior to the 1.8/1.9V transistors,it is possible for the output buffers to turn on,causing a glitch to occur on the pin during power up.To avoid this behavior,power the V DD pins prior to or simultaneously with the V DDIO pins,ensuring that the V DD pins have reached 0.7V before the V DDIO pins reach 0.7.
NOTE:If you are planning to derive core supply (V DD )from 3.3V,you need to ensure that 3.3V is
not connected to DSC before V DD as described above.You may have to use an FET switch to achieve this.
Additionally,it is recommended that no voltage larger than a diode drop (0.7V)should be applied to any input pin prior to powering up the device.Voltages applied to pins of an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.
For F281x devices,if the 1.8V (or 1.9V)rail lags the 3.3V rail,the GPIO pins are undefined until the 1.8V rail reaches at least 1V.The C281x devices do not require this sequencing.A simple way to achieve this is described below:
Enable power to all 3.3V supply pins (V DDIO ,V DD3VFL ,V DDA1/V DDA2/V DDAIO /AVDDREFBG)and then ramp 1.8V (or 1.9V)(V DD /V DD1)supply pins.1.8V or 1.9V should not reach 0.3V until V DDIO has reached 2.5V.This ensures the reset signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the device.
The F281x devices also need to follow the power-down sequencing as described below:
During power-down,the device reset should be asserted low (8μs,minimum)before the V DD supply reaches 1.5V.This helps to keep on-chip Flash logic in reset prior to the V DDIO /V DD power supplies
ramping down.It is recommended that you use the device reset control from low-dropout (LDO)regulators or voltage supervisors to meet this constraint.LDO regulators that facilitate power-sequencing,with the aid of additional external components,can be used to meet the power sequencing requirement.For F2812eZdsp ?schematics and updates,see https://www.wendangku.net/doc/5815650014.html, .3.5.5
Total Power Requirement and Selecting Voltage Regulators
While considering the current output capacity of the voltage regulators,allow for additional current
required at the power-on as many capacitors are charged during this time.Also,some of the peripheral signals (e.g.,PWM)draw excess current during switching.This dynamic current condition exists on both the voltage rails.
If your application uses in-circuit Flash programming,consider the extra current drawn (~200mA)by the Flash circuits from 1.8V rail during the program/erase cycles.
To determine the total current,add the maximum current values for different blocks specified in the data sheets.Consider all GPIO pins as output pins and calculate the total source current.Consider a 100%margin by multiplying this total by two for specifying the voltage regulator.Strictly avoid current starvation.Finally,determine if the heat-sinks are required.
The power supply noise should be quite low.Note that the ADC ’s step-size is 0.732mV for the input
range of 0V -3V.A high value ripple on the ADC supply will result in bouncy ADC counts.The PLL jitter increases with power supply noise.Even the timing accuracy of the PWM is affected as the threshold of the transistors varies with high ripple/noise on the digital supply.Linear voltage regulators (LDO)have lower noise and high power supply rejection ratio (PSRR)compared to switching regulators (DC-DC converters).LDOs have faster response to load changes,typically 1μs;however,LDOs have lower efficiency and they can become unstable if total decoupling capacitance exceeds higher limit.
Texas Instruments ’power management portfolio offers various linear and switching regulators,reference designs/applications notes customized for F28x designs,and the power supply design support.You can find this information at the following URL:https://www.wendangku.net/doc/5815650014.html, .
20Hardware Design Guidelines for TMS320F28xx and TMS320F28xxx DSCs
SPRAAS1B –August 2011
硬件电路设计过程经验分享 (1)
献给那些刚开始或即将开始设计硬件电路的人。时光飞逝，离俺最初画第一块电路已有3年。刚刚开始接触电路板的时候，与你一样，俺充满了疑惑同时又带着些兴奋。在网上许多关于硬件电路的经验、知识让人目不暇接。像信号完整性，EMI，PS设计准会把你搞晕。别急，一切要慢慢来。 1)总体思路。 设计硬件电路，大的框架和架构要搞清楚，但要做到这一点还真不容易。有些大框架也许自己的老板、老师已经想好，自己只是把思路具体实现;但也有些要自己设计框架的，那就要搞清楚要实现什么功能，然后找找有否能实现同样或相似功能的参考电路板(要懂得尽量利用他人的成果，越是有经验的工程师越会懂得借鉴他人的成果)。 2)理解电路。 如果你找到了的参考设计，那么恭喜你，你可以节约很多时间了(包括前期设计和后期调试)。马上就copy?NO，还是先看懂理解了再说，一方面能提高我们的电路理解能力，而且能避免设计中的错误。 3)没有找到参考设计? 没关系。先确定大IC芯片，找datasheet，看其关键参数是否符合自己的要求，哪些才是自己需要的关键参数，以及能否看懂这些关键参数，都是硬件工程师的能力的体现，这也需要长期地慢慢地积累。这期间，要善于提问，因为自己不懂的东西，别人往往一句话就能点醒你，尤其是硬件设计。 4)硬件电路设计主要是三个部分，原理图，pcb，物料清单(BOM)表。 原理图设计就是将前面的思路转化为电路原理图。它很像我们教科书上的电路图。
pcb涉及到实际的电路板，它根据原理图转化而来的网表(网表是沟通原理图和pcb之间的桥梁)，而将具体的元器件的封装放置(布局)在电路板上，然后根据飞线(也叫预拉线)连接其电信号(布线)。完成了pcb布局布线后，要用到哪些元器件应该有所归纳，所以我们将用到BOM表。 5)用什么工具? Protel，也就是altimuml容易上手，在国内也比较流行，应付一般的工作已经足够，适合初入门的设计者使用。 6)to be continued...... 其实无论用简单的protel或者复杂的cadence工具，硬件设计大环节是一样的(protel上的操作类似windwos，是post-command型的;而cadence的产品concept&allegro是pre-command型的，用惯了protel，突然转向cadence的工具，会不习惯就是这个原因)。设计大环节都要有1)原理图设计。2)pcb设计。3)制作BOM 表。现在简要谈一下设计流程(步骤)： 1)原理图库建立。要将一个新元件摆放在原理图上，我们必须得建立改元件的库。库中主要定义了该新元件的管脚定义及其属性，并且以具体的图形形式来代表(我们常常看到的是一个矩形(代表其IC BODY)，周围许多短线(代表IC管脚))。protel创建库及其简单，而且因为用的人多，许多元件都能找到现成的库，这一点对使用者极为方便。应搞清楚ic body，ic pins，input pin，output pin，analog pin，digital pin，power pin等区别。 2)有了充足的库之后，就可以在原理图上画图了，按照datasheet和系统设计的要
硬件电路设计基础知识
硬件电子电路基础
第一章半导体器件 §1-1 半导体基础知识 一、什么是半导体 半导体就是导电能力介于导体和绝缘体之间的物质。（导电能力即电导率）（如：硅Si 锗Ge等＋4价元素以及化合物）
二、半导体的导电特性 本征半导体――纯净、晶体结构完整的半导体称为本征半导体。 硅和锗的共价键结构。（略） 1、半导体的导电率会在外界因素作用下发生变化 ?掺杂──管子 ?温度──热敏元件 ?光照──光敏元件等 2、半导体中的两种载流子──自由电子和空穴 ?自由电子──受束缚的电子（－） ?空穴──电子跳走以后留下的坑（＋） 三、杂质半导体──N型、P型 （前讲）掺杂可以显著地改变半导体的导电特性，从而制造出杂质半导体。 ?N型半导体（自由电子多） 掺杂为＋5价元素。如：磷；砷P──＋5价使自由电子大大增加原理：Si──＋4价P与Si形成共价键后多余了一个电子。 载流子组成： o本征激发的空穴和自由电子──数量少。 o掺杂后由P提供的自由电子──数量多。 o空穴──少子 o自由电子──多子 ?P型半导体（空穴多） 掺杂为＋3价元素。如：硼；铝使空穴大大增加 原理：Si──＋4价B与Si形成共价键后多余了一个空穴。 B──＋3价 载流子组成：
o本征激发的空穴和自由电子──数量少。 o掺杂后由B提供的空穴──数量多。 o空穴──多子 o自由电子──少子 结论：N型半导体中的多数载流子为自由电子； P型半导体中的多数载流子为空穴。 §1-2 PN结 一、PN结的基本原理 1、什么是PN结 将一块P型半导体和一块N型半导体紧密第结合在一起时，交界面两侧的那部分区域。 2、PN结的结构 分界面上的情况： P区：空穴多 N区：自由电子多 扩散运动： 多的往少的那去，并被复合掉。留下了正、负离子。 （正、负离子不能移动） 留下了一个正、负离子区──耗尽区。 由正、负离子区形成了一个内建电场（即势垒高度）。 方向：N--> P 大小：与材料和温度有关。（很小，约零点几伏）
硬件电路设计具体详解
2系统方案设计 2.1 数字示波器的工作原理 图2.1 数字示波器显示原理 数字示波器的工作原理可以用图2.1 来描述，当输入被测信号从无源探头进入到数字示波器，首先通过的是示波器的信号调理模块，由于后续的A/D模数转换器对其测量电压有一个规定的量程范围，所以，示波器的信号调理模块就是负责对输入信号的预先处理，通过放大器放大或者通过衰减网络衰减到一定合适的幅度，然后才进入A/D转换器。在这一阶段，微控制器可设置放大和衰减的倍数来让用户选择调整信号的幅度和位置范围。 在A/D采样模块阶段，信号实时在离散点采样，采样位置的信号电压转换为数字值，而这些数字值成为采样点。该处理过程称为信号数字化。A/D采样的采样时钟决定了ADC采样的频度。该速率被称为采样速率，表示为样值每秒（S/s）。A/D模数转换器最终将输入信号转换为二进制数据，传送给捕获存储区。 因为处理器的速度跟不上高速A/D模数转换器的转换速度，所以在两者之间需要添加一个高速缓存，明显，这里捕获存储区就是充当高速缓存的角色。来自ADC的采样点存储在捕获存储区，叫做波形点。几个采样点可以组成一个波形点，波形点共同组成一条波形记录，创建一条波形记录的波形点的数量称为记录长度。捕获存储区内部还应包括一个触发系统，触发系统决定记录的起始和终止点。 被测的模拟信号在显示之前要通过微处理器的处理，微处理器处理信号，包括获取信号的电压峰峰值、有效值、周期、频率、上升时间、相位、延迟、占空比、均方值等信息，然后调整显示运行。最后，信号通过显示器的显存显示在屏幕上。 2.2 数字示波器的重要技术指标 （1）频带宽度 当示波器输入不同频率的等幅正弦信号时，屏幕上显示的信号幅度下降3dB 所对应的输入信号上、下限频率之差，称为示波器的频带宽度，单位为MHz或GHz。
电路硬件设计基础
1.1电路硬件设计基础 1.1.1电路设计 硬件电路设计原理 嵌入式系统的硬件设计主要分3个步骤：设计电路原理图、生成网络表、设计印制电路板，如下图所示。 图1-1硬件设计的3个步骤 进行硬件设计开发，首先要进行原理图设计，需要将一个个元器件按一定的逻辑关系连接起来。设计一个原理图的元件来源是“原理图库”，除了元件库外还可以由用户自己增加建立新的元件，用户可以用这些元件来实现所要设计产品的逻辑功能。例如利用Protel 中的画线、总线等工具，将电路中具有电气意义的导线、符号和标识根据设计要求连接起来，构成一个完整的原理图。 原理图设计完成后要进行网络表输出。网络表是电路原理设计和印制电路板设计中的一个桥梁，它是设计工具软件自动布线的灵魂，可以从原理图中生成，也可以从印制电路板图中提取。常见的原理图输入工具都具有Verilog/VHDL网络表生成功能，这些网络表包含所有的元件及元件之间的网络连接关系。 原理图设计完成后就可进行印制电路板设计。进行印制电路板设计时，可以利用Protel 提供的包括自动布线、各种设计规则的确定、叠层的设计、布线方式的设计、信号完整性设计等强大的布线功能，完成复杂的印制电路板设计，达到系统的准确性、功能性、可靠性设计。 电路设计方法(有效步骤) 电路原理图设计不仅是整个电路设计的第一步，也是电路设计的基础。由于以后的设计工作都是以此为基础，因此电路原理图的好坏直接影响到以后的设计工作。电路原理图的具体设计步骤，如图所示。
图1-2原理图设计流程图 （1）建立元件库中没有的库元件 元件库中保存的元件只有常用元件。设计者在设计时首先碰到的问题往往就是库中没有原理图中的部分元件。这时设计者只有利用设计软件提供的元件编辑功能建立新的库元件，然后才能进行原理图设计。 当采用片上系统的设计方法时，系统电路是针对封装的引脚关系图，与传统的设计方法中采用逻辑关系的库元件不同。 （2）设置图纸属性 设计者根据实际电路的复杂程度设置图纸大小和类型。图纸属性的设置过程实际上是建立设计平台的过程。设计者只有设置好这个工作平台，才能够在上面设计符合要求的电路图。 （3）放置元件 在这个阶段，设计者根据原理图的需要，将元件从元件库中取出放置到图纸上，并根据原理图的需要进行调整，修改位置，对元件的编号、封装进行设置等，为下一步的工作打下基础。 （4）原理图布线 在这个阶段，设计者根据原理图的需要，利用设计软件提供的各种工具和指令进行布线，将工作平面上的元件用具有电气意义的导线、符号连接起来，构成一个完整的原理图。 （5）检查与校对 在该阶段，设计者利用设计软件提供的各种检测功能对所绘制的原理图进行检查与校对，以保证原理图符合电气规则，同时还应力求做到布局美观。这个过程包括校对元件、导线位置调整以及更改元件的属性等。 （6）电路分析与仿真 这一步，设计者利用原理图仿真软件或设计软件提供的强大的电路仿真功能，对原理图的性能指标进行仿真，使设计者在原理图中就能对自己设计的电路性能指标进行观察、测试，从而避免前期问题后移，造成不必要的返工。
STM32硬件电路设计注意事项
STM32的基本系统主要涉及下面几个部分： 1、电源 1)、无论是否使用模拟部分和AD部分，MCU外围出去VCC和GND，VDDA、VSSA、Vref(如果封装有该引脚)都必需要连接，不可悬空； 2)、对于每组对应的VDD和GND都应至少放置一个104的陶瓷电容用于滤波，并接该电容应放置尽量靠近MCU； 2、复位、启动选择 1)、Boot引脚与JTAG无关。其仅是用于MCU启动后，判断执行代码的起始地址； 2)、在电路设计上可能Boot引脚不会使用，但要求一定要外部连接电阻到地或电源，切不可悬空； 3、调试接口 4、ADC 1)、ADC是有工作电压的，且与MCU的工作电压不完全相同。MCU工作电压可以到2.0V～3.6V，但ADC模块工作的电压在2.4V～3.6V。设计电路时需要注意。 5、时钟 1)、STM32上电默认是使用内部高速RC时钟(HSI)启动运行，如果做外部时钟(HSE)切换，外部时钟是不会运行的。因此，判断最小系统是否工作用示波器检查OSC是否有时钟信号，是错误的方法； 2)、RTC时钟要求使用的32.768振荡器的寄生电容是6pF，这个电容区别于振荡器外部接的负载电容； 5、GPIO 1)、IO推动LED时，建议尽量考虑使用灌电流的方式。 2)、在Stop等低功耗模式下，为了更省电，通常情况下建议GPIO配置为带上拉的输出模式，输出电平由外部电路决定； 6、FSMC 1)、对应100pin或144pin,FSMC的功能与I2C是存在冲突的，如果FSMC时钟打开，I2C 1的硬件模式无法工作。这在STM32F10xxx的勘误表中是有描述的。 ST官方推荐的几大主流开发板的原理图，在画电路的时候可以做为参考依据： 1、IAR https://www.wendangku.net/doc/5815650014.html, 1)、STM32F103RBT6 点击此处下载ourdev_606049.pdf(文件大小:208K)(原文件名:IAR_STM32_SK_revB.pdf)
硬件电路设计流程系列--方案设计
平台的选择很多时候和系统选择的算法是相关的，所以如果要提高架构，平台的设计能力，得不断提高自身的算法设计，复杂度评估能力，带宽分析能力。 常用的主处理器芯片有：单片机，ASIC，RISC(DEC Alpha、ARC、ARM、MIPS、PowerPC、SPARC和SuperH )，DSP和FPGA等，这些处理器的比较在网上有很多的文章，在这里不老生常谈了，这里只提1个典型的主处理器选型案例。 比如市场上现在有很多高清网络摄像机（HD-IPNC）的设计需求，而IPNC的解决方案也层出不穷，TI的解决方案有DM355、DM365、DM368等，海思提供的方案则有Hi3512、Hi3515、Hi3520等，NXP提供的方案有PNX1700、PNX1005等。 对于HD-IPNC的主处理芯片，有几个主要的技术指标：视频分辨率，视频编码器算法，最高支持的图像抓拍分辨率，CMOS的图像预处理能力，以及网络协议栈的开发平台。 Hi3512单芯片实现720P30 编解码能力，满足高清IP Camera应用, Hi3515可实现1080P30的编解码能力，持续提升高清IP Camera的性能。 DM355单芯片实现720P30 MPEG4编解码能力，DM365单芯片实现720P30 编解码能力, DM368单芯片实现1080P30 编解码能力。 DM355是2007 Q3推出的，DM365是2009 Q1推出的，DM368是2010 Q2推出的。海思的同档次解决方案也基本上与之同时出现。 海思和TI的解决方案都是基于linux，对于网络协议栈的开发而言，开源社区的资源是没有区别的，区别的只在于芯片供应商提供的SDK开发包，两家公司的SDK离产品都有一定的距离，但是linux的网络开发并不是一个技术难点，所以并不影响产品的推广。 作为IPNC的解决方案，在720P时代，海思的解决方案相对于TI的解决方案，其优势是支持了编解码算法，而TI只支持了MPEG4的编解码算法。虽然在2008年初，MPEG4的劣势在市场上已经开始体现出来，但在当时这似乎并不影响DM355的推广。 对于最高支持的图像抓拍分辨率，海思的解决方案可以支持支持JPEG抓拍3M Pixels@5fps，DM355最高可以支持5M Pixels，虽然当时没有成功的开发成5M Pixel的抓拍（内存分配得有点儿问题，后来就不折腾了），但是至少4M Pixel 的抓拍是实现了的，而且有几个朋友已经实现了2560x1920这个接近5M Pixel 的抓拍，所以在这一点上DM355稍微胜出。 因为在高清分辨率下，CCD传感器非常昂贵，而CMOS传感器像原尺寸又做不大，导致本身在低照度下就性能欠佳的CMOS传感器的成像质量在高分辨率时变差，
硬件基础知识
第三章硬件基础知识学习 通过上一课的学习，我们貌似成功的点亮了一个LED小灯，但是还有一些知识大家还没有 彻底明白。单片机是根据硬件电路图的设计来写代码的，所以我们不仅仅要学习编程知识，还有硬件知识，也要进一步的学习，这节课我们就要来穿插介绍电路硬件知识。 3.1 电磁干扰EMI 第一个知识点，去耦电容的应用，那首先要介绍一下去耦电容的应用背景，这个背景就是电磁干扰，也就是传说中的EMI。 1、冬天的时候，尤其是空气比较干燥的内陆城市，很多朋友都有这样的经历，手触碰到电脑外壳、铁柜子等物品的时候会被电击，实际上这就是“静电放电”现象，也称之为ESD。 2、不知道有没有同学有这样的经历，早期我们使用电钻这种电机设备，并且同时在听收音机或者看电视的时候，收音机或者电视会出现杂音，这就是“快速瞬间群脉冲”的效果，也称之为EFT。 3、以前的老电脑，有的性能不是很好，带电热插拔优盘、移动硬盘等外围设备的时候，内部会产生一个百万分之一秒的电源切换，直接导致电脑出现蓝屏或者重启现象，就是热插拔的“浪涌”效果，称之为Surge... ... 电磁干扰的内容有很多，我们这里不能一一列举，但是有些内容非常重要，后边我们要一点点的了解。这些问题大家不要认为是小问题，比如一个简单的静电放电，我们用手能感觉到的静电，可能已经达到3KV以上，如果用眼睛能看得到的，至少是5KV了，只是因为 这个电压虽然很高，电量却很小，因此不会对人体造成伤害。但是我们应用的这些半导体元器件就不一样了，一旦瞬间电压过高，就有可能造成器件的损坏。而且，即使不损坏，在2、3里边介绍的两种现象，也严重干扰到我们正常使用电子设备了。 基于以上的这些问题，就诞生了电磁兼容(EMC)这个名词。这节课我们仅仅讲一下去耦
硬件电路设计基础知识
硬件电路设计基础知识 Document serial number【LGGKGB-LGG98YT-LGGT8CB-LGUT-
硬件电子电路基础
第一章半导体器件 §1-1 半导体基础知识一、什么是半导体
半导体就是导电能力介于导体和绝缘体之间的物质。（导电能力即电导率）（如：硅Si 锗Ge等＋4价元素以及化合物） 二、半导体的导电特性 本征半导体――纯净、晶体结构完整的半导体称为本征半导体。 硅和锗的共价键结构。（略） 1、半导体的导电率会在外界因素作用下发生变化 掺杂──管子 温度──热敏元件 光照──光敏元件等 2、半导体中的两种载流子──自由电子和空穴 自由电子──受束缚的电子（－） 空穴──电子跳走以后留下的坑（＋） 三、杂质半导体──N型、P型 （前讲）掺杂可以显着地改变半导体的导电特性，从而制造出杂质半导体。 N型半导体（自由电子多） 掺杂为＋5价元素。如：磷；砷 P──＋5价使自由电子大大增加 原理： Si──＋4价 P与Si形成共价键后多余了一个电子。 载流子组成：
o本征激发的空穴和自由电子──数量少。 o掺杂后由P提供的自由电子──数量多。 o空穴──少子 o自由电子──多子 P型半导体（空穴多） 掺杂为＋3价元素。如：硼；铝使空穴大大增加 原理： Si──＋4价 B与Si形成共价键后多余了一个空穴。 B──＋3价 载流子组成： o本征激发的空穴和自由电子──数量少。 o掺杂后由B提供的空穴──数量多。 o空穴──多子 o自由电子──少子 结论：N型半导体中的多数载流子为自由电子； P型半导体中的多数载流子为空穴。 §1-2 PN结 一、PN结的基本原理 1、什么是PN结 将一块P型半导体和一块N型半导体紧密第结合在一起时，交界面两侧的那部分区域。
硬件电路原理图设计审核思路和方法
硬件电路原理图设计审核思路和方法 1、详细理解设计需求，从需求中整理出电路功能模块和性能指标要 求； 2、根据功能和性能需求制定总体设计方案，对CPU进行选型，CPU 选型有以下几点要求： a）性价比高； b）容易开发：体现在硬件调试工具种类多，参考设计多，软件资源丰富，成功案例多； c）可扩展性好； 3、针对已经选定的CPU芯片，选择一个与我们需求比较接近的成功 参考设计，一般CPU生产商或他们的合作方都会对每款CPU芯片做若干开发板进行验证，比如440EP就有yosemite开发板和 bamboo开发板，我们参考得是yosemite开发板，厂家最后公开给用户的参考设计图虽说不是产品级的东西，也应该是经过严格验证的，否则也会影响到他们的芯片推广应用，纵然参考设计的外围电路有可推敲的地方，CPU本身的管脚连接使用方法也绝对是值得我们信赖的，当然如果万一出现多个参考设计某些管脚连接方式不同，可以细读CPU芯片手册和勘误表，或者找厂商确认；另外在设计之前，最好我们能外借或者购买一块选定的参考板进行软件验证，如果没问题那么硬件参考设计也是可以信赖的；但要注意一点，现在很多CPU 都有若干种启动模式，我们要选一种最适合的启动模式，或者做成兼容设计；
4、根据需求对外设功能模块进行元器件选型，元器件选型应该遵守 以下原则： a）普遍性原则：所选的元器件要被广泛使用验证过的尽量少使用冷偏芯片，减少风险； b）高性价比原则：在功能、性能、使用率都相近的情况下，尽量选择价格比较好的元器件，减少成本； c）采购方便原则：尽量选择容易买到，供货周期短的元器件； d）持续发展原则：尽量选择在可预见的时间内不会停产的元器件；e）可替代原则：尽量选择pin to pin兼容种类比较多的元器件；f）向上兼容原则：尽量选择以前老产品用过的元器件； g）资源节约原则：尽量用上元器件的全部功能和管脚； 5、对选定的CPU参考设计原理图外围电路进行修改，修改时对于每 个功能模块都要找至少3个相同外围芯片的成功参考设计，如果找到的参考设计连接方法都是完全一样的，那么基本可以放心参照设计，但即使只有一个参考设计与其他的不一样，也不能简单地少数服从多数，而是要细读芯片数据手册，深入理解那些管脚含义，多方讨论，联系芯片厂技术支持，最终确定科学、正确的连接方式，如果仍有疑义，可以做兼容设计；这是整个原理图设计过程中最关键的部分，我们必须做到以下几点： a）对于每个功能模块要尽量找到更多的成功参考设计，越难的应该越多，成功参考设计是“前人”的经验和财富，我们理当借鉴吸收，站在“前人”的肩膀上，也就提高了自己的起点；
模拟电路设计 基础知识(笔试时候容易遇到的题目)
模拟电路设计基础知识(笔试时候容易遇到的 题目) 1、最基本的如三极管曲线特性(太低极了点) 2、基本放大电路，种类，优缺点，特别是广泛采用差分结构的原因 3、反馈之类，如：负反馈的优点（带宽变大） 4、频率响应，如：怎么才算是稳定的，如何改变频响曲线的几个方法 5、锁相环电路组成，振荡器（比如用D触发器如何搭） 6、A/D电路组成,工作原理如果公司做高频电子的，可能还要RF知识，调频，鉴频鉴相之类，不一一列举太底层的MOS管物理特性感觉一般不大会作为笔试面试题，因为全是微电子物理，公式推导太罗索，除非面试出题的是个老学究 ic设计的话需要熟悉的软件adence, Synopsys, Advant，UNIX当然也要大概会操作实际工作所需要的一些技术知识(面试容易问到) 如电路的低功耗，稳定，高速如何做到，调运放，布版图注意的地方等等,一般会针对简历上你所写做过的东西具体问，肯定会问得很细（所以别把什么都写上，精通之类的词也别用太多了），这个东西各个人就不一样了，不好说什么了。 2、数字电路设计当然必问Verilog/VHDL，如设计计数器逻辑方面数字电路的卡诺图化简，时序（同步异步差异），触发器有几种（区别，优点），全加器等等比如：设计一个自动售货
机系统，卖soda水的，只能投进三种硬币，要正确的找回钱数1、画出fsm（有限状态机）2、用verilog编程，语法要符合fpga设计的要求系统方面：如果简历上还说做过cpu之类，就会问到诸如cpu如何工作，流水线之类的问题3、单片机、DSP、FPG A、嵌入式方面（从没碰过，就大概知道几个名字胡扯几句，欢迎拍砖，也欢迎牛人帮忙补充）如单片机中断几个/类型，编中断程序注意什么问题 DSP的结构（冯、诺伊曼结构吗？）嵌入式处理器类型(如ARM)，操作系统种类 （Vxworks,ucos,winCE,linux），操作系统方面偏CS方向了，在CS篇里面讲了4、信号系统基础拉氏变换与Z变换公式等类似东西，随便翻翻书把如、h(n)=-a*h(n-1)+b*δ(n) a、求h(n)的z变换 b、问该系统是否为稳定系统 c、写出F IR数字滤波器的差分方程以往各种笔试题举例利用4选1实现F(x,y,z)=xz+yz 用mos管搭出一个二输入与非门。 用传输门和倒向器搭一个边沿触发器用运算放大器组成一个10倍的放大器微波电路的匹配电阻。 名词解释，无聊的外文缩写罢了，比如PCI、EC C、DDR、interrupt、pipeline IRQ,BIOS,USB,VHDL,VLSI VCO(压控振荡器) RAM (动态随机存储器)，FIR IIR DFT(离散傅立叶变换） 或者是中文的，比如 a量化误差 b、直方图 c、白平衡共同的注
硬件电路设计基础知识.docx
硬件电子电路基础关于本课程 § 4—2乙类功率放大电路 § 4—3丙类功率放大电路 § 4—4丙类谐振倍频电路 第五章正弦波振荡器 § 5—1反馈型正弦波振荡器的工作原理 § 5— 2 LC正弦波振荡电路 § 5— 3 LC振荡器的频率稳定度 § 5—4石英晶体振荡器 § 5— 5 RC正弦波振荡器
第一章半导体器件 §1半导体基础知识 §1PN 结 §-1二极管 §1晶体三极管 §1场效应管 §1半导体基础知识 、什么是半导体半导体就是导电能力介于导体和绝缘体之间的物质。（导电能力即电导率）（如：硅Si锗Ge等+ 4价元素以及化合物） 、半导体的导电特性本征半导体一一纯净、晶体结构完整的半导体称为本征半导体。 硅和锗的共价键结构。（略）
1、半导体的导电率会在外界因素作用下发生变化 ?掺杂一一管子 *温度--- 热敏元件 ?光照——光敏元件等 2、半导体中的两种载流子一一自由电子和空穴 ?自由电子——受束缚的电子（一） ?空穴——电子跳走以后留下的坑（+ ） 三、杂质半导体——N型、P型 （前讲）掺杂可以显著地改变半导体的导电特性，从而制造出杂质半导体。 *N型半导体（自由电子多） 掺杂为+ 5价元素。女口：磷；砷P—+ 5价使自由电子大大增加原理：Si—+ 4价P与Si形成共价键后多余了一个电子。 载流子组成： o本征激发的空穴和自由电子——数量少。 o掺杂后由P提供的自由电子——数量多。 o 空穴——少子 o 自由电子------ 多子 ?P型半导体（空穴多） 掺杂为+ 3价元素。女口：硼；铝使空穴大大增加 原理：Si—+ 4价B与Si形成共价键后多余了一个空穴。 B——+ 3价 载流子组成： o本征激发的空穴和自由电子数量少。 o掺杂后由B提供的空穴——数量多。 o 空穴——多子 o 自由电子——少子
RS485硬件电路设计中需注意的问题
RS48硬件电路设计中需注意的问题 1 问题的提出 在工业控制及测量领域较为常用的网络之一就是物理层采用RS-485通信接口所组成的工控设备网络。这种通信接口可以十分方便地将许多设备组成一个控制网络。从目前解决单片机之间中长距离通信的诸多方案分析来看，RS-485总线通信模式由于具有结构简单、价格低廉、通信距离和数据传输速率适当等特点而被广泛应用于仪器仪表、智能化传感器集散控制、楼宇控制、监控报警等领域。但RS485总线存在自适应、自保护功能脆弱等缺点，如不注意一些细节的处理，常出现通信失败甚至系统瘫痪等故障，因此提高RS-485总线运行可靠性至关重要。 2 硬件电路设计中需注意的问题 图1 RS485通信接口原理 2.1 电路基本原理 某节点的硬件电路设计如图1所示，在该电路中，使用了一种RS-485接口芯片SN75LBC184，它采用单一电源Vcc，电压在＋3～＋5.5 V范围内都能正常工作。与普通的RS-485芯片相比，它不但能抗雷电的冲击而且能承受高达8 k V的静电放电冲击，片内集成4个瞬时过压保护管，可承受高达400 V的瞬态脉冲电压。因此，它能显著提高防止雷电损坏器件的可靠性。对一些环境比较恶劣的现场，可直接与传输线相接而不需要任何外加保护元件。该芯片还有一个独特的设计，当输入端开路时，其输出为高电平，这样可保证接收器输入端电缆有开路故障时，不影响系统的正常工作。另外，它的输入阻抗为RS485标准输入阻抗的2倍（≥24 kΩ），故可以在总线上连接64个收发器。芯片内部设计了限斜率驱动，使输出信号边沿不会过陡，使传输线上不会产生过多的高频分量，从而有效扼制电磁干扰。在图1中，四位一体的光电耦合器TLP521让单片机与S N75LBC184之间完全没有了电的联系，提高了工作的可靠性。基本原理为：当单片机P1.6=0时，光电耦合器的发光二极管发光，光敏三极管导通，输出高电压（＋5 V），选中RS485接口芯片的DE端，允许发送。当单片机P1.6=1时，光电耦合器的发光二极管不发光，光敏三极管不导通，输出低电压（0 V），选
硬件电路设计规范
硬件电路板设计规范 制定此《规范》的目的和出发点是为了培养硬件开发人员严谨、务实的工作作风和严肃、认真的工作态度，增强硬件开发人员的责任感和使命感，提高工作效率和开发成功率，保证产品质量。 1、深入理解设计需求，从需求中整理出电路功能模块和性能指标要求； 2、根据功能和性能需求制定总体设计方案，对CPU等主芯片进行选型，CPU 选型有以下几点要求： 1）容易采购，性价比高； 2）容易开发：体现在硬件调试工具种类多，参考设计多，软件资源丰富，成功案例多； 3）可扩展性好； 3、针对已经选定的CPU芯片，选择一个与我们需求比较接近的成功参考设计。 一般CPU生产商或他们的合作方都会对每款CPU芯片做若干开发板进行验证，厂家最后公开给用户的参考设计图虽说不是产品级的东西，也应该是经过严格验证的，否则也会影响到他们的芯片推广应用，纵然参考设计的外围电路有可推敲的地方，CPU本身的管脚连接使用方法也绝对是值得我们信赖的，当然如果万一出现多个参考设计某些管脚连接方式不同，可以细读CPU芯片手册和勘误表，或者找厂商确认；另外在设计之前，最好我们能外借或者购买一块选定的参考板进
行软件验证，如果没问题那么硬件参考设计也是可以信赖的；但要注意一点，现在很多CPU都有若干种启动模式，我们要选一种最适合的启动模式，或者做成兼容设计； 4、根据需求对外设功能模块进行元器件选型，元器件选型应该遵守以下原则： 1）普遍性原则：所选的元器件要被广泛使用验证过的尽量少使用冷、偏芯片，减少风险； 2）高性价比原则：在功能、性能、使用率都相近的情况下，尽量选择价格比较好的元器件，减少成本； 3）采购方便原则：尽量选择容易买到，供货周期短的元器件； 4）持续发展原则：尽量选择在可预见的时间内不会停产的元器件； 5）可替代原则：尽量选择pin to pin兼容种类比较多的元器件； 6）向上兼容原则：尽量选择以前老产品用过的元器件； 7）资源节约原则：尽量用上元器件的全部功能和管脚； 5、对选定的CPU参考设计原理图外围电路进行修改，修改时对于每个功能模块都要找至少3个相同外围芯片的成功参考设计，如果找到的参考设计连接方法都是完全一样的，那么基本可以放心参照设计，但即使只有一个参考设计与其他的不一样，也不能简单地少数服从多数，而是要细读芯片数据手册，深入理解那些管脚含义，多方讨论，联系芯片厂技术支持，最终确定科学、正确的连接方式，如果仍有疑义，可以做兼容设计；当然，如果所采用的成功参考设计已经是
单片机硬件电路设计
单片机应用设计
概述 单片机是一种大规模的具有计算机基本功能的单片 单片机是一种大规模的具有计算机基本功能的单片集成电路。可以与少量外围电路构成一个小而完善的计算机系统。芯片内置和外围的电路能在软件的控制下准确、迅速、高效地完成程序设计者事先规定的任务。 单片机具有体积小、功耗低、控制功能强、扩 单片机具有体积小、功耗低、控制功能强、扩展灵活、使用方便等优点，广泛应用于仪器仪表、家用电器、医用设备、航空航天、通信产品、智能玩具、汽车电子、专用设备的智能化管理及过程控制等领域。 制等领域。
单片机类型 集中指令集（CISC）和精简指令集（RISC）–采用CISC结构的单片机数据线和指令线分时复 用，即所谓冯.诺伊曼结构。它的指令丰富，功 能较强，但取指令和取数据不能同时进行，速度 受限，价格亦高。 –采用RISC结构的单片机，数据线和指令线分离 ，即所谓哈佛结构。这使得取指令和取数据可同 时进行，且由于一般指令线宽于数据线，使其指 令较同类CISC单片机指令包含更多的处理信息 ，执行效率更高，速度亦更快。同时，这种单片 机指令多为单字节，程序存储器的空间利用率大 大提高，有利于实现超小型化。
常用的几个系列单片机 MCS-51及其兼容系列： –英特尔公司的MCS-51系列单片机是目前应 用最广泛的8位单片机之一，并且ATMEL、 PHILIPS、ADI、MAXIM、LG、 SIEMENS等公司都有其兼容型号的芯片。 这个系列的单片机具有运算与寻址能力强， 存储空间大，片内集成外设丰富，功耗低等 优点，其中大部分兼容芯片都含有片内 FLASH程序存储器，价格便宜。适合应用于 仪器仪表、测控系统、嵌入系统等开发。
电路设计的基本原理和方法
电路设计的基本原理和方法 本人经过整理得出如下的电路设计方法，希望对广大电子爱好者及热衷于硬件研发的朋友有所帮助。 电子电路的设计方法 设计一个电子电路系统时，首先必须明确系统的设计任务，根据任务进行方案选择，然后对方案中的各个部分进行单元的设计，参数计算和器件选择，最后将各个部分连接在一起，画出一个符合设计要求的完整的系统电路图。 一．明确系统的设计任务要求 对系统的设计任务进行具体分析，充分了解系统的性能，指标，内容及要求，以明确系统应完成的任务。 二．方案选择 这一步的工作要求是把系统要完成的任务分配给若干个单元电路，并画出一个能表示各单元功能的整机原理框图。 方案选择的重要任务是根据掌握的知识和资料，针对系统提出的任务，要求和条件，完成系统的功能设计。在这个过程中要敢于探索，勇于创新，力争做到设计方案合理，可靠，经济，功能齐全，技术先进。并且对方案要不断进行可行性和有缺点的分析，最后设计出一个完整框图。框图必须正确反映应完成的任务和各组成部分的功能，清楚表示系统的基本组成和相互关系。 三．单元电路的设计，参数计算和期间选择 根据系统的指标和功能框图，明确各部分任务，进行各单元电路的设计，参数计算和器件选择。 1．单元电路设计 单元电路是整机的一部分，只有把各单元电路设计好才能提高整机设计水平。 每个单元电路设计前都需明确各单元电路的任务，详细拟定出单元电路的性能指标，与前后级之间的关系，分析电路的组成形式。具体设计时，可以模仿传输的先进的电路，也可以进行创新或改进，但都必须保证性能要求。而且，不仅单元电路本身要设计合理，各单元电路间也要互相配合，注意各部分的输入信号，输出信号和控制信号的关系。 2．参数计算 为保证单元电路达到功能指标要求，就需要用电子技术知识对参数进行计算。例如，放大电路中各电阻值，放大倍数的计算；振荡器中电阻，电容，振荡频率等参数的计算。只有很好的理解电路的工作原理，正确利用计算公式，计算的参数才能满足设计要求。 参数计算时，同一个电路可能有几组数据，注意选择一组能完成电路设计要求的功能，在实践中能真正可行的参数。 计算电路参数时应注意下列问题： （1）元器件的工作电流，电压，频率和功耗等参数应能满足电路指标的要求； （2）元器件的极限参数必须留有足够充裕量，一般应大于额定值的1．5倍； （3）电阻和电容的参数应选计算值附近的标称值。 3．器件选择 （1）元件的选择 阻容电阻和电容种类很多，正确选择电阻和电容是很重要的。不同的电路对电阻和电容性能要求也不同，有解电路对电容的漏电要求很严，还有些电路对电阻，电容的性能和容量要求很高。例如滤波电路中常用大容量（100ｕF～3000uF）铝电解电容，为滤掉高频通常
硬件工程师必用20个电子线路图
这20个电子线路图，硬件工程师一定用得上！ 电子技术、无线电维修及电子制造工艺技术绝不是一门容易学好、短时间内就能够掌握的学科。这门学科所涉及的方方面面很多，各方面又相互联系，作为初学者，首先要在整体上了解、初步掌握它。 无论是无线电爱好者还是维修技术人员，你能够说出电路板上那些小元件叫做什么，又有什么作用吗？如果想成为元件（芯片）级高手的话，掌握一些相关的电子知识是必不可少的。 普及与电子基础知识，拓宽思路交流，知识的积累是基础的基础，基础和基本功扎实了才能奠定攀登高峰阶梯！这就是基本功。 电子技术的历史背景： 早在两千多年前，人们就发现了电现象和磁现象。我国早在战国时期（公元前475一211年）就发明了司南。而人类对电和磁的真正认识和广泛应用、迄今还只有一百多年历史。在第一次产业革命浪潮的推动下，许多科学家对电和磁现象进行了深入细致的研究，从而取得了重大进展。人们发现带电的物体同性相斥、异性相吸，与磁学现象有类似之处。 1785年，法国物理学家库仑在总结前人对电磁现象认识的基础上，提出了后人所称的“库仑定律”,使电学与磁学现象得到了统一。 1800年，意大利物理学家伏特研制出化学电池，用人工办法获得了连续电池，为后人对电和磁关系的研究创造了首要条件。 1822年，英国的法拉第在前人所做大量工作的基础上，提出了电磁感应定律，证明了“磁”能够产生“电”,这就为发电机和电动机的原理奠定了基础。 1837年美国画家莫尔斯在前人的基础上设计出比较实用的、用电码传送信息的电报机，之后，又在华盛顿与巴尔的摩城之间建立了世界上第一条电报线路。 1876 年，美国的贝尔发明了电话，实现了人类最早的模拟通信。英国的麦克斯韦在总结前人工作基础上，提出了一套完整的“电磁理论”,表现为四个微分方程。这那就后人所称的“麦克斯韦方程组”.麦克斯韦得出结论：运动着的电荷能产生电磁辐射，形成逐渐向外传播的、看不见的电磁波。他虽然并未提出“无线电”这个名词，但他的电磁理论却已经告诉人们，“电”是能够“无线”传播的。 对模拟电路的掌握分为三个层次：
硬件电路设计流程系列
硬件电路设计流程系列--方案设计 一、硬件电路设计流程系列--硬件电路设计规范 二、硬件电路设计流程系列--方案设计(1) ：主芯片选型三、 硬件电路设计流程系列--方案设计(2) ：芯片选购 四、硬件电路设计流程系列--方案设计(3) ：功耗分析与电源设计五、 硬件电路设计流程系列--方案设计(4)：设计一个合适的系统电源 一 硬件电路设计规范 1、详细理解设计需求，从需求中整理出电路功能模块和性能指标要求； 2、根据功能和性能需求制定总体设计方案，对CPU进行选型， CPU选型有以下几点要求： a）性价比高； b）容易开发：体现在硬件调试工具种类多，参考设计多，软件资源丰富，成功案例多； c）可扩展性好； 3、针对已经选定的 CPU芯片，选择一个与我们需求比较接近的成功参考设计，一般 CPU生产商或他们的合作方都会对每款 CPU 芯片做若干开发板进行验证，比如440EP 就有yosemite 开发板和 bamboo 开发板，我们参考得是yosemite 开发板，厂家最后公开给用户的参考设计图虽说不是产品级的东西，也应该是经过严格验证的，否则也会影响到他们的芯片推广应用，纵然参考设计的外围电路有可推敲的地方，CPU 本身的管脚连接使用方法也绝对是值得我们信赖的，当然如果万一出现多个参考设计某些管脚连接方式不同，可以细读 CPU 芯片手册和勘误表，或者找厂商确认；另外在设计之前，最好我们能外借或者购买一块选定的参考板进行软件验证，如果没问题那么硬件参考设计也是可以信赖的；但要注意一点，现在很多 CPU 都有若干种启动模式，我们要选一种最适合的启动模式，或者做成兼容设计。
STM32硬件电路设计注意事项
发现最近有关STM32硬件电路设计的帖子稍有增多，也许STM32对于大家来说还算比较新的东西的缘故吧。因ST 有一份应用笔记：AN2586 “STM32F10xxx hardware development:getting started”已经有很详细的描述了，之前也就没有就STM32的硬件电路设计在论坛上罗嗦什么。这次感觉很多网友都不太爱去ST 的官方网站上更新最新的Aplication note ，其实很多设计中需要注意的事项在官方提供的应用笔记中都有提到，这里就全当做一个总结吧。也欢迎有兴趣的和我（grant_jx@https://www.wendangku.net/doc/5815650014.html, ）沟通电路设计的问题，希望大家相互学习进步，如果说错的地方，也欢迎提出。 STM32的基本系统主要涉及下面几个部分： 1、电源 1)、无论是否使用模拟部分和AD 部分，MCU 外围出去VCC 和GND ，VDDA 、VSSA 、Vref(如果封装有该引脚)都必需要连接，不可悬空； 2)、对于每组对应的VDD 和GND 都应至少放置一个104的陶瓷电容用于滤波，并接该电容应放置尽量靠近MCU ； 2、复位、启动选择 1)、Boot 引脚与JTAG 无关。其仅是用于MCU 启动后，判断执行代码的起始地址； 2)、在电路设计上可能Boot 引脚不会使用，但要求一定要外部连接电阻到地或电源，切不可悬空； 3、调试接口 4、ADC 1)、ADC 是有工作电压的，且与MCU 的工作电压不完全相同。MCU 工作电压可以到2.0V ～3.6V ，但ADC 模块工作的电压在2.4V ～3.6V 。设计电路时需要注意。 5、时钟 1)、STM32上电默认是使用内部高速RC 时钟(HSI)启动运行，如果做外部时钟(HSE)切换，外部时钟是不会运行的。因此，判断最小系统是否工作用示波器检查OSC 是否有时钟信号，是错误的方法； 2)、RTC 时钟要求使用的32.768振荡器的寄生电容是6pF ，这个电容区别于振荡器外部接的负载电容； 5、GPIO 1)、IO 推动LED 时，建议尽量考虑使用灌电流的方式。 2)、在Stop 等低功耗模式下，为了更省电，通常情况下建议GPIO 配置为带上拉的输出模式，输出电平由外部电路决定； 6、FSMC 1)、对应100pin 或144pin,FSMC 的功能与I2C 是存在冲突的，如果FSMC 时钟打开，I2C 1的硬件模式无法工作。这在STM32F10xxx 的勘误表中是有描述。 Generated by Foxit PDF Creator ? Foxit Software https://www.wendangku.net/doc/5815650014.html, For evaluation only.
产品硬件开发评审流程
文件编号： 产品硬件开发评审流程编制：审核：
文档修改历史 日期版本作者修改内容评审号变更控 制号 发布日期 01.00.000
目录 1、目的 (4) 2、适用范围 (4) 3、评审需求 (4) 4、评审计划 (4) 5、评审结果判定 (4) 6、评审流程图 (4) 7、附录 (5)
1、目的：为规范产品硬件的研发评审工作制定此硬件研发评审流程。 2、适用范围：适用公司产品硬件的研发评审。 3、评审需求： 产品硬件评审可分3部分：硬件原理图评审、PCB评审、PCBA评审。在硬件开发设计过程中，各个阶段完成后需填写硬件评审申请表提交硬件评审小组，提出评审需求。 4、评审计划： 硬件评审小组根据评审需求制定评审计划书，可参考附录及结合实际情况制定具体的评审项目。 5、评审结果判定： 硬件评审小组在制定评审计划时，需根据相应的审查项目划分权重等级，并明确评定结果的判定标准。评审不通过，需返回开发设计改良或进行风险评估，之后再重新评审。 6、评审流程图：
7、附录： 单元电路评审：针对产品硬件常规设计所涉及的单元电路进行常规性评审，审查各单元电路是否符合设计标准。请参照下表，审查通过项目请打（√），审查未通过项目请打（×）。审查硬件板未涉及到的单元电路模块可不填写。 单元电路审查一览表 审查项目审查内容审查结果审查建议 滤波电路1、审查电路中是否设计电源 滤波电路。 2、审查电路中电源滤波器的 形式是否有效，是否为单电容 型或单电感型，而未采用П形 电源滤波器。 3、对单板的П形电源滤波器 参数进行审查。 （）（） （）（） （）（） ID电路1、审查ID电路的形式是否符 合规范电路的要求。 2、审查ID电路的参数是否正 确。 3、审查ID电路是否有隔离电 阻或隔离芯片。 （）（） （）（） （）（） 复位、WDT （看门狗）电路1、硬件设计中不推荐使用可 关闭的WDT系统，即计数器清 零电路应是单稳电路而非锁存 电路。如果设计为可关闭的 WDT，刷新时应是关闭后立即开 启，不可使watchdog处于长期 关闭的状态。 2、WDT设计中，坚决不可使用 分离元件依靠电容充电实现 WDT电路。 3、在WDT设计中，计数时钟应 尽量取用本板时钟。防止因为 其他单板更换，插拔导致时钟 不正常时，本板WDT电路工作 失常。 4、上电时WDT计数器应可清 零。 5、单板设计中有无手动复位 开关。 6、设计中是否为重要芯片设 计供软件单独调试的复位口。 7、复位电路中消抖电容的容 （）（） （）（） （）（） （）（） （）（） （）（） （）（）