单片机英文中文翻译论文

A T89S52

Features

? Compatible with MCS-51 Products

? 8K Bytes of In-System Programmable (ISP) Flash Memory –Endurance: 10,000 Write/Erase Cycles

? 4.0V to 5.5V Operating Range

? Fully Static Operation: 0 Hz to 33 MHz

? Three-level Program Memory Lock

? 256 x 8-bit Internal RAM

? 32 Programmable I/O Lines

? Three 16-bit Timer/Counters

? Eight Interrupt Sources

? Full Duplex UART Serial Channel

? Low-power Idle and Power-down Modes

? Interrupt Recovery from Power-down Mode

? Watchdog Timer ? Dual Data Pointer

? Power-off Flag ? Fast Programming Time

? Flexible ISP Programming (Byte and Page Mode)

? Green (Pb/Halide-free) Packaging Option

1.Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static

logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

2.Pin Description

2.1 VCC ：Supply voltage.

2.2 GND ：Ground.

2.3 Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.

2.4 Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2), clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction

control)

P1.5 MOSI (used for In-System Programming)

P1.6 MISO (used for In-System Programming)

P1.7 SCK (used for In-System Programming)

2.5 Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.

2.6 Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table.

Port Pin Alternate Functions

P3.0RXD (serial input port)

P3.1TXD (serial output port)

P3.2INT0(external interrupt 0)

P3.3IN T1(external interrupt 1)

P3.4T0 (timer 0 external input)

P3.5T1 (timer 1 external input)

P3.6W R(external data memory write strobe)

P3.7R D(external data memory read strobe)

2.7 RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

2.8 ALE/PRO G：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PR O G) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

2.9 PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to exter-nal data memory.

2.10 E A/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

2.11 XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

2.12 XTAL2：Output from the inverting oscillator amplifier.

3.Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

3.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.

3.2 Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes

occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

4.Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.

4.1 Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET

pulse dura-tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

4.2 WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the A T89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

5. UART

The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52.

6. Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52.

7. Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2

consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.

Table 6-1. Timer 2 Operating Modes

RCLK +TCLK CP/R L2TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator X X 0 (Off) In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P

2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

7.1 Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.

7.2 Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD . Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also

causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

8. Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol-lowing equation.

The Timer can be configured for either timer or counter operation. In most applications, it is con-figured for timer operation (CP/T2= 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency).

9. Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the

Timer/Counter 2 as a clock generator, bit C/T 2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.

10. Interrupts

The A T89S52 has a total of six interrupt vectors: two external interrupts (INT0 and IN T 1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

11. Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively , of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Oscilator Frequency Clock-Out Frequency=4[65536-(RCAP2H,RCAP2L)]

12. Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

13. Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

A T89S52单片机

主要性能

?与MCS-51单片机产品兼容

? 8K字节在系统可编程Flash存储器

? 1000次擦写周期

?全静态操作：0Hz～33Hz

?三级加密程序存储器

? 32个可编程I/O口线

?三个16位定时器/计数器

?八个中断源

?全双工UART串行通道

?低功耗空闲和掉电模式

?掉电后中断可唤醒

?看门狗定时器

?双数据指针

?掉电标识符

1.功能特征描述

AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。AT89S52具有以下标准功能： 8k字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2 个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。另外，AT89S52 可降至0Hz 静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。

2.引脚功能

VCC：电源

GND: 接地

P0口： P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具

有内部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。

2.4 P1口：P1 口是一个具有内部上拉电阻的8 位双向I/O 口，p1 输出缓冲器能驱动4 个TTL 逻辑电平。对P1 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如下表所示。在flash编程和校验时，P1口接收低8位地址字节。

引脚号第二功能

P1.0 T2（定时器/计数器T2的外部计数输入），时钟输出

P1.1 T2EX（定时器/计数器T2的捕捉/重载触发信号和方向控

制）

P1.5 MOSI（在系统编程用）

P1.6 MISO（在系统编程用）

P1.7 SCK（在系统编程用）

2.5 P2口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2 输出缓冲器能驱动4 个TTL 逻辑电平。对P2 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（I IL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX @DPTR）时，P2 口送出高八位地址。在这种应用中，P2 口使用很强的内部上拉发送1。在使用8位地址（如MOVX @RI）访问外部数据存储器时，P2口输出P2锁存器的内容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。

2.6 P3口：P3 口是一个有内部上拉电阻的8 位双向I/O 口，p2 输出缓冲器能驱动4 个TTL 逻辑电平。对P3 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（I IL）。P3口亦作为AT89S52特殊功能（第二功能）使用，如下表所示。在flash编程和校验时，P3口也接收一些控制信号。

引脚号第二功能

P3.0RXD（串行输入）

P3.1TXD（串行输出）

P3.2INT0 (外部中断0)

P3.3IN T1 (外部中断1)

P3.4T0（定时器0外部输入）

P3.5T1定时器1外部输入）

P3.6W R (外部数据存储器写选通)

P3.7R D (外部数据存储器写选通)

2.7 RST：复位输入。晶振工作时，RST脚持续2 个机器周期高电平将使单片机复位。看门狗计时完成后，RST 脚输出96 个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。

2.8 ALE/PRO G：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8 位地址的输出脉冲。在flash编程时，此引脚(PR O G)也用作编程输入脉冲。在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。如果需要，通过将地址为8EH的SFR的第0位置“1”，ALE操作将无效。这一位置“1”，ALE 仅在执行MOVX 或MOVC指令时有效。否则，ALE 将被微弱拉高。这个ALE 使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处于外部执行模式下无效。

2.9 PSEN：外部程序存储器选通信号(PSEN)是外部程序存储器选通信号。当AT89S52从外部程序存储器执行外部代码时，PSEN在每个机器周期被激活两次，而在访问外部数据存储器时，PSEN将不被激活。

2.10 E A/VPP：访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令，EA必须接GND。为了执行内部程序指令，EA应该接VCC。在flash编程期间，EA也接收12伏VPP电压。

2.11 XTAL1：振荡器反相放大器和内部时钟发生电路的输入端。

2.12 XTAL2：振荡器反相放大器的输出端。

3. 存储器结构

MCS-51器件有单独的程序存储器和数据存储器。外部程序存储器和数据存储器都可以64K寻址。

3.1 程序存储器:如果EA引脚接地，程序读取只从外部存储器开始。对于

89S52，如果EA接VCC，程序读写先从内部存储器（地址为0000H～1FFFH）开始，接着从外部寻址，寻址地址为：2000H~FFFFH。

3.2 数据存储器: AT89S52 有256 字节片内数据存储器。高128 字节与特殊功能寄存器重叠。也就是说高128字节与特殊功能寄存器有相同的地址，而物理上是分开的。当一条指令访问高于7FH 的地址时，寻址方式决定CPU 访问高128 字节RAM 还是特殊功能寄存器空间。直接寻址方式访问特殊功能寄存器（SFR）。例如，下面的直接寻址指令访问0A0H（P2口）存储单元

MOV 0A0H , #data

使用间接寻址方式访问高128 字节RAM。例如，下面的间接寻址方式中，R0 内容为0A0H，访问的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。

MOV @R0 , #data

堆栈操作也是简介寻址方式。因此，高128字节数据RAM也可用于堆栈空间。

4. 看门狗定时器

WDT是一种需要软件控制的复位方式。WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器（WDTRST）构成。WDT 在默认情况下无法工作；为了激活WDT，户用必须往WDTRST 寄存器（地址：0A6H）中依次写入01EH 和0E1H。当WDT激活后，晶振工作，WDT在每个机器周期都会增加。WDT计时周期依赖于外部时钟频率。除了复位（硬件复位或WDT溢出复位），没有办法停止WDT工作。当WDT溢出，它将驱动RSR引脚一个高个电平输出。

4.1 WDT的使用

为了激活WDT，用户必须向WDTRST寄存器（地址为0A6H的SFR）依次写入0E1H 和0E1H。当WDT激活后，用户必须向WDTRST写入01EH和0E1H喂狗来避免WDT溢出。当计数达到8191(1FFFH)时，13 位计数器将会溢出，这将会复位器件。晶振正常工作、WDT激活后，每一个机器周期WDT 都会增加。为了复位WDT，用户必须向WDTRST 写入01EH 和0E1H（WDTRST 是只读寄存器）。WDT 计数器不能读或写。当WDT 计数器溢出时，将给RST 引脚产生一个复位脉冲输出，这个复位脉冲持续96个晶振周期（TOSC），其中TOSC=1/FOSC。为了很好地使用WDT，应该在一定时间内周期性写入那部分代码，以避免WDT复位。

4.2 掉电和空闲方式下的WDT

在掉电模式下，晶振停止工作，这意味这WDT也停止了工作。在这种方式下，用户不必喂狗。有两种方式可以离开掉电模式：硬件复位或通过一个激活的外部中断。通过硬件复位退出掉电模式后，用户就应该给WDT 喂狗，就如同通常

AT89S52 复位一样。通过中断退出掉电模式的情形有很大的不同。中断应持续拉低很长一段时间，使得晶振稳定。当中断拉高后，执行中断服务程序。为了防止WDT在中断保持低电平的时候复位器件，WDT 直到中断拉低后才开始工作。这就

意味着WDT 应该在中断服务程序中复位。为了确保在离开掉电模式最初的几个状态WDT不被溢出，最好在进入掉电模式前就复WDT。在进入待机模式前，特殊寄存器AUXR的WDIDLE位用来决定WDT是否继续计数。默认状态下，在待机模式下，WDIDLE＝0，WDT继续计数。为了防止WDT在待机模式下复位AT89S52，用户应该建立一个定时器，定时离开待机模式，再重新进入待机模式。

5. UART

在AT89S52 中，UART 的操作与AT89C51 和AT89C52 一样。

6. 定时器0 和定时器1

在AT89S52 中，定时器0 和定时器1 的操作与AT89C51 和AT89C52 一样。7. 定时器2

定时器2是一个16位定时/计数器，它既可以做定时器，又可以做事件计数器。其工作方式由特殊寄存器T2CON中的C/T2位选择（如表2所示）。定时器2有三种工作模式：捕捉方式、自动重载（向下或向上计数）和波特率发生器。如表3 所示，工作模式由T2CON中的相关位选择。定时器2 有2 个8位寄存器：TH2和TL2。在定时工作方式中，每个机器周期，TL2 寄存器都会加1。由于一个机器周期由12 个晶振周期构成，因此，计数频率就是晶振频率的1/12。

表3 定时器2工作模式

RCLK +TCLK CP/R L2TR2 MODE

0 0 1 16位自动重载

0 1 1 16位捕捉

1 X 1 波特率发生器

X X 0 （不用）

在计数工作方式下，寄存器在相关外部输入角T2 发生1 至0 的下降沿时增加1。在这种方式下，每个机器周期的S5P2期间采样外部输入。一个机器周期采样到高电平，而下一个周期采样到低电平，计数器将加1。在检测到跳变的这个周期的S3P1 期间，新的计数值出现在寄存器中。因为识别1－0的跳变需要2个机器周期（24个晶振周期），所以，最大的计数频率不高于晶振频率的1/24。为了确保给定的电平在改变前采样到一次，电平应该至少在一个完整的机器周期内保持不变。

7.1 捕捉方式

在捕捉模式下，通过T2CON中的EXEN2来选择两种方式。如果EXEN2=0，定时器2时一个16位定时/计数器，溢出时，对T2CON 的TF2标志置位，TF2引起中断。如果EXEN2=1，定时器2做相同的操作。除上述功能外，外部输入T2EX引脚（P1.1）1至0的下跳变也会使得TH2和TL2中的值分别捕捉到RCAP2H和RCAP2L中。除此之

外，T2EX 的跳变会引起T2CON 中的EXF2 置位。像TF2 一样，T2EX 也会引起中断。

7.2 自动重载

当定时器2 工作于16 位自动重载模式，可对其编程实现向上计数或向下计数。这一功能可以通过特殊寄存器T2MOD（见表4）中的DCEN（向下计数允许位）来实现。通过复位，DCEN 被置为0，因此，定时器2 默认为向上计数。DCEN 设置后，定时器2就可以取决于T2EX向上、向下计数。DCEN=0 时，定时器2 自动计数。通过T2CON 中的EXEN2 位可以选择两种方式。如果EXEN2=0，定时器2计数，计到0FFFFH后置位TF2溢出标志。计数溢出也使得定时器寄存器重新从RCAP2H 和RCAP2L 中加载16 位值。定时器工作于捕捉模式，RCAP2H和RCAP2L的值可以由软件预设。如果EXEN2=1，计数溢出或在外部T2EX（P1.1）引脚上的1到0的下跳变都会触发16位重载。这个跳变也置位EXF2中断标志位。置位DCEN，允许定时器2向上或向下计数。在这种模式下，T2EX引脚控制着计数的方向。T2EX上的一个逻辑1使得定时器2向上计数。定时器计到0FFFFH溢出，并置位TF2。定时器的溢出也使得RCAP2H和RCAP2L中的16位值分别加载到定时器存储器TH2和TL2中。T2EX 上的一个逻辑0 使得定时器2 向下计数。当TH2 和TL2 分别等于RCAP2H 和RCAP2L中的值的时候，计数器下溢。计数器下溢，置位TF2，并将0FFFFH加载到定时器存储器中。定时器2上溢或下溢，外部中断标志位EXF2 被锁死。在这种工作模式下，EXF2不能触发中断。

8. 波特率发生器

通过设置T2CON中的TCLK或RCLK可选择定时器2 作为波特率发生器。如果定时器2作为发送或接收波特率发生器，定时器1可用作它用，发送和接收的波特率可以不同。如图8 所示，设置RCLK 和（或）TCLK 可以使定时器2 工作于波特率产生模式。波特率产生工作模式与自动重载模式相似，因此，TH2 的翻转使得定时器2 寄存器重载被软件预置16位值的RCAP2H和RCAP2L中的值。模式1和模式3

的波特率由定时器2溢出速率决定。

定时器可设置成定时器，也可为计数器。在多数应用情况下，一般配置成定时方式（CP/T2=0）。定时器2 用于定时器操作与波特率发生器有所不同，它在每一机器周期（1/12晶振周期）都会增加；然而，作为波特率发生器，它在每一机器状态（1/2晶振周期）都会增加。

9. 可编程时钟输出

可以通过编程在P1.0 引脚输出一个占空比为50%的时钟信号。这个引脚除了常规的I/O 角外，还有两种可选择功能。它可以通过编程作为定时器/计数器2 的外部时钟输入或占空比为50%的时钟输出。当工作频率为16MHZ时，时钟输出

频率范围为61HZ 到4HZ 。为了把定时器2配置成时钟发生器，位C/T 2（T2CON.1）必须清0，位T2OE （T2MOD.1）必须置1。位TR2（T2CON.2）启动、停止定时器。时钟输出频率取决于晶振频率和定时器2捕捉寄存器（RCAP2H ，RCAP2L ）的重载值，如公式所示：

在时钟输出模式下，定时器2不会产生中断，这和定时器2用作波特率发生器一样。定时器2也可以同时用作波特率发生器和时钟产生。不过，波特率和输出时钟频率相互并不独立，它们都依赖于RCAP2H 和RCAP2L 。

10. 中断

AT89S52 有6个中断源：两个外部中断（INT0 和IN T 1），三个定时中断（定时器0、1、2）和一个串行中断。每个中断源都可以通过置位或清除特殊寄存器IE 中的相关中断允许控制位分别使得中断源有效或无效。IE 还包括一个中断允许总控制位EA ，它能一次禁止所有中断。IE.6位是不可用的。对于AT89S52，IE.5位也是不能用的。用户软件不应给这些位写1。它们为AT89系列新产品预留。定时器2可以被寄存器T2CON 中的TF2和EXF2的或逻辑触发。程序进入中断服务后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。它们的值一直到下一个周期被电路捕捉下来。然而，定时器2 的标志位TF2 在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。

11. 晶振特性

AT89S52 单片机有一个用于构成内部振荡器的反相放大器，XTAL1 和XTAL2 分别是放大器的输入、输出端。石英晶体和陶瓷谐振器都可以用来一起构成自激振荡器。从外部时钟源驱动器件的话，XTAL2 可以不接，而从XTAL1 接入。由于外部时钟信号经过二分频触发后作为外部时钟电路输入的，所以对外部时钟信号的占空比没有其它要求，最长低电平持续时间和最少高电平持续时间等还是要符合要求的。

12. 空闲模式

在空闲工作模式下，CPU 处于睡眠状态，而所有片上外部设备保持激活状态。这种状态可以通过软件产生。在这种状态下，片上RAM 和特殊功能寄存器的内容保持不变。空闲模式可以被任一个中断或硬件复位终止。由硬件复位终止空闲模式只需两个机器周期有效复位信号，在这种情况下，片上硬件禁止访问内4[65536]=?-晶振频率

时钟输出频率（RCAP2H,RCAP2L ）

部RAM，而可以访问端口引脚。空闲模式被硬件复位终止后，为了防止预想不到的写端口，激活空闲模式的那一条指令的下一条指令不应该是写端口或外部存储器。

13. 掉电模式

在掉电模式下，晶振停止工作，激活掉电模式的指令是最后一条执行指令。片上RAM和特殊功能寄存器保持原值，直到掉电模式终止。掉电模式可以通过硬件复位和外部中断退出。复位重新定义了SFR 的值，但不改变片上RAM 的值。在V CC未恢复到正常工作电压时，硬件复位不能无效，并且应保持足够长的时间以使晶振重新工作和初始化。

关于力的外文文献翻译、中英文翻译、外文翻译

五、外文资料翻译 Stress and Strain 1.Introduction to Mechanics of Materials Mechanics of materials is a branch of applied mechanics that deals with the behavior of solid bodies subjected to various types of loading. It is a field of study that i s known by a variety of names, including “strength of materials” and “mechanics of deformable bodies”. The solid bodies considered in this book include axially-loaded bars, shafts, beams, and columns, as well as structures that are assemblies of these components. Usually the objective of our analysis will be the determination of the stresses, strains, and deformations produced by the loads; if these quantities can be found for all values of load up to the failure load, then we will have obtained a complete picture of the mechanics behavior of the body. Theoretical analyses and experimental results have equally important roles in the study of mechanics of materials . On many occasion we will make logical derivations to obtain formulas and equations for predicting mechanics behavior, but at the same time we must recognize that these formulas cannot be used in a realistic way unless certain properties of the been made in the laboratory. Also , many problems of importance in engineering cannot be handled efficiently by theoretical means, and experimental measurements become a practical necessity. The historical development of mechanics of materials is a fascinating blend of both theory and experiment, with experiments pointing the way to useful results in some instances and with theory doing so in others①. Such famous men as Leonardo da Vinci(1452-1519) and Galileo Galilei (1564-1642) made experiments to adequate to determine the strength of wires , bars , and beams , although they did not develop any adequate theo ries (by today’s standards ) to explain their test results . By contrast , the famous mathematician Leonhard Euler(1707-1783) developed the mathematical theory any of columns and calculated the critical load of a column in 1744 , long before any experimental evidence existed to show the significance of his results ②. Thus , Euler’s theoretical results remained unused for many years, although today they form the basis of column theory. The importance of combining theoretical derivations with experimentally determined properties of materials will be evident theoretical derivations with experimentally determined properties of materials will be evident as we proceed with

七年级下册英语短文带中文翻译(1-12单元)

Unit 1 (sectionB 3a) Dear Student, My name is Bob . I live in Toronto , Canada , and I want a pen pal in China . I think China is a interesting country . I’m 14 years old and my brithday is in November . I can sperk English and a littie Frenth . I have a brother , Paul , and a sister , Sarah . They have pen pals in the United Kingdom and Australia . I like going to the movies with my friends and playing sports . My favorite subject in school is P.E . It’s fun . But I don’t like math. It’s too difficult! Can you wtite to me soon? Bob 亲爱的同学， 我的名字叫鲍勃，我住在加拿大的多伦多。我想在中国找个笔友。我认为中国是个非常有趣的国家。我十四岁，我的生日在九月。我能说英语和一点法语。我有一个哥哥 Paul, 和一个姐姐Sarah。他们在英国和澳大利亚有笔友。我喜 欢和我的朋友们看电影和做运动。在学校我最喜欢的科目是体育。它很有趣。但我不喜欢数学。它太难了。你能尽快给我写信吗 Bob 3b PEN PAL WANTED My name is Tom King . I’m 14 years old and I’m from Australia . I sperk English . I have a brother , Sam , and a sister , Lisa . I play soccer on weekengs . It’s my favorite sport . I like music at school . It’s fun! My favorite movte is The Long Weekend . Do you know it ? It’s an action movie . Please write and tell me about yoursrlf. 征集笔友 我的名字是汤姆~金。我14岁,我来自澳大利亚。我讲英语。我有一个哥哥, 萨姆,和一个妹妹,莉莎。我在周末踢足球，那是我最喜欢的运动。我喜欢学校的音乐课。它是有趣的!我最喜欢的电影是《这个长周末》。你知道它吗?它是一部动作片。 请写信给我,告诉我有关你的一些情况。 Unit 2 (sectionB 3a) Welcome to the Garden District Turn left on First Avenue and enjoy the city’s quiet streets and smail parks . Take a walk through the park on Center Avenue . Across from the park is an old hotel . Next to the hotel is a small house with an interesting garden . This is the benginning of the garden tour. 欢迎来到这个花园区 在第一大街左转并享受这个城市的安静街道和小公园。在中心大道上散步穿过这个公园。在公园对面是一个老旅馆。紧靠这个旅馆旁边是一个带着有趣花园的小房子。开始游历这个花园。

平面设计中英文对照外文翻译文献

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英语背诵美文30篇(翻译)

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10kV小区供配电英文文献及中文翻译

在广州甚至广东的住宅小区电气设计中,一般都会涉及到小区的高低压供配电系统的设计.如10kV高压配电系统图,低压配电系统图等等图纸一大堆.然而在真正实施过程中,供电部门(尤其是供电公司指定的所谓电力设计小公司)根本将这些图纸作为一回事,按其电脑里原有的电子档图纸将数据稍作改动以及断路器按其所好换个厂家名称便美其名曰设计(可笑不?),拿出来的图纸根本无法满足电气设计的设计意图,致使严重存在以下问题:(也不知道是职业道德问题还是根本一窍不通) 1.跟原设计的电气系统货不对板,存在与低压开关柜后出线回路严重冲突,对实际施工造成严重阻碍,经常要求设计单位改动原有电气系统图才能满足它的要求(垄断的没话说). 2.对消防负荷和非消防负荷的供电(主要在高层建筑里)应严格分回路(从母线段)都不清楚,将消防负荷和非消防负荷按一个回路出线(尤其是将电梯和消防电梯,地下室的动力合在一起等等,有的甚至将楼顶消防风机和梯间照明合在一个回路,以一个表计量). 3.系统接地保护接地型式由原设计的TN-S系统竟曲解成"TN-S-C-S"系统(室内的还需要做TN-C,好玩吧?),严格的按照所谓的"三相四线制"再做重复接地来实施,导致后续施工中存在重复浪费资源以及安全隐患等等问题.. ............................(违反建筑电气设计规范等等问题实在不好意思一一例举,给那帮人留点混饭吃的面子算了) 总之吧,在通过图纸审查后的电气设计图纸在这帮人的眼里根本不知何物,经常是完工后的高低压供配电系统已是面目全非了,能有百分之五十的保留已经是谢天谢地了. 所以.我觉得:住宅建筑电气设计,让供电部门走!大不了留点位置,让他供几个必需回路的电,爱怎么折腾让他自个怎么折腾去.. Guangzhou, Guangdong, even in the electrical design of residential quarters, generally involving high-low cell power supply system design. 10kV power distribution systems, such as maps, drawings, etc. low-voltage distribution system map a lot. But in the real implementation of the process, the power sector (especially the so-called power supply design company appointed a small company) did these drawings for one thing, according to computer drawings of the original electronic file data to make a little change, and circuit breakers by their the name of another manufacturer will be sounding good design (ridiculously?), drawing out the design simply can not meet the electrical design intent, resulting in a serious following problems: (do not know or not know nothing about ethical issues) 1. With the original design of the electrical system not meeting board, the existence and low voltage switchgear circuit after qualifying serious conflicts seriously hinder the actual construction, often require changes to the original design unit plans to meet its electrical system requirements (monopoly impress ). 2. On the fire load and fire load of non-supply (mainly in high-rise building in) should be strictly sub-loop (from the bus segment) are not clear, the fire load and fire load of non-qualifying press of a circuit (especially the elevator and fire elevator, basement, etc.

英文文献及中文翻译

毕业设计说明书 英文文献及中文翻译 学院：专 2011年6月 电子与计算机科学技术软件工程

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英语短文中英文翻译

my friend and I are taking a , we are seeing a boy sit on the chair,he is crying,we go and ask him.“what’s the matter with you” he tell us“I can’t find my dog can you help me”.“yes,I can”.And we help him find his dong .oh it stay under the big tree! 今天我和我的朋友一起去散步。突然我们看见一个男孩坐在椅子上，他哭的很伤心。我们走过去问他：“你怎么了”。他告诉我们：“我的狗不见了，你们能帮我找到它吗”。“是的，我们能帮你找到你的狗”然后我们帮助他找到了他的狗，原来是它呆在一棵大树下。 day an old man siselling a big young man comes to the elephant and begins to look at it old man goes up to him and says inhis ear,“Don't sa y anything about the elephant before I sell it,then i'll give you some money.”“All right,”says the young the old man slles the elephant,he gives the young man some money and says,“Now,can you tell me how you find the bad ears of theelephant?”“I don't find the bad ears,”says the young man.“Then why do you look at the elephant slowly?”asks the old young man answers,“Because I never see an elephant before,and I want to know what it looks like.” 一天，一个老的男人正在卖一头大象。一个年轻的男人走向大象然后开始慢慢看着它（大象），这个老的男人走向他对着他的耳朵说，“不要在我卖出它（大象）之前说关于它（大象）的事，然后我会给你一些钱。”“好的”，这个年轻的男人说。在这个老的男人卖出大象后，他给了年轻的男人一些钱并且说，“现在，你可以告诉我你是怎样知道大象的坏的耳朵了吧？”“我不知道坏的耳朵”，这个年轻的男人说。“然后为什么你慢慢的看着大象？”这个老的男人问。这个年轻的男人回答，“因为我在这之前从来没有见过大象，还有我想知道它（大象）是什么样子的。” 3.An old woman had a cat. The cat was very old; she could not run quickly, and she could not bite, because she was so old. One day the old cat saw a mouse; she jumped and caught the mouse. But she could not bite it; so the mouse got out of her mouth and ran away, because the cat could not bite it.? Then the old woman became very angry because the cat had not killed the mouse. She began to hit the cat. The cat said, "Do not hit your old servant. I have worked for you for many years, and I would work for you still, but I am too old. Do not be unkind to the old, but remember what good work the old did when they were young."? 一位老妇有只猫，这只猫很老，它跑不快了，也咬不了东西，因为它年纪太大了。一天，老猫发现一只老鼠，它跳过去抓这只老鼠，然而，它咬不住这只老鼠。因此，老鼠从它的嘴边溜掉了，因为老猫咬不了它。? 于是，老妇很生气，因为老猫没有把老鼠咬死。她开始打这只猫，猫说：“不要打你的老仆人，我已经为你服务了很多年，而且还愿意为你效劳，但是，我实在太老了，对年纪大的不

英文论文及中文翻译

International Journal of Minerals, Metallurgy and Materials Volume 17, Number 4, August 2010, Page 500 DOI: 10.1007/s12613-010-0348-y Corresponding author: Zhuan Li E-mail: li_zhuan@https://www.wendangku.net/doc/5515979335.html, ? University of Science and Technology Beijing and Springer-Verlag Berlin Heidelberg 2010 Preparation and properties of C/C-SiC brake composites fabricated by warm compacted-in situ reaction Zhuan Li, Peng Xiao, and Xiang Xiong State Key Laboratory of Powder Metallurgy, Central South University, Changsha 410083, China (Received: 12 August 2009; revised: 28 August 2009; accepted: 2 September 2009) Abstract: Carbon fibre reinforced carbon and silicon carbide dual matrix composites (C/C-SiC) were fabricated by the warm compacted-in situ reaction. The microstructure, mechanical properties, tribological properties, and wear mechanism of C/C-SiC composites at different brake speeds were investigated. The results indicate that the composites are composed of 58wt% C, 37wt% SiC, and 5wt% Si. The density and open porosity are 2.0 g·cm–3 and 10%, respectively. The C/C-SiC brake composites exhibit good mechanical properties. The flexural strength can reach up to 160 MPa, and the impact strength can reach 2.5 kJ·m–2. The C/C-SiC brake composites show excellent tribological performances. The friction coefficient is between 0.57 and 0.67 at the brake speeds from 8 to 24 m·s?1. The brake is stable, and the wear rate is less than 2.02×10?6 cm3·J?1. These results show that the C/C-SiC brake composites are the promising candidates for advanced brake and clutch systems. Keywords: C/C-SiC; ceramic matrix composites; tribological properties; microstructure [This work was financially supported by the National High-Tech Research and Development Program of China (No.2006AA03Z560) and the Graduate Degree Thesis Innovation Foundation of Central South University (No.2008yb019).] 温压-原位反应法制备C / C-SiC刹车复合材料的工艺和性能 李专，肖鹏，熊翔 粉末冶金国家重点实验室，中南大学，湖南长沙410083，中国（收稿日期：2009年8月12日修订：2009年8月28日;接受日期：2009年9月2日） 摘要：采用温压?原位反应法制备炭纤维增强炭和碳化硅双基体(C/C-SiC)复合材

中英文翻译与文献

Monolithic integrated circuit history The monolithic integrated circuit was born in the late-1970s, has experienced SCM, MCU, the SOC three big stages. SCM namely monolithic microcomputer (Single Chip Microcomputer) the stage, mainly seeks the best monolithic shape embedded system's best architecture. “the innovation pattern” obtains successfully, has established SCM and the general-purpose calculator completely different development path. In founds on the embedded system independent development path, Intel Corporation has lasting achievements. MCU namely micro controller (Micro Controller Unit) the stage, the main technological development direction is: Expands unceasingly when satisfies the embedded application, the object system request's each kind of peripheral circuit and the interface circuit, underline its object intellectualization control. It involves the domain is related with the object system, therefore, develops the MCU heavy responsibility to fall inevitably on electrical, the electronic technology factory. Looking from this angle, Intel fades out the MCU development also to have its objective factor gradually. Is developing the MCU aspect, the most famous factory family belongings count Philips Corporation. Philips Corporation by it in embedded application aspect huge superiority, MCS-51 from monolithic microcomputer rapidly expand to micro controller. Therefore, when we review the embedded system development path, do not forget Intel and the Philips historical merit. Monolithic integrated circuit is the embedded system's road of independent development, to the MCU stage development's important attribute, seeks application system's on chip maximized solution;

英语美文(带翻译)

Always will I seek the seed of triumph in every adversity 在困境中寻找成功的希望 1．There is no better school than adversity. Every defeat, every heartbreak, every loss, contains its own seed, its own lesson on how to improve my performance next time. Never again will I contribute to my downfall by refusing to face the truth and learn from my past mistakes. Because I know: gems cannot shine without polish, and I cannot perfect myself without hardship. 2．Now I know that there are no times in life when opportunity, the chance to be and do, gathers so richly about my soul as when it has to suffer cruel adversity. Then everything depends on whether I raise my head or lower it in seeking help. Whenever I am struck down, in the future, by any terrible defeat, I will always inquire of myself, after the first pain has passed how I can turn that adversity into good. What a great opportunity that moment might present… to take the bitter root I am holding and transform it into a fragrant garden of flowers. 3．Always will I seek the seed of triumph in every adversity. 1．逆境是一所最好的学校每一次打击、每一次损失。都蕴含着成功的萌芽。都教会我在下一次有更出色的表现。我再也不会逃避现实，也不会拒绝从以往的错误中获取经验，我不再因此促成自己的失败。因为我我知道，宝玉不经磨砺就不能发光，没有磨练，我也不完善自我。 2．现在我知道，灵魂倍受煎熬的时刻，也正是生命中最多选择与机会的时刻。任何事情的成败取决于我在寻求帮助时是抬起头还是低下头。无论何时，当我被可怕的失败击倒，在最初的阵痛过去之后，我都要想方设法将苦难变成好事。伟大的机遇就在这一刻闪现——这苦涩的根本必将迎来满园芬芳！ 3．我将一直在困境中寻找成功希望。 Hold Fast to Dreams 紧紧抓住梦想 1．We all have dreams. We all want to believe deep down in our souls that we have a special gift, that we can make a difference, that we can touch others in a special way, and that we can make the world a better place. 2．At one time in our lives, we all had a vision for the quality of life that we desire and deserve. Yet, for many of us, those dreams have become so shrouded in the frustrations and routines of daily life that we no longer even make an effort to accomplish them. For far too many, the dream has dissipated and with it, so has the will to shape our destinies. Many have lost that sense of certainty that creates the winner’s edge.